Commit | Line | Data |
---|---|---|
fb4562b2 | 1 | /* * CAAM control-plane driver backend |
8e8ec596 KP |
2 | * Controller-level driver, kernel property detection, initialization |
3 | * | |
281922a1 | 4 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
8e8ec596 KP |
5 | */ |
6 | ||
4776d381 | 7 | #include <linux/device.h> |
5af50730 RH |
8 | #include <linux/of_address.h> |
9 | #include <linux/of_irq.h> | |
10 | ||
8e8ec596 KP |
11 | #include "compat.h" |
12 | #include "regs.h" | |
13 | #include "intern.h" | |
14 | #include "jr.h" | |
281922a1 KP |
15 | #include "desc_constr.h" |
16 | #include "error.h" | |
8e8ec596 | 17 | |
24821c46 VM |
18 | /* |
19 | * ARM targets tend to have clock control subsystems that can | |
20 | * enable/disable clocking to our device. | |
21 | */ | |
22 | #ifdef CONFIG_ARM | |
23 | static inline struct clk *caam_drv_identify_clk(struct device *dev, | |
24 | char *clk_name) | |
25 | { | |
26 | return devm_clk_get(dev, clk_name); | |
27 | } | |
28 | #else | |
29 | static inline struct clk *caam_drv_identify_clk(struct device *dev, | |
30 | char *clk_name) | |
31 | { | |
32 | return NULL; | |
33 | } | |
34 | #endif | |
35 | ||
281922a1 KP |
36 | /* |
37 | * Descriptor to instantiate RNG State Handle 0 in normal mode and | |
38 | * load the JDKEK, TDKEK and TDSK registers | |
39 | */ | |
1005bccd | 40 | static void build_instantiation_desc(u32 *desc, int handle, int do_sk) |
281922a1 | 41 | { |
1005bccd | 42 | u32 *jump_cmd, op_flags; |
281922a1 KP |
43 | |
44 | init_job_desc(desc, 0); | |
45 | ||
1005bccd AP |
46 | op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
47 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; | |
48 | ||
281922a1 | 49 | /* INIT RNG in non-test mode */ |
1005bccd | 50 | append_operation(desc, op_flags); |
281922a1 | 51 | |
1005bccd AP |
52 | if (!handle && do_sk) { |
53 | /* | |
54 | * For SH0, Secure Keys must be generated as well | |
55 | */ | |
281922a1 | 56 | |
1005bccd AP |
57 | /* wait for done */ |
58 | jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); | |
59 | set_jump_tgt_here(desc, jump_cmd); | |
281922a1 | 60 | |
1005bccd AP |
61 | /* |
62 | * load 1 to clear written reg: | |
63 | * resets the done interrrupt and returns the RNG to idle. | |
64 | */ | |
65 | append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); | |
66 | ||
67 | /* Initialize State Handle */ | |
68 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | | |
69 | OP_ALG_AAI_RNG4_SK); | |
70 | } | |
281922a1 | 71 | |
d5e4e999 | 72 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); |
281922a1 | 73 | } |
281922a1 | 74 | |
b1f996e0 | 75 | /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ |
1005bccd | 76 | static void build_deinstantiation_desc(u32 *desc, int handle) |
b1f996e0 AP |
77 | { |
78 | init_job_desc(desc, 0); | |
281922a1 | 79 | |
b1f996e0 | 80 | /* Uninstantiate State Handle 0 */ |
281922a1 | 81 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
1005bccd | 82 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); |
b1f996e0 AP |
83 | |
84 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); | |
281922a1 KP |
85 | } |
86 | ||
04cddbfe AP |
87 | /* |
88 | * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of | |
89 | * the software (no JR/QI used). | |
90 | * @ctrldev - pointer to device | |
1005bccd AP |
91 | * @status - descriptor status, after being run |
92 | * | |
04cddbfe AP |
93 | * Return: - 0 if no error occurred |
94 | * - -ENODEV if the DECO couldn't be acquired | |
95 | * - -EAGAIN if an error occurred while executing the descriptor | |
96 | */ | |
1005bccd AP |
97 | static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, |
98 | u32 *status) | |
281922a1 | 99 | { |
997ad290 | 100 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 NNL |
101 | struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; |
102 | struct caam_deco __iomem *deco = ctrlpriv->deco; | |
997ad290 | 103 | unsigned int timeout = 100000; |
04cddbfe | 104 | u32 deco_dbg_reg, flags; |
b1f996e0 | 105 | int i; |
997ad290 | 106 | |
17157c90 | 107 | |
8f1da7b9 | 108 | if (ctrlpriv->virt_en == 1) { |
fb4562b2 | 109 | setbits32(&ctrl->deco_rsr, DECORSR_JR0); |
17157c90 | 110 | |
fb4562b2 | 111 | while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && |
8f1da7b9 HG |
112 | --timeout) |
113 | cpu_relax(); | |
114 | ||
115 | timeout = 100000; | |
116 | } | |
17157c90 | 117 | |
fb4562b2 | 118 | setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); |
997ad290 | 119 | |
fb4562b2 | 120 | while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && |
997ad290 RG |
121 | --timeout) |
122 | cpu_relax(); | |
123 | ||
124 | if (!timeout) { | |
125 | dev_err(ctrldev, "failed to acquire DECO 0\n"); | |
fb4562b2 | 126 | clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); |
04cddbfe | 127 | return -ENODEV; |
281922a1 KP |
128 | } |
129 | ||
997ad290 | 130 | for (i = 0; i < desc_len(desc); i++) |
fb4562b2 | 131 | wr_reg32(&deco->descbuf[i], *(desc + i)); |
281922a1 | 132 | |
04cddbfe AP |
133 | flags = DECO_JQCR_WHL; |
134 | /* | |
135 | * If the descriptor length is longer than 4 words, then the | |
136 | * FOUR bit in JRCTRL register must be set. | |
137 | */ | |
138 | if (desc_len(desc) >= 4) | |
139 | flags |= DECO_JQCR_FOUR; | |
140 | ||
141 | /* Instruct the DECO to execute it */ | |
fb4562b2 | 142 | wr_reg32(&deco->jr_ctl_hi, flags); |
997ad290 RG |
143 | |
144 | timeout = 10000000; | |
84cf4827 | 145 | do { |
fb4562b2 | 146 | deco_dbg_reg = rd_reg32(&deco->desc_dbg); |
84cf4827 AP |
147 | /* |
148 | * If an error occured in the descriptor, then | |
149 | * the DECO status field will be set to 0x0D | |
150 | */ | |
151 | if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == | |
152 | DESC_DBG_DECO_STAT_HOST_ERR) | |
153 | break; | |
997ad290 | 154 | cpu_relax(); |
84cf4827 | 155 | } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); |
281922a1 | 156 | |
fb4562b2 | 157 | *status = rd_reg32(&deco->op_status_hi) & |
1005bccd | 158 | DECO_OP_STATUS_HI_ERR_MASK; |
997ad290 | 159 | |
17157c90 | 160 | if (ctrlpriv->virt_en == 1) |
fb4562b2 | 161 | clrbits32(&ctrl->deco_rsr, DECORSR_JR0); |
17157c90 | 162 | |
04cddbfe | 163 | /* Mark the DECO as free */ |
fb4562b2 | 164 | clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); |
04cddbfe AP |
165 | |
166 | if (!timeout) | |
167 | return -EAGAIN; | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | /* | |
173 | * instantiate_rng - builds and executes a descriptor on DECO0, | |
174 | * which initializes the RNG block. | |
175 | * @ctrldev - pointer to device | |
1005bccd AP |
176 | * @state_handle_mask - bitmask containing the instantiation status |
177 | * for the RNG4 state handles which exist in | |
178 | * the RNG4 block: 1 if it's been instantiated | |
179 | * by an external entry, 0 otherwise. | |
180 | * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; | |
181 | * Caution: this can be done only once; if the keys need to be | |
182 | * regenerated, a POR is required | |
183 | * | |
04cddbfe AP |
184 | * Return: - 0 if no error occurred |
185 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
186 | * - -ENODEV if DECO0 couldn't be acquired | |
187 | * - -EAGAIN if an error occurred when executing the descriptor | |
188 | * f.i. there was a RNG hardware error due to not "good enough" | |
189 | * entropy being aquired. | |
190 | */ | |
1005bccd AP |
191 | static int instantiate_rng(struct device *ctrldev, int state_handle_mask, |
192 | int gen_sk) | |
04cddbfe | 193 | { |
1005bccd | 194 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 | 195 | struct caam_ctrl __iomem *ctrl; |
62743a41 | 196 | u32 *desc, status = 0, rdsta_val; |
1005bccd AP |
197 | int ret = 0, sh_idx; |
198 | ||
fb4562b2 | 199 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe AP |
200 | desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); |
201 | if (!desc) | |
202 | return -ENOMEM; | |
04cddbfe | 203 | |
1005bccd AP |
204 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
205 | /* | |
206 | * If the corresponding bit is set, this state handle | |
207 | * was initialized by somebody else, so it's left alone. | |
208 | */ | |
209 | if ((1 << sh_idx) & state_handle_mask) | |
210 | continue; | |
211 | ||
212 | /* Create the descriptor for instantiating RNG State Handle */ | |
213 | build_instantiation_desc(desc, sh_idx, gen_sk); | |
214 | ||
215 | /* Try to run it through DECO0 */ | |
216 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
217 | ||
218 | /* | |
219 | * If ret is not 0, or descriptor status is not 0, then | |
220 | * something went wrong. No need to try the next state | |
221 | * handle (if available), bail out here. | |
222 | * Also, if for some reason, the State Handle didn't get | |
223 | * instantiated although the descriptor has finished | |
224 | * without any error (HW optimizations for later | |
225 | * CAAM eras), then try again. | |
226 | */ | |
467707b2 | 227 | rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; |
62743a41 HG |
228 | if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || |
229 | !(rdsta_val & (1 << sh_idx))) | |
1005bccd AP |
230 | ret = -EAGAIN; |
231 | if (ret) | |
232 | break; | |
1005bccd AP |
233 | dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); |
234 | /* Clear the contents before recreating the descriptor */ | |
235 | memset(desc, 0x00, CAAM_CMD_SZ * 7); | |
236 | } | |
04cddbfe | 237 | |
997ad290 | 238 | kfree(desc); |
04cddbfe | 239 | |
281922a1 KP |
240 | return ret; |
241 | } | |
242 | ||
243 | /* | |
b1f996e0 AP |
244 | * deinstantiate_rng - builds and executes a descriptor on DECO0, |
245 | * which deinitializes the RNG block. | |
246 | * @ctrldev - pointer to device | |
1005bccd AP |
247 | * @state_handle_mask - bitmask containing the instantiation status |
248 | * for the RNG4 state handles which exist in | |
249 | * the RNG4 block: 1 if it's been instantiated | |
b1f996e0 AP |
250 | * |
251 | * Return: - 0 if no error occurred | |
252 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
253 | * - -ENODEV if DECO0 couldn't be acquired | |
254 | * - -EAGAIN if an error occurred when executing the descriptor | |
281922a1 | 255 | */ |
1005bccd | 256 | static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) |
b1f996e0 | 257 | { |
1005bccd AP |
258 | u32 *desc, status; |
259 | int sh_idx, ret = 0; | |
b1f996e0 AP |
260 | |
261 | desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); | |
262 | if (!desc) | |
263 | return -ENOMEM; | |
264 | ||
1005bccd AP |
265 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
266 | /* | |
267 | * If the corresponding bit is set, then it means the state | |
268 | * handle was initialized by us, and thus it needs to be | |
269 | * deintialized as well | |
270 | */ | |
271 | if ((1 << sh_idx) & state_handle_mask) { | |
272 | /* | |
273 | * Create the descriptor for deinstantating this state | |
274 | * handle | |
275 | */ | |
276 | build_deinstantiation_desc(desc, sh_idx); | |
277 | ||
278 | /* Try to run it through DECO0 */ | |
279 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
280 | ||
281 | if (ret || status) { | |
282 | dev_err(ctrldev, | |
283 | "Failed to deinstantiate RNG4 SH%d\n", | |
284 | sh_idx); | |
285 | break; | |
286 | } | |
287 | dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); | |
288 | } | |
289 | } | |
b1f996e0 AP |
290 | |
291 | kfree(desc); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
04cddbfe AP |
296 | static int caam_remove(struct platform_device *pdev) |
297 | { | |
298 | struct device *ctrldev; | |
299 | struct caam_drv_private *ctrlpriv; | |
fb4562b2 | 300 | struct caam_ctrl __iomem *ctrl; |
e558017b | 301 | int ring; |
04cddbfe AP |
302 | |
303 | ctrldev = &pdev->dev; | |
304 | ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 305 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe | 306 | |
313ea293 | 307 | /* Remove platform devices for JobRs */ |
04cddbfe | 308 | for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { |
313ea293 RG |
309 | if (ctrlpriv->jrpdev[ring]) |
310 | of_device_unregister(ctrlpriv->jrpdev[ring]); | |
04cddbfe AP |
311 | } |
312 | ||
1005bccd AP |
313 | /* De-initialize RNG state handles initialized by this driver. */ |
314 | if (ctrlpriv->rng4_sh_init) | |
315 | deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); | |
b1f996e0 | 316 | |
04cddbfe AP |
317 | /* Shut down debug views */ |
318 | #ifdef CONFIG_DEBUG_FS | |
319 | debugfs_remove_recursive(ctrlpriv->dfs_root); | |
320 | #endif | |
321 | ||
322 | /* Unmap controller region */ | |
f4ec6aa5 | 323 | iounmap(ctrl); |
04cddbfe | 324 | |
24821c46 VM |
325 | /* shut clocks off before finalizing shutdown */ |
326 | clk_disable_unprepare(ctrlpriv->caam_ipg); | |
327 | clk_disable_unprepare(ctrlpriv->caam_mem); | |
328 | clk_disable_unprepare(ctrlpriv->caam_aclk); | |
329 | clk_disable_unprepare(ctrlpriv->caam_emi_slow); | |
330 | ||
e558017b | 331 | return 0; |
281922a1 KP |
332 | } |
333 | ||
334 | /* | |
84cf4827 AP |
335 | * kick_trng - sets the various parameters for enabling the initialization |
336 | * of the RNG4 block in CAAM | |
337 | * @pdev - pointer to the platform device | |
338 | * @ent_delay - Defines the length (in system clocks) of each entropy sample. | |
281922a1 | 339 | */ |
84cf4827 | 340 | static void kick_trng(struct platform_device *pdev, int ent_delay) |
281922a1 KP |
341 | { |
342 | struct device *ctrldev = &pdev->dev; | |
343 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 344 | struct caam_ctrl __iomem *ctrl; |
281922a1 KP |
345 | struct rng4tst __iomem *r4tst; |
346 | u32 val; | |
347 | ||
fb4562b2 NNL |
348 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
349 | r4tst = &ctrl->r4tst[0]; | |
281922a1 KP |
350 | |
351 | /* put RNG4 into program mode */ | |
352 | setbits32(&r4tst->rtmctl, RTMCTL_PRGM); | |
84cf4827 AP |
353 | |
354 | /* | |
355 | * Performance-wise, it does not make sense to | |
356 | * set the delay to a value that is lower | |
357 | * than the last one that worked (i.e. the state handles | |
358 | * were instantiated properly. Thus, instead of wasting | |
359 | * time trying to set the values controlling the sample | |
360 | * frequency, the function simply returns. | |
361 | */ | |
362 | val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) | |
363 | >> RTSDCTL_ENT_DLY_SHIFT; | |
364 | if (ent_delay <= val) { | |
365 | /* put RNG4 into run mode */ | |
366 | clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); | |
367 | return; | |
368 | } | |
369 | ||
281922a1 | 370 | val = rd_reg32(&r4tst->rtsdctl); |
84cf4827 AP |
371 | val = (val & ~RTSDCTL_ENT_DLY_MASK) | |
372 | (ent_delay << RTSDCTL_ENT_DLY_SHIFT); | |
281922a1 | 373 | wr_reg32(&r4tst->rtsdctl, val); |
84cf4827 AP |
374 | /* min. freq. count, equal to 1/4 of the entropy sample length */ |
375 | wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); | |
b061f3fe AP |
376 | /* disable maximum frequency count */ |
377 | wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); | |
e5ffbfc1 AP |
378 | /* read the control register */ |
379 | val = rd_reg32(&r4tst->rtmctl); | |
380 | /* | |
381 | * select raw sampling in both entropy shifter | |
382 | * and statistical checker | |
383 | */ | |
384 | setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); | |
281922a1 | 385 | /* put RNG4 into run mode */ |
e5ffbfc1 AP |
386 | clrbits32(&val, RTMCTL_PRGM); |
387 | /* write back the control register */ | |
388 | wr_reg32(&r4tst->rtmctl, val); | |
281922a1 KP |
389 | } |
390 | ||
82c2f960 AP |
391 | /** |
392 | * caam_get_era() - Return the ERA of the SEC on SoC, based | |
883619a9 | 393 | * on "sec-era" propery in the DTS. This property is updated by u-boot. |
82c2f960 | 394 | **/ |
883619a9 | 395 | int caam_get_era(void) |
82c2f960 | 396 | { |
883619a9 | 397 | struct device_node *caam_node; |
e27513eb AP |
398 | int ret; |
399 | u32 prop; | |
400 | ||
401 | caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); | |
402 | ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); | |
403 | of_node_put(caam_node); | |
82c2f960 | 404 | |
e27513eb | 405 | return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop; |
82c2f960 AP |
406 | } |
407 | EXPORT_SYMBOL(caam_get_era); | |
408 | ||
8e8ec596 | 409 | /* Probe routine for CAAM top (controller) level */ |
2930d497 | 410 | static int caam_probe(struct platform_device *pdev) |
8e8ec596 | 411 | { |
1005bccd | 412 | int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; |
82c2f960 | 413 | u64 caam_id; |
8e8ec596 KP |
414 | struct device *dev; |
415 | struct device_node *nprop, *np; | |
416 | struct caam_ctrl __iomem *ctrl; | |
8e8ec596 | 417 | struct caam_drv_private *ctrlpriv; |
24821c46 | 418 | struct clk *clk; |
23457bc9 KP |
419 | #ifdef CONFIG_DEBUG_FS |
420 | struct caam_perfmon *perfmon; | |
421 | #endif | |
17157c90 | 422 | u32 scfgr, comp_params; |
eb1139cd | 423 | u32 cha_vid_ls; |
fb4562b2 NNL |
424 | int pg_size; |
425 | int BLOCK_OFFSET = 0; | |
8e8ec596 | 426 | |
4776d381 HS |
427 | ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private), |
428 | GFP_KERNEL); | |
8e8ec596 KP |
429 | if (!ctrlpriv) |
430 | return -ENOMEM; | |
431 | ||
432 | dev = &pdev->dev; | |
433 | dev_set_drvdata(dev, ctrlpriv); | |
434 | ctrlpriv->pdev = pdev; | |
435 | nprop = pdev->dev.of_node; | |
436 | ||
24821c46 VM |
437 | /* Enable clocking */ |
438 | clk = caam_drv_identify_clk(&pdev->dev, "ipg"); | |
439 | if (IS_ERR(clk)) { | |
440 | ret = PTR_ERR(clk); | |
441 | dev_err(&pdev->dev, | |
442 | "can't identify CAAM ipg clk: %d\n", ret); | |
443 | return -ENODEV; | |
444 | } | |
445 | ctrlpriv->caam_ipg = clk; | |
446 | ||
447 | clk = caam_drv_identify_clk(&pdev->dev, "mem"); | |
448 | if (IS_ERR(clk)) { | |
449 | ret = PTR_ERR(clk); | |
450 | dev_err(&pdev->dev, | |
451 | "can't identify CAAM mem clk: %d\n", ret); | |
452 | return -ENODEV; | |
453 | } | |
454 | ctrlpriv->caam_mem = clk; | |
455 | ||
456 | clk = caam_drv_identify_clk(&pdev->dev, "aclk"); | |
457 | if (IS_ERR(clk)) { | |
458 | ret = PTR_ERR(clk); | |
459 | dev_err(&pdev->dev, | |
460 | "can't identify CAAM aclk clk: %d\n", ret); | |
461 | return -ENODEV; | |
462 | } | |
463 | ctrlpriv->caam_aclk = clk; | |
464 | ||
465 | clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); | |
466 | if (IS_ERR(clk)) { | |
467 | ret = PTR_ERR(clk); | |
468 | dev_err(&pdev->dev, | |
469 | "can't identify CAAM emi_slow clk: %d\n", ret); | |
470 | return -ENODEV; | |
471 | } | |
472 | ctrlpriv->caam_emi_slow = clk; | |
473 | ||
474 | ret = clk_prepare_enable(ctrlpriv->caam_ipg); | |
475 | if (ret < 0) { | |
476 | dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); | |
477 | return -ENODEV; | |
478 | } | |
479 | ||
480 | ret = clk_prepare_enable(ctrlpriv->caam_mem); | |
481 | if (ret < 0) { | |
482 | dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", | |
483 | ret); | |
484 | return -ENODEV; | |
485 | } | |
486 | ||
487 | ret = clk_prepare_enable(ctrlpriv->caam_aclk); | |
488 | if (ret < 0) { | |
489 | dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); | |
490 | return -ENODEV; | |
491 | } | |
492 | ||
493 | ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); | |
494 | if (ret < 0) { | |
495 | dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", | |
496 | ret); | |
497 | return -ENODEV; | |
498 | } | |
499 | ||
8e8ec596 KP |
500 | /* Get configuration properties from device tree */ |
501 | /* First, get register page */ | |
502 | ctrl = of_iomap(nprop, 0); | |
503 | if (ctrl == NULL) { | |
504 | dev_err(dev, "caam: of_iomap() failed\n"); | |
505 | return -ENOMEM; | |
506 | } | |
fb4562b2 NNL |
507 | /* Finding the page size for using the CTPR_MS register */ |
508 | comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); | |
509 | pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; | |
8e8ec596 | 510 | |
fb4562b2 NNL |
511 | /* Allocating the BLOCK_OFFSET based on the supported page size on |
512 | * the platform | |
513 | */ | |
514 | if (pg_size == 0) | |
515 | BLOCK_OFFSET = PG_SIZE_4K; | |
516 | else | |
517 | BLOCK_OFFSET = PG_SIZE_64K; | |
518 | ||
519 | ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; | |
520 | ctrlpriv->assure = (struct caam_assurance __force *) | |
521 | ((uint8_t *)ctrl + | |
522 | BLOCK_OFFSET * ASSURE_BLOCK_NUMBER | |
523 | ); | |
524 | ctrlpriv->deco = (struct caam_deco __force *) | |
525 | ((uint8_t *)ctrl + | |
526 | BLOCK_OFFSET * DECO_BLOCK_NUMBER | |
527 | ); | |
8e8ec596 KP |
528 | |
529 | /* Get the IRQ of the controller (for security violations only) */ | |
f7578496 | 530 | ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); |
8e8ec596 KP |
531 | |
532 | /* | |
533 | * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, | |
e13af18a | 534 | * long pointers in master configuration register |
8e8ec596 | 535 | */ |
509da8fd VM |
536 | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | |
537 | MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? | |
538 | MCFGR_LONG_PTR : 0)); | |
8e8ec596 | 539 | |
17157c90 RG |
540 | /* |
541 | * Read the Compile Time paramters and SCFGR to determine | |
542 | * if Virtualization is enabled for this platform | |
543 | */ | |
fb4562b2 | 544 | scfgr = rd_reg32(&ctrl->scfgr); |
17157c90 RG |
545 | |
546 | ctrlpriv->virt_en = 0; | |
547 | if (comp_params & CTPR_MS_VIRT_EN_INCL) { | |
548 | /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or | |
549 | * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 | |
550 | */ | |
551 | if ((comp_params & CTPR_MS_VIRT_EN_POR) || | |
552 | (!(comp_params & CTPR_MS_VIRT_EN_POR) && | |
553 | (scfgr & SCFGR_VIRT_EN))) | |
554 | ctrlpriv->virt_en = 1; | |
555 | } else { | |
556 | /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ | |
557 | if (comp_params & CTPR_MS_VIRT_EN_POR) | |
558 | ctrlpriv->virt_en = 1; | |
559 | } | |
560 | ||
561 | if (ctrlpriv->virt_en == 1) | |
fb4562b2 | 562 | setbits32(&ctrl->jrstart, JRSTART_JR0_START | |
17157c90 RG |
563 | JRSTART_JR1_START | JRSTART_JR2_START | |
564 | JRSTART_JR3_START); | |
565 | ||
8e8ec596 | 566 | if (sizeof(dma_addr_t) == sizeof(u64)) |
e13af18a | 567 | if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) |
a2ac287e | 568 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); |
e13af18a | 569 | else |
a2ac287e | 570 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); |
e13af18a | 571 | else |
a2ac287e | 572 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
8e8ec596 | 573 | |
8e8ec596 KP |
574 | /* |
575 | * Detect and enable JobRs | |
576 | * First, find out how many ring spec'ed, allocate references | |
577 | * for all, then go probe each one. | |
578 | */ | |
579 | rspec = 0; | |
0a63b09d NL |
580 | for_each_available_child_of_node(nprop, np) |
581 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
582 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) | |
a0ea0f6d | 583 | rspec++; |
a0ea0f6d | 584 | |
4776d381 HS |
585 | ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev, |
586 | sizeof(struct platform_device *) * rspec, | |
587 | GFP_KERNEL); | |
313ea293 | 588 | if (ctrlpriv->jrpdev == NULL) { |
f4ec6aa5 | 589 | iounmap(ctrl); |
8e8ec596 KP |
590 | return -ENOMEM; |
591 | } | |
592 | ||
593 | ring = 0; | |
594 | ctrlpriv->total_jobrs = 0; | |
0a63b09d NL |
595 | for_each_available_child_of_node(nprop, np) |
596 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
597 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { | |
313ea293 RG |
598 | ctrlpriv->jrpdev[ring] = |
599 | of_platform_device_create(np, NULL, dev); | |
600 | if (!ctrlpriv->jrpdev[ring]) { | |
601 | pr_warn("JR%d Platform device creation error\n", | |
602 | ring); | |
603 | continue; | |
604 | } | |
fb4562b2 NNL |
605 | ctrlpriv->jr[ring] = (struct caam_job_ring __force *) |
606 | ((uint8_t *)ctrl + | |
607 | (ring + JR_BLOCK_NUMBER) * | |
608 | BLOCK_OFFSET | |
609 | ); | |
a0ea0f6d SL |
610 | ctrlpriv->total_jobrs++; |
611 | ring++; | |
fb4562b2 | 612 | } |
8e8ec596 KP |
613 | |
614 | /* Check to see if QI present. If so, enable */ | |
eb1139cd | 615 | ctrlpriv->qi_present = |
fb4562b2 | 616 | !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & |
eb1139cd | 617 | CTPR_MS_QI_MASK); |
8e8ec596 | 618 | if (ctrlpriv->qi_present) { |
fb4562b2 NNL |
619 | ctrlpriv->qi = (struct caam_queue_if __force *) |
620 | ((uint8_t *)ctrl + | |
621 | BLOCK_OFFSET * QI_BLOCK_NUMBER | |
622 | ); | |
8e8ec596 | 623 | /* This is all that's required to physically enable QI */ |
fb4562b2 | 624 | wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); |
8e8ec596 KP |
625 | } |
626 | ||
627 | /* If no QI and no rings specified, quit and go home */ | |
628 | if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { | |
629 | dev_err(dev, "no queues configured, terminating\n"); | |
630 | caam_remove(pdev); | |
631 | return -ENOMEM; | |
632 | } | |
633 | ||
fb4562b2 | 634 | cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); |
986dfbcf | 635 | |
281922a1 | 636 | /* |
986dfbcf | 637 | * If SEC has RNG version >= 4 and RNG state handle has not been |
84cf4827 | 638 | * already instantiated, do RNG instantiation |
281922a1 | 639 | */ |
eb1139cd | 640 | if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { |
1005bccd | 641 | ctrlpriv->rng4_sh_init = |
fb4562b2 | 642 | rd_reg32(&ctrl->r4tst[0].rdsta); |
1005bccd AP |
643 | /* |
644 | * If the secure keys (TDKEK, JDKEK, TDSK), were already | |
645 | * generated, signal this to the function that is instantiating | |
646 | * the state handles. An error would occur if RNG4 attempts | |
647 | * to regenerate these keys before the next POR. | |
648 | */ | |
649 | gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; | |
650 | ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; | |
84cf4827 | 651 | do { |
1005bccd | 652 | int inst_handles = |
fb4562b2 | 653 | rd_reg32(&ctrl->r4tst[0].rdsta) & |
1005bccd AP |
654 | RDSTA_IFMASK; |
655 | /* | |
656 | * If either SH were instantiated by somebody else | |
657 | * (e.g. u-boot) then it is assumed that the entropy | |
658 | * parameters are properly set and thus the function | |
659 | * setting these (kick_trng(...)) is skipped. | |
660 | * Also, if a handle was instantiated, do not change | |
661 | * the TRNG parameters. | |
662 | */ | |
663 | if (!(ctrlpriv->rng4_sh_init || inst_handles)) { | |
eeaa1724 AP |
664 | dev_info(dev, |
665 | "Entropy delay = %u\n", | |
666 | ent_delay); | |
1005bccd AP |
667 | kick_trng(pdev, ent_delay); |
668 | ent_delay += 400; | |
669 | } | |
670 | /* | |
671 | * if instantiate_rng(...) fails, the loop will rerun | |
672 | * and the kick_trng(...) function will modfiy the | |
673 | * upper and lower limits of the entropy sampling | |
674 | * interval, leading to a sucessful initialization of | |
675 | * the RNG. | |
676 | */ | |
677 | ret = instantiate_rng(dev, inst_handles, | |
678 | gen_sk); | |
eeaa1724 AP |
679 | if (ret == -EAGAIN) |
680 | /* | |
681 | * if here, the loop will rerun, | |
682 | * so don't hog the CPU | |
683 | */ | |
684 | cpu_relax(); | |
04cddbfe | 685 | } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); |
281922a1 | 686 | if (ret) { |
84cf4827 | 687 | dev_err(dev, "failed to instantiate RNG"); |
281922a1 KP |
688 | caam_remove(pdev); |
689 | return ret; | |
690 | } | |
1005bccd AP |
691 | /* |
692 | * Set handles init'ed by this module as the complement of the | |
693 | * already initialized ones | |
694 | */ | |
695 | ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; | |
575c1bd5 VG |
696 | |
697 | /* Enable RDB bit so that RNG works faster */ | |
fb4562b2 | 698 | setbits32(&ctrl->scfgr, SCFGR_RDBENABLE); |
281922a1 KP |
699 | } |
700 | ||
8e8ec596 KP |
701 | /* NOTE: RTIC detection ought to go here, around Si time */ |
702 | ||
fb4562b2 NNL |
703 | caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | |
704 | (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); | |
82c2f960 | 705 | |
8e8ec596 | 706 | /* Report "alive" for developer to see */ |
82c2f960 | 707 | dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, |
883619a9 | 708 | caam_get_era()); |
8e8ec596 KP |
709 | dev_info(dev, "job rings = %d, qi = %d\n", |
710 | ctrlpriv->total_jobrs, ctrlpriv->qi_present); | |
711 | ||
712 | #ifdef CONFIG_DEBUG_FS | |
713 | /* | |
714 | * FIXME: needs better naming distinction, as some amalgamation of | |
715 | * "caam" and nprop->full_name. The OF name isn't distinctive, | |
716 | * but does separate instances | |
717 | */ | |
718 | perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; | |
719 | ||
178f827a | 720 | ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); |
8e8ec596 KP |
721 | ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); |
722 | ||
723 | /* Controller-level - performance monitor counters */ | |
724 | ctrlpriv->ctl_rq_dequeued = | |
725 | debugfs_create_u64("rq_dequeued", | |
eda65cc6 | 726 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
727 | ctrlpriv->ctl, &perfmon->req_dequeued); |
728 | ctrlpriv->ctl_ob_enc_req = | |
729 | debugfs_create_u64("ob_rq_encrypted", | |
eda65cc6 | 730 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
731 | ctrlpriv->ctl, &perfmon->ob_enc_req); |
732 | ctrlpriv->ctl_ib_dec_req = | |
733 | debugfs_create_u64("ib_rq_decrypted", | |
eda65cc6 | 734 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
735 | ctrlpriv->ctl, &perfmon->ib_dec_req); |
736 | ctrlpriv->ctl_ob_enc_bytes = | |
737 | debugfs_create_u64("ob_bytes_encrypted", | |
eda65cc6 | 738 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
739 | ctrlpriv->ctl, &perfmon->ob_enc_bytes); |
740 | ctrlpriv->ctl_ob_prot_bytes = | |
741 | debugfs_create_u64("ob_bytes_protected", | |
eda65cc6 | 742 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
743 | ctrlpriv->ctl, &perfmon->ob_prot_bytes); |
744 | ctrlpriv->ctl_ib_dec_bytes = | |
745 | debugfs_create_u64("ib_bytes_decrypted", | |
eda65cc6 | 746 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
747 | ctrlpriv->ctl, &perfmon->ib_dec_bytes); |
748 | ctrlpriv->ctl_ib_valid_bytes = | |
749 | debugfs_create_u64("ib_bytes_validated", | |
eda65cc6 | 750 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
751 | ctrlpriv->ctl, &perfmon->ib_valid_bytes); |
752 | ||
753 | /* Controller level - global status values */ | |
754 | ctrlpriv->ctl_faultaddr = | |
755 | debugfs_create_u64("fault_addr", | |
eda65cc6 | 756 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
757 | ctrlpriv->ctl, &perfmon->faultaddr); |
758 | ctrlpriv->ctl_faultdetail = | |
759 | debugfs_create_u32("fault_detail", | |
eda65cc6 | 760 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
761 | ctrlpriv->ctl, &perfmon->faultdetail); |
762 | ctrlpriv->ctl_faultstatus = | |
763 | debugfs_create_u32("fault_status", | |
eda65cc6 | 764 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
765 | ctrlpriv->ctl, &perfmon->status); |
766 | ||
767 | /* Internal covering keys (useful in non-secure mode only) */ | |
768 | ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0]; | |
769 | ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
770 | ctrlpriv->ctl_kek = debugfs_create_blob("kek", | |
eda65cc6 | 771 | S_IRUSR | |
8e8ec596 KP |
772 | S_IRGRP | S_IROTH, |
773 | ctrlpriv->ctl, | |
774 | &ctrlpriv->ctl_kek_wrap); | |
775 | ||
776 | ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0]; | |
777 | ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
778 | ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", | |
eda65cc6 | 779 | S_IRUSR | |
8e8ec596 KP |
780 | S_IRGRP | S_IROTH, |
781 | ctrlpriv->ctl, | |
782 | &ctrlpriv->ctl_tkek_wrap); | |
783 | ||
784 | ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0]; | |
785 | ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
786 | ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", | |
eda65cc6 | 787 | S_IRUSR | |
8e8ec596 KP |
788 | S_IRGRP | S_IROTH, |
789 | ctrlpriv->ctl, | |
790 | &ctrlpriv->ctl_tdsk_wrap); | |
791 | #endif | |
792 | return 0; | |
793 | } | |
794 | ||
795 | static struct of_device_id caam_match[] = { | |
796 | { | |
54e198d4 | 797 | .compatible = "fsl,sec-v4.0", |
8e8ec596 | 798 | }, |
a0ea0f6d SL |
799 | { |
800 | .compatible = "fsl,sec4.0", | |
801 | }, | |
8e8ec596 KP |
802 | {}, |
803 | }; | |
804 | MODULE_DEVICE_TABLE(of, caam_match); | |
805 | ||
2930d497 | 806 | static struct platform_driver caam_driver = { |
8e8ec596 KP |
807 | .driver = { |
808 | .name = "caam", | |
8e8ec596 KP |
809 | .of_match_table = caam_match, |
810 | }, | |
811 | .probe = caam_probe, | |
49cfe4db | 812 | .remove = caam_remove, |
8e8ec596 KP |
813 | }; |
814 | ||
741e8c2d | 815 | module_platform_driver(caam_driver); |
8e8ec596 KP |
816 | |
817 | MODULE_LICENSE("GPL"); | |
818 | MODULE_DESCRIPTION("FSL CAAM request backend"); | |
819 | MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); |