Commit | Line | Data |
---|---|---|
fb4562b2 | 1 | /* * CAAM control-plane driver backend |
8e8ec596 KP |
2 | * Controller-level driver, kernel property detection, initialization |
3 | * | |
281922a1 | 4 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
8e8ec596 KP |
5 | */ |
6 | ||
4776d381 | 7 | #include <linux/device.h> |
5af50730 RH |
8 | #include <linux/of_address.h> |
9 | #include <linux/of_irq.h> | |
10 | ||
8e8ec596 KP |
11 | #include "compat.h" |
12 | #include "regs.h" | |
13 | #include "intern.h" | |
14 | #include "jr.h" | |
281922a1 | 15 | #include "desc_constr.h" |
1ac6b731 | 16 | #include "ctrl.h" |
8e8ec596 | 17 | |
261ea058 HG |
18 | bool caam_little_end; |
19 | EXPORT_SYMBOL(caam_little_end); | |
20 | ||
24821c46 | 21 | /* |
6c3af955 | 22 | * i.MX targets tend to have clock control subsystems that can |
24821c46 VM |
23 | * enable/disable clocking to our device. |
24 | */ | |
6c3af955 | 25 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX |
24821c46 VM |
26 | static inline struct clk *caam_drv_identify_clk(struct device *dev, |
27 | char *clk_name) | |
28 | { | |
29 | return devm_clk_get(dev, clk_name); | |
30 | } | |
31 | #else | |
32 | static inline struct clk *caam_drv_identify_clk(struct device *dev, | |
33 | char *clk_name) | |
34 | { | |
35 | return NULL; | |
36 | } | |
37 | #endif | |
38 | ||
281922a1 KP |
39 | /* |
40 | * Descriptor to instantiate RNG State Handle 0 in normal mode and | |
41 | * load the JDKEK, TDKEK and TDSK registers | |
42 | */ | |
1005bccd | 43 | static void build_instantiation_desc(u32 *desc, int handle, int do_sk) |
281922a1 | 44 | { |
1005bccd | 45 | u32 *jump_cmd, op_flags; |
281922a1 KP |
46 | |
47 | init_job_desc(desc, 0); | |
48 | ||
1005bccd AP |
49 | op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
50 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; | |
51 | ||
281922a1 | 52 | /* INIT RNG in non-test mode */ |
1005bccd | 53 | append_operation(desc, op_flags); |
281922a1 | 54 | |
1005bccd AP |
55 | if (!handle && do_sk) { |
56 | /* | |
57 | * For SH0, Secure Keys must be generated as well | |
58 | */ | |
281922a1 | 59 | |
1005bccd AP |
60 | /* wait for done */ |
61 | jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); | |
62 | set_jump_tgt_here(desc, jump_cmd); | |
281922a1 | 63 | |
1005bccd AP |
64 | /* |
65 | * load 1 to clear written reg: | |
66 | * resets the done interrrupt and returns the RNG to idle. | |
67 | */ | |
68 | append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); | |
69 | ||
70 | /* Initialize State Handle */ | |
71 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | | |
72 | OP_ALG_AAI_RNG4_SK); | |
73 | } | |
281922a1 | 74 | |
d5e4e999 | 75 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); |
281922a1 | 76 | } |
281922a1 | 77 | |
b1f996e0 | 78 | /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ |
1005bccd | 79 | static void build_deinstantiation_desc(u32 *desc, int handle) |
b1f996e0 AP |
80 | { |
81 | init_job_desc(desc, 0); | |
281922a1 | 82 | |
b1f996e0 | 83 | /* Uninstantiate State Handle 0 */ |
281922a1 | 84 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
1005bccd | 85 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); |
b1f996e0 AP |
86 | |
87 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); | |
281922a1 KP |
88 | } |
89 | ||
04cddbfe AP |
90 | /* |
91 | * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of | |
92 | * the software (no JR/QI used). | |
93 | * @ctrldev - pointer to device | |
1005bccd AP |
94 | * @status - descriptor status, after being run |
95 | * | |
04cddbfe AP |
96 | * Return: - 0 if no error occurred |
97 | * - -ENODEV if the DECO couldn't be acquired | |
98 | * - -EAGAIN if an error occurred while executing the descriptor | |
99 | */ | |
1005bccd AP |
100 | static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, |
101 | u32 *status) | |
281922a1 | 102 | { |
997ad290 | 103 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 NNL |
104 | struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; |
105 | struct caam_deco __iomem *deco = ctrlpriv->deco; | |
997ad290 | 106 | unsigned int timeout = 100000; |
04cddbfe | 107 | u32 deco_dbg_reg, flags; |
b1f996e0 | 108 | int i; |
997ad290 | 109 | |
17157c90 | 110 | |
8f1da7b9 | 111 | if (ctrlpriv->virt_en == 1) { |
261ea058 | 112 | clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); |
17157c90 | 113 | |
fb4562b2 | 114 | while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && |
8f1da7b9 HG |
115 | --timeout) |
116 | cpu_relax(); | |
117 | ||
118 | timeout = 100000; | |
119 | } | |
17157c90 | 120 | |
261ea058 | 121 | clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); |
997ad290 | 122 | |
fb4562b2 | 123 | while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && |
997ad290 RG |
124 | --timeout) |
125 | cpu_relax(); | |
126 | ||
127 | if (!timeout) { | |
128 | dev_err(ctrldev, "failed to acquire DECO 0\n"); | |
261ea058 | 129 | clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); |
04cddbfe | 130 | return -ENODEV; |
281922a1 KP |
131 | } |
132 | ||
997ad290 | 133 | for (i = 0; i < desc_len(desc); i++) |
261ea058 | 134 | wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); |
281922a1 | 135 | |
04cddbfe AP |
136 | flags = DECO_JQCR_WHL; |
137 | /* | |
138 | * If the descriptor length is longer than 4 words, then the | |
139 | * FOUR bit in JRCTRL register must be set. | |
140 | */ | |
141 | if (desc_len(desc) >= 4) | |
142 | flags |= DECO_JQCR_FOUR; | |
143 | ||
144 | /* Instruct the DECO to execute it */ | |
261ea058 | 145 | clrsetbits_32(&deco->jr_ctl_hi, 0, flags); |
997ad290 RG |
146 | |
147 | timeout = 10000000; | |
84cf4827 | 148 | do { |
fb4562b2 | 149 | deco_dbg_reg = rd_reg32(&deco->desc_dbg); |
84cf4827 AP |
150 | /* |
151 | * If an error occured in the descriptor, then | |
152 | * the DECO status field will be set to 0x0D | |
153 | */ | |
154 | if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == | |
155 | DESC_DBG_DECO_STAT_HOST_ERR) | |
156 | break; | |
997ad290 | 157 | cpu_relax(); |
84cf4827 | 158 | } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); |
281922a1 | 159 | |
fb4562b2 | 160 | *status = rd_reg32(&deco->op_status_hi) & |
1005bccd | 161 | DECO_OP_STATUS_HI_ERR_MASK; |
997ad290 | 162 | |
17157c90 | 163 | if (ctrlpriv->virt_en == 1) |
261ea058 | 164 | clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); |
17157c90 | 165 | |
04cddbfe | 166 | /* Mark the DECO as free */ |
261ea058 | 167 | clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); |
04cddbfe AP |
168 | |
169 | if (!timeout) | |
170 | return -EAGAIN; | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | /* | |
176 | * instantiate_rng - builds and executes a descriptor on DECO0, | |
177 | * which initializes the RNG block. | |
178 | * @ctrldev - pointer to device | |
1005bccd AP |
179 | * @state_handle_mask - bitmask containing the instantiation status |
180 | * for the RNG4 state handles which exist in | |
181 | * the RNG4 block: 1 if it's been instantiated | |
182 | * by an external entry, 0 otherwise. | |
183 | * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; | |
184 | * Caution: this can be done only once; if the keys need to be | |
185 | * regenerated, a POR is required | |
186 | * | |
04cddbfe AP |
187 | * Return: - 0 if no error occurred |
188 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
189 | * - -ENODEV if DECO0 couldn't be acquired | |
190 | * - -EAGAIN if an error occurred when executing the descriptor | |
191 | * f.i. there was a RNG hardware error due to not "good enough" | |
192 | * entropy being aquired. | |
193 | */ | |
1005bccd AP |
194 | static int instantiate_rng(struct device *ctrldev, int state_handle_mask, |
195 | int gen_sk) | |
04cddbfe | 196 | { |
1005bccd | 197 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 | 198 | struct caam_ctrl __iomem *ctrl; |
62743a41 | 199 | u32 *desc, status = 0, rdsta_val; |
1005bccd AP |
200 | int ret = 0, sh_idx; |
201 | ||
fb4562b2 | 202 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe AP |
203 | desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); |
204 | if (!desc) | |
205 | return -ENOMEM; | |
04cddbfe | 206 | |
1005bccd AP |
207 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
208 | /* | |
209 | * If the corresponding bit is set, this state handle | |
210 | * was initialized by somebody else, so it's left alone. | |
211 | */ | |
212 | if ((1 << sh_idx) & state_handle_mask) | |
213 | continue; | |
214 | ||
215 | /* Create the descriptor for instantiating RNG State Handle */ | |
216 | build_instantiation_desc(desc, sh_idx, gen_sk); | |
217 | ||
218 | /* Try to run it through DECO0 */ | |
219 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
220 | ||
221 | /* | |
222 | * If ret is not 0, or descriptor status is not 0, then | |
223 | * something went wrong. No need to try the next state | |
224 | * handle (if available), bail out here. | |
225 | * Also, if for some reason, the State Handle didn't get | |
226 | * instantiated although the descriptor has finished | |
227 | * without any error (HW optimizations for later | |
228 | * CAAM eras), then try again. | |
229 | */ | |
467707b2 | 230 | rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; |
62743a41 HG |
231 | if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || |
232 | !(rdsta_val & (1 << sh_idx))) | |
1005bccd AP |
233 | ret = -EAGAIN; |
234 | if (ret) | |
235 | break; | |
1005bccd AP |
236 | dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); |
237 | /* Clear the contents before recreating the descriptor */ | |
238 | memset(desc, 0x00, CAAM_CMD_SZ * 7); | |
239 | } | |
04cddbfe | 240 | |
997ad290 | 241 | kfree(desc); |
04cddbfe | 242 | |
281922a1 KP |
243 | return ret; |
244 | } | |
245 | ||
246 | /* | |
b1f996e0 AP |
247 | * deinstantiate_rng - builds and executes a descriptor on DECO0, |
248 | * which deinitializes the RNG block. | |
249 | * @ctrldev - pointer to device | |
1005bccd AP |
250 | * @state_handle_mask - bitmask containing the instantiation status |
251 | * for the RNG4 state handles which exist in | |
252 | * the RNG4 block: 1 if it's been instantiated | |
b1f996e0 AP |
253 | * |
254 | * Return: - 0 if no error occurred | |
255 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
256 | * - -ENODEV if DECO0 couldn't be acquired | |
257 | * - -EAGAIN if an error occurred when executing the descriptor | |
281922a1 | 258 | */ |
1005bccd | 259 | static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) |
b1f996e0 | 260 | { |
1005bccd AP |
261 | u32 *desc, status; |
262 | int sh_idx, ret = 0; | |
b1f996e0 AP |
263 | |
264 | desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); | |
265 | if (!desc) | |
266 | return -ENOMEM; | |
267 | ||
1005bccd AP |
268 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
269 | /* | |
270 | * If the corresponding bit is set, then it means the state | |
271 | * handle was initialized by us, and thus it needs to be | |
1cce2000 | 272 | * deinitialized as well |
1005bccd AP |
273 | */ |
274 | if ((1 << sh_idx) & state_handle_mask) { | |
275 | /* | |
276 | * Create the descriptor for deinstantating this state | |
277 | * handle | |
278 | */ | |
279 | build_deinstantiation_desc(desc, sh_idx); | |
280 | ||
281 | /* Try to run it through DECO0 */ | |
282 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
283 | ||
284 | if (ret || status) { | |
285 | dev_err(ctrldev, | |
286 | "Failed to deinstantiate RNG4 SH%d\n", | |
287 | sh_idx); | |
288 | break; | |
289 | } | |
290 | dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); | |
291 | } | |
292 | } | |
b1f996e0 AP |
293 | |
294 | kfree(desc); | |
295 | ||
296 | return ret; | |
297 | } | |
298 | ||
04cddbfe AP |
299 | static int caam_remove(struct platform_device *pdev) |
300 | { | |
301 | struct device *ctrldev; | |
302 | struct caam_drv_private *ctrlpriv; | |
fb4562b2 | 303 | struct caam_ctrl __iomem *ctrl; |
e558017b | 304 | int ring; |
04cddbfe AP |
305 | |
306 | ctrldev = &pdev->dev; | |
307 | ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 308 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe | 309 | |
313ea293 | 310 | /* Remove platform devices for JobRs */ |
4d8348d8 TA |
311 | for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) |
312 | of_device_unregister(ctrlpriv->jrpdev[ring]); | |
04cddbfe | 313 | |
1005bccd AP |
314 | /* De-initialize RNG state handles initialized by this driver. */ |
315 | if (ctrlpriv->rng4_sh_init) | |
316 | deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); | |
b1f996e0 | 317 | |
04cddbfe AP |
318 | /* Shut down debug views */ |
319 | #ifdef CONFIG_DEBUG_FS | |
320 | debugfs_remove_recursive(ctrlpriv->dfs_root); | |
321 | #endif | |
322 | ||
323 | /* Unmap controller region */ | |
f4ec6aa5 | 324 | iounmap(ctrl); |
04cddbfe | 325 | |
24821c46 VM |
326 | /* shut clocks off before finalizing shutdown */ |
327 | clk_disable_unprepare(ctrlpriv->caam_ipg); | |
328 | clk_disable_unprepare(ctrlpriv->caam_mem); | |
329 | clk_disable_unprepare(ctrlpriv->caam_aclk); | |
b80609a1 | 330 | if (ctrlpriv->caam_emi_slow) |
4e518816 | 331 | clk_disable_unprepare(ctrlpriv->caam_emi_slow); |
e558017b | 332 | return 0; |
281922a1 KP |
333 | } |
334 | ||
335 | /* | |
84cf4827 AP |
336 | * kick_trng - sets the various parameters for enabling the initialization |
337 | * of the RNG4 block in CAAM | |
338 | * @pdev - pointer to the platform device | |
339 | * @ent_delay - Defines the length (in system clocks) of each entropy sample. | |
281922a1 | 340 | */ |
84cf4827 | 341 | static void kick_trng(struct platform_device *pdev, int ent_delay) |
281922a1 KP |
342 | { |
343 | struct device *ctrldev = &pdev->dev; | |
344 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 345 | struct caam_ctrl __iomem *ctrl; |
281922a1 KP |
346 | struct rng4tst __iomem *r4tst; |
347 | u32 val; | |
348 | ||
fb4562b2 NNL |
349 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
350 | r4tst = &ctrl->r4tst[0]; | |
281922a1 KP |
351 | |
352 | /* put RNG4 into program mode */ | |
261ea058 | 353 | clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); |
84cf4827 AP |
354 | |
355 | /* | |
356 | * Performance-wise, it does not make sense to | |
357 | * set the delay to a value that is lower | |
358 | * than the last one that worked (i.e. the state handles | |
359 | * were instantiated properly. Thus, instead of wasting | |
360 | * time trying to set the values controlling the sample | |
361 | * frequency, the function simply returns. | |
362 | */ | |
363 | val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) | |
364 | >> RTSDCTL_ENT_DLY_SHIFT; | |
8439e94f HG |
365 | if (ent_delay <= val) |
366 | goto start_rng; | |
84cf4827 | 367 | |
281922a1 | 368 | val = rd_reg32(&r4tst->rtsdctl); |
84cf4827 AP |
369 | val = (val & ~RTSDCTL_ENT_DLY_MASK) | |
370 | (ent_delay << RTSDCTL_ENT_DLY_SHIFT); | |
281922a1 | 371 | wr_reg32(&r4tst->rtsdctl, val); |
84cf4827 AP |
372 | /* min. freq. count, equal to 1/4 of the entropy sample length */ |
373 | wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); | |
b061f3fe AP |
374 | /* disable maximum frequency count */ |
375 | wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); | |
e5ffbfc1 AP |
376 | /* read the control register */ |
377 | val = rd_reg32(&r4tst->rtmctl); | |
8439e94f | 378 | start_rng: |
e5ffbfc1 AP |
379 | /* |
380 | * select raw sampling in both entropy shifter | |
8439e94f | 381 | * and statistical checker; ; put RNG4 into run mode |
e5ffbfc1 | 382 | */ |
8439e94f | 383 | clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); |
281922a1 KP |
384 | } |
385 | ||
82c2f960 AP |
386 | /** |
387 | * caam_get_era() - Return the ERA of the SEC on SoC, based | |
883619a9 | 388 | * on "sec-era" propery in the DTS. This property is updated by u-boot. |
82c2f960 | 389 | **/ |
883619a9 | 390 | int caam_get_era(void) |
82c2f960 | 391 | { |
883619a9 | 392 | struct device_node *caam_node; |
e27513eb AP |
393 | int ret; |
394 | u32 prop; | |
395 | ||
396 | caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); | |
397 | ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); | |
398 | of_node_put(caam_node); | |
82c2f960 | 399 | |
287980e4 | 400 | return ret ? -ENOTSUPP : prop; |
82c2f960 AP |
401 | } |
402 | EXPORT_SYMBOL(caam_get_era); | |
403 | ||
261ea058 HG |
404 | #ifdef CONFIG_DEBUG_FS |
405 | static int caam_debugfs_u64_get(void *data, u64 *val) | |
406 | { | |
407 | *val = caam64_to_cpu(*(u64 *)data); | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static int caam_debugfs_u32_get(void *data, u64 *val) | |
412 | { | |
413 | *val = caam32_to_cpu(*(u32 *)data); | |
414 | return 0; | |
415 | } | |
416 | ||
417 | DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n"); | |
418 | DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n"); | |
419 | #endif | |
420 | ||
8e8ec596 | 421 | /* Probe routine for CAAM top (controller) level */ |
2930d497 | 422 | static int caam_probe(struct platform_device *pdev) |
8e8ec596 | 423 | { |
4d8348d8 | 424 | int ret, ring, ridx, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; |
82c2f960 | 425 | u64 caam_id; |
8e8ec596 KP |
426 | struct device *dev; |
427 | struct device_node *nprop, *np; | |
428 | struct caam_ctrl __iomem *ctrl; | |
8e8ec596 | 429 | struct caam_drv_private *ctrlpriv; |
24821c46 | 430 | struct clk *clk; |
23457bc9 KP |
431 | #ifdef CONFIG_DEBUG_FS |
432 | struct caam_perfmon *perfmon; | |
433 | #endif | |
17157c90 | 434 | u32 scfgr, comp_params; |
eb1139cd | 435 | u32 cha_vid_ls; |
fb4562b2 NNL |
436 | int pg_size; |
437 | int BLOCK_OFFSET = 0; | |
8e8ec596 | 438 | |
9c4f9733 | 439 | ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); |
8e8ec596 KP |
440 | if (!ctrlpriv) |
441 | return -ENOMEM; | |
442 | ||
443 | dev = &pdev->dev; | |
444 | dev_set_drvdata(dev, ctrlpriv); | |
445 | ctrlpriv->pdev = pdev; | |
446 | nprop = pdev->dev.of_node; | |
447 | ||
24821c46 VM |
448 | /* Enable clocking */ |
449 | clk = caam_drv_identify_clk(&pdev->dev, "ipg"); | |
450 | if (IS_ERR(clk)) { | |
451 | ret = PTR_ERR(clk); | |
452 | dev_err(&pdev->dev, | |
453 | "can't identify CAAM ipg clk: %d\n", ret); | |
a3c09550 | 454 | return ret; |
24821c46 VM |
455 | } |
456 | ctrlpriv->caam_ipg = clk; | |
457 | ||
458 | clk = caam_drv_identify_clk(&pdev->dev, "mem"); | |
459 | if (IS_ERR(clk)) { | |
460 | ret = PTR_ERR(clk); | |
461 | dev_err(&pdev->dev, | |
462 | "can't identify CAAM mem clk: %d\n", ret); | |
a3c09550 | 463 | return ret; |
24821c46 VM |
464 | } |
465 | ctrlpriv->caam_mem = clk; | |
466 | ||
467 | clk = caam_drv_identify_clk(&pdev->dev, "aclk"); | |
468 | if (IS_ERR(clk)) { | |
469 | ret = PTR_ERR(clk); | |
470 | dev_err(&pdev->dev, | |
471 | "can't identify CAAM aclk clk: %d\n", ret); | |
a3c09550 | 472 | return ret; |
24821c46 VM |
473 | } |
474 | ctrlpriv->caam_aclk = clk; | |
475 | ||
4e518816 MF |
476 | if (!of_machine_is_compatible("fsl,imx6ul")) { |
477 | clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); | |
478 | if (IS_ERR(clk)) { | |
479 | ret = PTR_ERR(clk); | |
480 | dev_err(&pdev->dev, | |
481 | "can't identify CAAM emi_slow clk: %d\n", ret); | |
482 | return ret; | |
483 | } | |
484 | ctrlpriv->caam_emi_slow = clk; | |
24821c46 | 485 | } |
24821c46 VM |
486 | |
487 | ret = clk_prepare_enable(ctrlpriv->caam_ipg); | |
488 | if (ret < 0) { | |
489 | dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); | |
31f44d15 | 490 | return ret; |
24821c46 VM |
491 | } |
492 | ||
493 | ret = clk_prepare_enable(ctrlpriv->caam_mem); | |
494 | if (ret < 0) { | |
495 | dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", | |
496 | ret); | |
31f44d15 | 497 | goto disable_caam_ipg; |
24821c46 VM |
498 | } |
499 | ||
500 | ret = clk_prepare_enable(ctrlpriv->caam_aclk); | |
501 | if (ret < 0) { | |
502 | dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); | |
31f44d15 | 503 | goto disable_caam_mem; |
24821c46 VM |
504 | } |
505 | ||
b80609a1 | 506 | if (ctrlpriv->caam_emi_slow) { |
4e518816 MF |
507 | ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); |
508 | if (ret < 0) { | |
509 | dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", | |
510 | ret); | |
511 | goto disable_caam_aclk; | |
512 | } | |
24821c46 VM |
513 | } |
514 | ||
8e8ec596 KP |
515 | /* Get configuration properties from device tree */ |
516 | /* First, get register page */ | |
517 | ctrl = of_iomap(nprop, 0); | |
518 | if (ctrl == NULL) { | |
519 | dev_err(dev, "caam: of_iomap() failed\n"); | |
31f44d15 FE |
520 | ret = -ENOMEM; |
521 | goto disable_caam_emi_slow; | |
8e8ec596 | 522 | } |
261ea058 HG |
523 | |
524 | caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & | |
525 | (CSTA_PLEND | CSTA_ALT_PLEND)); | |
526 | ||
fb4562b2 NNL |
527 | /* Finding the page size for using the CTPR_MS register */ |
528 | comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); | |
529 | pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; | |
8e8ec596 | 530 | |
fb4562b2 NNL |
531 | /* Allocating the BLOCK_OFFSET based on the supported page size on |
532 | * the platform | |
533 | */ | |
534 | if (pg_size == 0) | |
535 | BLOCK_OFFSET = PG_SIZE_4K; | |
536 | else | |
537 | BLOCK_OFFSET = PG_SIZE_64K; | |
538 | ||
8439e94f HG |
539 | ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; |
540 | ctrlpriv->assure = (struct caam_assurance __iomem __force *) | |
541 | ((__force uint8_t *)ctrl + | |
fb4562b2 NNL |
542 | BLOCK_OFFSET * ASSURE_BLOCK_NUMBER |
543 | ); | |
8439e94f HG |
544 | ctrlpriv->deco = (struct caam_deco __iomem __force *) |
545 | ((__force uint8_t *)ctrl + | |
fb4562b2 NNL |
546 | BLOCK_OFFSET * DECO_BLOCK_NUMBER |
547 | ); | |
8e8ec596 KP |
548 | |
549 | /* Get the IRQ of the controller (for security violations only) */ | |
f7578496 | 550 | ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); |
8e8ec596 KP |
551 | |
552 | /* | |
553 | * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, | |
e13af18a | 554 | * long pointers in master configuration register |
8e8ec596 | 555 | */ |
39eaf759 HG |
556 | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR, |
557 | MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF | | |
558 | MCFGR_WDENABLE | MCFGR_LARGE_BURST | | |
e7a7104e | 559 | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); |
8e8ec596 | 560 | |
17157c90 RG |
561 | /* |
562 | * Read the Compile Time paramters and SCFGR to determine | |
563 | * if Virtualization is enabled for this platform | |
564 | */ | |
fb4562b2 | 565 | scfgr = rd_reg32(&ctrl->scfgr); |
17157c90 RG |
566 | |
567 | ctrlpriv->virt_en = 0; | |
568 | if (comp_params & CTPR_MS_VIRT_EN_INCL) { | |
569 | /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or | |
570 | * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 | |
571 | */ | |
572 | if ((comp_params & CTPR_MS_VIRT_EN_POR) || | |
573 | (!(comp_params & CTPR_MS_VIRT_EN_POR) && | |
574 | (scfgr & SCFGR_VIRT_EN))) | |
575 | ctrlpriv->virt_en = 1; | |
576 | } else { | |
577 | /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ | |
578 | if (comp_params & CTPR_MS_VIRT_EN_POR) | |
579 | ctrlpriv->virt_en = 1; | |
580 | } | |
581 | ||
582 | if (ctrlpriv->virt_en == 1) | |
261ea058 HG |
583 | clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | |
584 | JRSTART_JR1_START | JRSTART_JR2_START | | |
585 | JRSTART_JR3_START); | |
17157c90 | 586 | |
b3b5fce7 | 587 | if (sizeof(dma_addr_t) == sizeof(u64)) { |
e13af18a | 588 | if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) |
b3b5fce7 | 589 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); |
e13af18a | 590 | else |
b3b5fce7 HG |
591 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); |
592 | } else { | |
593 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); | |
594 | } | |
595 | if (ret) { | |
596 | dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); | |
597 | goto iounmap_ctrl; | |
598 | } | |
8e8ec596 | 599 | |
8e8ec596 KP |
600 | /* |
601 | * Detect and enable JobRs | |
602 | * First, find out how many ring spec'ed, allocate references | |
603 | * for all, then go probe each one. | |
604 | */ | |
605 | rspec = 0; | |
0a63b09d NL |
606 | for_each_available_child_of_node(nprop, np) |
607 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
608 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) | |
a0ea0f6d | 609 | rspec++; |
a0ea0f6d | 610 | |
9c4f9733 FE |
611 | ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec, |
612 | sizeof(*ctrlpriv->jrpdev), GFP_KERNEL); | |
313ea293 | 613 | if (ctrlpriv->jrpdev == NULL) { |
31f44d15 FE |
614 | ret = -ENOMEM; |
615 | goto iounmap_ctrl; | |
8e8ec596 KP |
616 | } |
617 | ||
618 | ring = 0; | |
4d8348d8 | 619 | ridx = 0; |
8e8ec596 | 620 | ctrlpriv->total_jobrs = 0; |
0a63b09d NL |
621 | for_each_available_child_of_node(nprop, np) |
622 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
623 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { | |
313ea293 RG |
624 | ctrlpriv->jrpdev[ring] = |
625 | of_platform_device_create(np, NULL, dev); | |
626 | if (!ctrlpriv->jrpdev[ring]) { | |
4d8348d8 TA |
627 | pr_warn("JR physical index %d: Platform device creation error\n", |
628 | ridx); | |
629 | ridx++; | |
313ea293 RG |
630 | continue; |
631 | } | |
8439e94f HG |
632 | ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) |
633 | ((__force uint8_t *)ctrl + | |
4d8348d8 | 634 | (ridx + JR_BLOCK_NUMBER) * |
fb4562b2 NNL |
635 | BLOCK_OFFSET |
636 | ); | |
a0ea0f6d SL |
637 | ctrlpriv->total_jobrs++; |
638 | ring++; | |
4d8348d8 | 639 | ridx++; |
fb4562b2 | 640 | } |
8e8ec596 KP |
641 | |
642 | /* Check to see if QI present. If so, enable */ | |
eb1139cd | 643 | ctrlpriv->qi_present = |
fb4562b2 | 644 | !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & |
eb1139cd | 645 | CTPR_MS_QI_MASK); |
8e8ec596 | 646 | if (ctrlpriv->qi_present) { |
8439e94f HG |
647 | ctrlpriv->qi = (struct caam_queue_if __iomem __force *) |
648 | ((__force uint8_t *)ctrl + | |
fb4562b2 NNL |
649 | BLOCK_OFFSET * QI_BLOCK_NUMBER |
650 | ); | |
8e8ec596 | 651 | /* This is all that's required to physically enable QI */ |
fb4562b2 | 652 | wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); |
8e8ec596 KP |
653 | } |
654 | ||
655 | /* If no QI and no rings specified, quit and go home */ | |
656 | if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { | |
657 | dev_err(dev, "no queues configured, terminating\n"); | |
31f44d15 FE |
658 | ret = -ENOMEM; |
659 | goto caam_remove; | |
8e8ec596 KP |
660 | } |
661 | ||
fb4562b2 | 662 | cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); |
986dfbcf | 663 | |
281922a1 | 664 | /* |
986dfbcf | 665 | * If SEC has RNG version >= 4 and RNG state handle has not been |
84cf4827 | 666 | * already instantiated, do RNG instantiation |
281922a1 | 667 | */ |
eb1139cd | 668 | if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { |
1005bccd | 669 | ctrlpriv->rng4_sh_init = |
fb4562b2 | 670 | rd_reg32(&ctrl->r4tst[0].rdsta); |
1005bccd AP |
671 | /* |
672 | * If the secure keys (TDKEK, JDKEK, TDSK), were already | |
673 | * generated, signal this to the function that is instantiating | |
674 | * the state handles. An error would occur if RNG4 attempts | |
675 | * to regenerate these keys before the next POR. | |
676 | */ | |
677 | gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; | |
678 | ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; | |
84cf4827 | 679 | do { |
1005bccd | 680 | int inst_handles = |
fb4562b2 | 681 | rd_reg32(&ctrl->r4tst[0].rdsta) & |
1005bccd AP |
682 | RDSTA_IFMASK; |
683 | /* | |
684 | * If either SH were instantiated by somebody else | |
685 | * (e.g. u-boot) then it is assumed that the entropy | |
686 | * parameters are properly set and thus the function | |
687 | * setting these (kick_trng(...)) is skipped. | |
688 | * Also, if a handle was instantiated, do not change | |
689 | * the TRNG parameters. | |
690 | */ | |
691 | if (!(ctrlpriv->rng4_sh_init || inst_handles)) { | |
eeaa1724 AP |
692 | dev_info(dev, |
693 | "Entropy delay = %u\n", | |
694 | ent_delay); | |
1005bccd AP |
695 | kick_trng(pdev, ent_delay); |
696 | ent_delay += 400; | |
697 | } | |
698 | /* | |
699 | * if instantiate_rng(...) fails, the loop will rerun | |
700 | * and the kick_trng(...) function will modfiy the | |
701 | * upper and lower limits of the entropy sampling | |
702 | * interval, leading to a sucessful initialization of | |
703 | * the RNG. | |
704 | */ | |
705 | ret = instantiate_rng(dev, inst_handles, | |
706 | gen_sk); | |
eeaa1724 AP |
707 | if (ret == -EAGAIN) |
708 | /* | |
709 | * if here, the loop will rerun, | |
710 | * so don't hog the CPU | |
711 | */ | |
712 | cpu_relax(); | |
04cddbfe | 713 | } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); |
281922a1 | 714 | if (ret) { |
84cf4827 | 715 | dev_err(dev, "failed to instantiate RNG"); |
31f44d15 | 716 | goto caam_remove; |
281922a1 | 717 | } |
1005bccd AP |
718 | /* |
719 | * Set handles init'ed by this module as the complement of the | |
720 | * already initialized ones | |
721 | */ | |
722 | ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; | |
575c1bd5 VG |
723 | |
724 | /* Enable RDB bit so that RNG works faster */ | |
261ea058 | 725 | clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); |
281922a1 KP |
726 | } |
727 | ||
8e8ec596 KP |
728 | /* NOTE: RTIC detection ought to go here, around Si time */ |
729 | ||
fb4562b2 NNL |
730 | caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | |
731 | (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); | |
82c2f960 | 732 | |
8e8ec596 | 733 | /* Report "alive" for developer to see */ |
82c2f960 | 734 | dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, |
883619a9 | 735 | caam_get_era()); |
8e8ec596 KP |
736 | dev_info(dev, "job rings = %d, qi = %d\n", |
737 | ctrlpriv->total_jobrs, ctrlpriv->qi_present); | |
738 | ||
739 | #ifdef CONFIG_DEBUG_FS | |
740 | /* | |
741 | * FIXME: needs better naming distinction, as some amalgamation of | |
742 | * "caam" and nprop->full_name. The OF name isn't distinctive, | |
743 | * but does separate instances | |
744 | */ | |
745 | perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; | |
746 | ||
178f827a | 747 | ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); |
8e8ec596 KP |
748 | ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); |
749 | ||
750 | /* Controller-level - performance monitor counters */ | |
261ea058 | 751 | |
8e8ec596 | 752 | ctrlpriv->ctl_rq_dequeued = |
261ea058 HG |
753 | debugfs_create_file("rq_dequeued", |
754 | S_IRUSR | S_IRGRP | S_IROTH, | |
755 | ctrlpriv->ctl, &perfmon->req_dequeued, | |
756 | &caam_fops_u64_ro); | |
8e8ec596 | 757 | ctrlpriv->ctl_ob_enc_req = |
261ea058 HG |
758 | debugfs_create_file("ob_rq_encrypted", |
759 | S_IRUSR | S_IRGRP | S_IROTH, | |
760 | ctrlpriv->ctl, &perfmon->ob_enc_req, | |
761 | &caam_fops_u64_ro); | |
8e8ec596 | 762 | ctrlpriv->ctl_ib_dec_req = |
261ea058 HG |
763 | debugfs_create_file("ib_rq_decrypted", |
764 | S_IRUSR | S_IRGRP | S_IROTH, | |
765 | ctrlpriv->ctl, &perfmon->ib_dec_req, | |
766 | &caam_fops_u64_ro); | |
8e8ec596 | 767 | ctrlpriv->ctl_ob_enc_bytes = |
261ea058 HG |
768 | debugfs_create_file("ob_bytes_encrypted", |
769 | S_IRUSR | S_IRGRP | S_IROTH, | |
770 | ctrlpriv->ctl, &perfmon->ob_enc_bytes, | |
771 | &caam_fops_u64_ro); | |
8e8ec596 | 772 | ctrlpriv->ctl_ob_prot_bytes = |
261ea058 HG |
773 | debugfs_create_file("ob_bytes_protected", |
774 | S_IRUSR | S_IRGRP | S_IROTH, | |
775 | ctrlpriv->ctl, &perfmon->ob_prot_bytes, | |
776 | &caam_fops_u64_ro); | |
8e8ec596 | 777 | ctrlpriv->ctl_ib_dec_bytes = |
261ea058 HG |
778 | debugfs_create_file("ib_bytes_decrypted", |
779 | S_IRUSR | S_IRGRP | S_IROTH, | |
780 | ctrlpriv->ctl, &perfmon->ib_dec_bytes, | |
781 | &caam_fops_u64_ro); | |
8e8ec596 | 782 | ctrlpriv->ctl_ib_valid_bytes = |
261ea058 HG |
783 | debugfs_create_file("ib_bytes_validated", |
784 | S_IRUSR | S_IRGRP | S_IROTH, | |
785 | ctrlpriv->ctl, &perfmon->ib_valid_bytes, | |
786 | &caam_fops_u64_ro); | |
8e8ec596 KP |
787 | |
788 | /* Controller level - global status values */ | |
789 | ctrlpriv->ctl_faultaddr = | |
261ea058 HG |
790 | debugfs_create_file("fault_addr", |
791 | S_IRUSR | S_IRGRP | S_IROTH, | |
792 | ctrlpriv->ctl, &perfmon->faultaddr, | |
793 | &caam_fops_u32_ro); | |
8e8ec596 | 794 | ctrlpriv->ctl_faultdetail = |
261ea058 HG |
795 | debugfs_create_file("fault_detail", |
796 | S_IRUSR | S_IRGRP | S_IROTH, | |
797 | ctrlpriv->ctl, &perfmon->faultdetail, | |
798 | &caam_fops_u32_ro); | |
8e8ec596 | 799 | ctrlpriv->ctl_faultstatus = |
261ea058 HG |
800 | debugfs_create_file("fault_status", |
801 | S_IRUSR | S_IRGRP | S_IROTH, | |
802 | ctrlpriv->ctl, &perfmon->status, | |
803 | &caam_fops_u32_ro); | |
8e8ec596 KP |
804 | |
805 | /* Internal covering keys (useful in non-secure mode only) */ | |
8439e94f | 806 | ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; |
8e8ec596 KP |
807 | ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); |
808 | ctrlpriv->ctl_kek = debugfs_create_blob("kek", | |
eda65cc6 | 809 | S_IRUSR | |
8e8ec596 KP |
810 | S_IRGRP | S_IROTH, |
811 | ctrlpriv->ctl, | |
812 | &ctrlpriv->ctl_kek_wrap); | |
813 | ||
8439e94f | 814 | ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0]; |
8e8ec596 KP |
815 | ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); |
816 | ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", | |
eda65cc6 | 817 | S_IRUSR | |
8e8ec596 KP |
818 | S_IRGRP | S_IROTH, |
819 | ctrlpriv->ctl, | |
820 | &ctrlpriv->ctl_tkek_wrap); | |
821 | ||
8439e94f | 822 | ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0]; |
8e8ec596 KP |
823 | ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); |
824 | ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", | |
eda65cc6 | 825 | S_IRUSR | |
8e8ec596 KP |
826 | S_IRGRP | S_IROTH, |
827 | ctrlpriv->ctl, | |
828 | &ctrlpriv->ctl_tdsk_wrap); | |
829 | #endif | |
830 | return 0; | |
31f44d15 FE |
831 | |
832 | caam_remove: | |
833 | caam_remove(pdev); | |
bdc67da7 RK |
834 | return ret; |
835 | ||
31f44d15 FE |
836 | iounmap_ctrl: |
837 | iounmap(ctrl); | |
838 | disable_caam_emi_slow: | |
b80609a1 | 839 | if (ctrlpriv->caam_emi_slow) |
4e518816 | 840 | clk_disable_unprepare(ctrlpriv->caam_emi_slow); |
31f44d15 FE |
841 | disable_caam_aclk: |
842 | clk_disable_unprepare(ctrlpriv->caam_aclk); | |
843 | disable_caam_mem: | |
844 | clk_disable_unprepare(ctrlpriv->caam_mem); | |
845 | disable_caam_ipg: | |
846 | clk_disable_unprepare(ctrlpriv->caam_ipg); | |
847 | return ret; | |
8e8ec596 KP |
848 | } |
849 | ||
850 | static struct of_device_id caam_match[] = { | |
851 | { | |
54e198d4 | 852 | .compatible = "fsl,sec-v4.0", |
8e8ec596 | 853 | }, |
a0ea0f6d SL |
854 | { |
855 | .compatible = "fsl,sec4.0", | |
856 | }, | |
8e8ec596 KP |
857 | {}, |
858 | }; | |
859 | MODULE_DEVICE_TABLE(of, caam_match); | |
860 | ||
2930d497 | 861 | static struct platform_driver caam_driver = { |
8e8ec596 KP |
862 | .driver = { |
863 | .name = "caam", | |
8e8ec596 KP |
864 | .of_match_table = caam_match, |
865 | }, | |
866 | .probe = caam_probe, | |
49cfe4db | 867 | .remove = caam_remove, |
8e8ec596 KP |
868 | }; |
869 | ||
741e8c2d | 870 | module_platform_driver(caam_driver); |
8e8ec596 KP |
871 | |
872 | MODULE_LICENSE("GPL"); | |
873 | MODULE_DESCRIPTION("FSL CAAM request backend"); | |
874 | MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); |