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618b5dc4 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
045e3678 YK |
2 | /* |
3 | * caam - Freescale FSL CAAM support for ahash functions of crypto API | |
4 | * | |
5 | * Copyright 2011 Freescale Semiconductor, Inc. | |
ae1dd17d | 6 | * Copyright 2018-2019, 2023 NXP |
045e3678 YK |
7 | * |
8 | * Based on caamalg.c crypto API driver. | |
9 | * | |
10 | * relationship of digest job descriptor or first job descriptor after init to | |
11 | * shared descriptors: | |
12 | * | |
13 | * --------------- --------------- | |
14 | * | JobDesc #1 |-------------------->| ShareDesc | | |
15 | * | *(packet 1) | | (hashKey) | | |
16 | * --------------- | (operation) | | |
17 | * --------------- | |
18 | * | |
19 | * relationship of subsequent job descriptors to shared descriptors: | |
20 | * | |
21 | * --------------- --------------- | |
22 | * | JobDesc #2 |-------------------->| ShareDesc | | |
23 | * | *(packet 2) | |------------->| (hashKey) | | |
24 | * --------------- | |-------->| (operation) | | |
25 | * . | | | (load ctx2) | | |
26 | * . | | --------------- | |
27 | * --------------- | | | |
28 | * | JobDesc #3 |------| | | |
29 | * | *(packet 3) | | | |
30 | * --------------- | | |
31 | * . | | |
32 | * . | | |
33 | * --------------- | | |
34 | * | JobDesc #4 |------------ | |
35 | * | *(packet 4) | | |
36 | * --------------- | |
37 | * | |
38 | * The SharedDesc never changes for a connection unless rekeyed, but | |
39 | * each packet will likely be in a different place. So all we need | |
40 | * to know to process the packet is where the input is, where the | |
41 | * output goes, and what context we want to process with. Context is | |
42 | * in the SharedDesc, packet references in the JobDesc. | |
43 | * | |
44 | * So, a job desc looks like: | |
45 | * | |
46 | * --------------------- | |
47 | * | Header | | |
48 | * | ShareDesc Pointer | | |
49 | * | SEQ_OUT_PTR | | |
50 | * | (output buffer) | | |
51 | * | (output length) | | |
52 | * | SEQ_IN_PTR | | |
53 | * | (input buffer) | | |
54 | * | (input length) | | |
55 | * --------------------- | |
56 | */ | |
57 | ||
58 | #include "compat.h" | |
59 | ||
60 | #include "regs.h" | |
61 | #include "intern.h" | |
62 | #include "desc_constr.h" | |
63 | #include "jr.h" | |
64 | #include "error.h" | |
65 | #include "sg_sw_sec4.h" | |
66 | #include "key_gen.h" | |
0efa7579 | 67 | #include "caamhash_desc.h" |
4ac1a2d8 | 68 | #include <crypto/internal/engine.h> |
623814c0 | 69 | #include <crypto/internal/hash.h> |
199354d7 | 70 | #include <linux/dma-mapping.h> |
623814c0 | 71 | #include <linux/err.h> |
199354d7 | 72 | #include <linux/kernel.h> |
623814c0 HX |
73 | #include <linux/slab.h> |
74 | #include <linux/string.h> | |
045e3678 YK |
75 | |
76 | #define CAAM_CRA_PRIORITY 3000 | |
77 | ||
78 | /* max hash key is max split key size */ | |
79 | #define CAAM_MAX_HASH_KEY_SIZE (SHA512_DIGEST_SIZE * 2) | |
80 | ||
81 | #define CAAM_MAX_HASH_BLOCK_SIZE SHA512_BLOCK_SIZE | |
82 | #define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE | |
83 | ||
045e3678 YK |
84 | #define DESC_HASH_MAX_USED_BYTES (DESC_AHASH_FINAL_LEN + \ |
85 | CAAM_MAX_HASH_KEY_SIZE) | |
86 | #define DESC_HASH_MAX_USED_LEN (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ) | |
87 | ||
88 | /* caam context sizes for hashes: running digest + 8 */ | |
89 | #define HASH_MSG_LEN 8 | |
90 | #define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE) | |
91 | ||
cfc6f11b RG |
92 | static struct list_head hash_list; |
93 | ||
045e3678 YK |
94 | /* ahash per-session context */ |
95 | struct caam_hash_ctx { | |
e11793f5 RK |
96 | u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; |
97 | u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; | |
98 | u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; | |
99 | u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; | |
12b8567f | 100 | u8 key[CAAM_MAX_HASH_KEY_SIZE] ____cacheline_aligned; |
e11793f5 | 101 | dma_addr_t sh_desc_update_dma ____cacheline_aligned; |
045e3678 YK |
102 | dma_addr_t sh_desc_update_first_dma; |
103 | dma_addr_t sh_desc_fin_dma; | |
104 | dma_addr_t sh_desc_digest_dma; | |
7e0880b9 | 105 | enum dma_data_direction dir; |
e9b4913a | 106 | enum dma_data_direction key_dir; |
e11793f5 | 107 | struct device *jrdev; |
045e3678 | 108 | int ctx_len; |
db57656b | 109 | struct alginfo adata; |
045e3678 YK |
110 | }; |
111 | ||
112 | /* ahash state */ | |
113 | struct caam_hash_state { | |
114 | dma_addr_t buf_dma; | |
115 | dma_addr_t ctx_dma; | |
65055e21 | 116 | int ctx_dma_len; |
46b49abc AB |
117 | u8 buf[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned; |
118 | int buflen; | |
119 | int next_buflen; | |
e7472422 | 120 | u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned; |
21b014f0 | 121 | int (*update)(struct ahash_request *req) ____cacheline_aligned; |
045e3678 YK |
122 | int (*final)(struct ahash_request *req); |
123 | int (*finup)(struct ahash_request *req); | |
21b014f0 IP |
124 | struct ahash_edesc *edesc; |
125 | void (*ahash_op_done)(struct device *jrdev, u32 *desc, u32 err, | |
126 | void *context); | |
045e3678 YK |
127 | }; |
128 | ||
5ec90831 RK |
129 | struct caam_export_state { |
130 | u8 buf[CAAM_MAX_HASH_BLOCK_SIZE]; | |
131 | u8 caam_ctx[MAX_CTX_LEN]; | |
132 | int buflen; | |
133 | int (*update)(struct ahash_request *req); | |
134 | int (*final)(struct ahash_request *req); | |
135 | int (*finup)(struct ahash_request *req); | |
136 | }; | |
137 | ||
87870cfb | 138 | static inline bool is_cmac_aes(u32 algtype) |
12b8567f IP |
139 | { |
140 | return (algtype & (OP_ALG_ALGSEL_MASK | OP_ALG_AAI_MASK)) == | |
87870cfb | 141 | (OP_ALG_ALGSEL_AES | OP_ALG_AAI_CMAC); |
12b8567f | 142 | } |
045e3678 YK |
143 | /* Common job descriptor seq in/out ptr routines */ |
144 | ||
145 | /* Map state->caam_ctx, and append seq_out_ptr command that points to it */ | |
ce572085 HG |
146 | static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev, |
147 | struct caam_hash_state *state, | |
148 | int ctx_len) | |
045e3678 | 149 | { |
65055e21 | 150 | state->ctx_dma_len = ctx_len; |
045e3678 YK |
151 | state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, |
152 | ctx_len, DMA_FROM_DEVICE); | |
ce572085 HG |
153 | if (dma_mapping_error(jrdev, state->ctx_dma)) { |
154 | dev_err(jrdev, "unable to map ctx\n"); | |
87ec02e7 | 155 | state->ctx_dma = 0; |
ce572085 HG |
156 | return -ENOMEM; |
157 | } | |
158 | ||
045e3678 | 159 | append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0); |
ce572085 HG |
160 | |
161 | return 0; | |
045e3678 YK |
162 | } |
163 | ||
944c3d4d HG |
164 | /* Map current buffer in state (if length > 0) and put it in link table */ |
165 | static inline int buf_map_to_sec4_sg(struct device *jrdev, | |
166 | struct sec4_sg_entry *sec4_sg, | |
167 | struct caam_hash_state *state) | |
045e3678 | 168 | { |
46b49abc | 169 | int buflen = state->buflen; |
045e3678 | 170 | |
944c3d4d HG |
171 | if (!buflen) |
172 | return 0; | |
045e3678 | 173 | |
46b49abc | 174 | state->buf_dma = dma_map_single(jrdev, state->buf, buflen, |
944c3d4d HG |
175 | DMA_TO_DEVICE); |
176 | if (dma_mapping_error(jrdev, state->buf_dma)) { | |
177 | dev_err(jrdev, "unable to map buf\n"); | |
178 | state->buf_dma = 0; | |
179 | return -ENOMEM; | |
180 | } | |
045e3678 | 181 | |
944c3d4d HG |
182 | dma_to_sec4_sg_one(sec4_sg, state->buf_dma, buflen, 0); |
183 | ||
184 | return 0; | |
045e3678 YK |
185 | } |
186 | ||
187 | /* Map state->caam_ctx, and add it to link table */ | |
dfcd8393 | 188 | static inline int ctx_map_to_sec4_sg(struct device *jrdev, |
ce572085 HG |
189 | struct caam_hash_state *state, int ctx_len, |
190 | struct sec4_sg_entry *sec4_sg, u32 flag) | |
045e3678 | 191 | { |
65055e21 | 192 | state->ctx_dma_len = ctx_len; |
045e3678 | 193 | state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag); |
ce572085 HG |
194 | if (dma_mapping_error(jrdev, state->ctx_dma)) { |
195 | dev_err(jrdev, "unable to map ctx\n"); | |
87ec02e7 | 196 | state->ctx_dma = 0; |
ce572085 HG |
197 | return -ENOMEM; |
198 | } | |
199 | ||
045e3678 | 200 | dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0); |
ce572085 HG |
201 | |
202 | return 0; | |
045e3678 YK |
203 | } |
204 | ||
045e3678 YK |
205 | static int ahash_set_sh_desc(struct crypto_ahash *ahash) |
206 | { | |
4cb4f7c1 | 207 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
045e3678 YK |
208 | int digestsize = crypto_ahash_digestsize(ahash); |
209 | struct device *jrdev = ctx->jrdev; | |
7e0880b9 | 210 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); |
045e3678 YK |
211 | u32 *desc; |
212 | ||
7e0880b9 HG |
213 | ctx->adata.key_virt = ctx->key; |
214 | ||
045e3678 YK |
215 | /* ahash_update shared descriptor */ |
216 | desc = ctx->sh_desc_update; | |
0efa7579 HG |
217 | cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len, |
218 | ctx->ctx_len, true, ctrlpriv->era); | |
bbf22344 | 219 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma, |
7e0880b9 | 220 | desc_bytes(desc), ctx->dir); |
6e005503 SH |
221 | |
222 | print_hex_dump_debug("ahash update shdesc@"__stringify(__LINE__)": ", | |
223 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
224 | 1); | |
045e3678 YK |
225 | |
226 | /* ahash_update_first shared descriptor */ | |
227 | desc = ctx->sh_desc_update_first; | |
0efa7579 HG |
228 | cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len, |
229 | ctx->ctx_len, false, ctrlpriv->era); | |
bbf22344 | 230 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, |
7e0880b9 | 231 | desc_bytes(desc), ctx->dir); |
6e005503 SH |
232 | print_hex_dump_debug("ahash update first shdesc@"__stringify(__LINE__) |
233 | ": ", DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
234 | desc_bytes(desc), 1); | |
045e3678 YK |
235 | |
236 | /* ahash_final shared descriptor */ | |
237 | desc = ctx->sh_desc_fin; | |
0efa7579 HG |
238 | cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize, |
239 | ctx->ctx_len, true, ctrlpriv->era); | |
bbf22344 | 240 | dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, |
7e0880b9 | 241 | desc_bytes(desc), ctx->dir); |
6e005503 SH |
242 | |
243 | print_hex_dump_debug("ahash final shdesc@"__stringify(__LINE__)": ", | |
244 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
245 | desc_bytes(desc), 1); | |
045e3678 | 246 | |
045e3678 YK |
247 | /* ahash_digest shared descriptor */ |
248 | desc = ctx->sh_desc_digest; | |
0efa7579 HG |
249 | cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize, |
250 | ctx->ctx_len, false, ctrlpriv->era); | |
bbf22344 | 251 | dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, |
7e0880b9 | 252 | desc_bytes(desc), ctx->dir); |
6e005503 SH |
253 | |
254 | print_hex_dump_debug("ahash digest shdesc@"__stringify(__LINE__)": ", | |
255 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
256 | desc_bytes(desc), 1); | |
045e3678 YK |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
12b8567f IP |
261 | static int axcbc_set_sh_desc(struct crypto_ahash *ahash) |
262 | { | |
4cb4f7c1 | 263 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
12b8567f IP |
264 | int digestsize = crypto_ahash_digestsize(ahash); |
265 | struct device *jrdev = ctx->jrdev; | |
266 | u32 *desc; | |
267 | ||
12b8567f IP |
268 | /* shared descriptor for ahash_update */ |
269 | desc = ctx->sh_desc_update; | |
87870cfb | 270 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_UPDATE, |
a2fb864c | 271 | ctx->ctx_len, ctx->ctx_len); |
12b8567f IP |
272 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma, |
273 | desc_bytes(desc), ctx->dir); | |
274 | print_hex_dump_debug("axcbc update shdesc@" __stringify(__LINE__)" : ", | |
275 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
276 | 1); | |
277 | ||
278 | /* shared descriptor for ahash_{final,finup} */ | |
279 | desc = ctx->sh_desc_fin; | |
87870cfb | 280 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, |
a2fb864c | 281 | digestsize, ctx->ctx_len); |
12b8567f IP |
282 | dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, |
283 | desc_bytes(desc), ctx->dir); | |
284 | print_hex_dump_debug("axcbc finup shdesc@" __stringify(__LINE__)" : ", | |
285 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
286 | 1); | |
287 | ||
288 | /* key is immediate data for INIT and INITFINAL states */ | |
289 | ctx->adata.key_virt = ctx->key; | |
290 | ||
291 | /* shared descriptor for first invocation of ahash_update */ | |
292 | desc = ctx->sh_desc_update_first; | |
87870cfb | 293 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len, |
a2fb864c | 294 | ctx->ctx_len); |
12b8567f IP |
295 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, |
296 | desc_bytes(desc), ctx->dir); | |
6e005503 SH |
297 | print_hex_dump_debug("axcbc update first shdesc@" __stringify(__LINE__) |
298 | " : ", DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
299 | desc_bytes(desc), 1); | |
12b8567f IP |
300 | |
301 | /* shared descriptor for ahash_digest */ | |
302 | desc = ctx->sh_desc_digest; | |
87870cfb | 303 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, |
a2fb864c | 304 | digestsize, ctx->ctx_len); |
12b8567f IP |
305 | dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, |
306 | desc_bytes(desc), ctx->dir); | |
307 | print_hex_dump_debug("axcbc digest shdesc@" __stringify(__LINE__)" : ", | |
308 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
309 | 1); | |
87870cfb IP |
310 | return 0; |
311 | } | |
312 | ||
313 | static int acmac_set_sh_desc(struct crypto_ahash *ahash) | |
314 | { | |
4cb4f7c1 | 315 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
87870cfb IP |
316 | int digestsize = crypto_ahash_digestsize(ahash); |
317 | struct device *jrdev = ctx->jrdev; | |
318 | u32 *desc; | |
319 | ||
320 | /* shared descriptor for ahash_update */ | |
321 | desc = ctx->sh_desc_update; | |
322 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_UPDATE, | |
a2fb864c | 323 | ctx->ctx_len, ctx->ctx_len); |
87870cfb IP |
324 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma, |
325 | desc_bytes(desc), ctx->dir); | |
326 | print_hex_dump_debug("acmac update shdesc@" __stringify(__LINE__)" : ", | |
327 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
328 | desc_bytes(desc), 1); | |
329 | ||
330 | /* shared descriptor for ahash_{final,finup} */ | |
331 | desc = ctx->sh_desc_fin; | |
332 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, | |
a2fb864c | 333 | digestsize, ctx->ctx_len); |
87870cfb IP |
334 | dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, |
335 | desc_bytes(desc), ctx->dir); | |
336 | print_hex_dump_debug("acmac finup shdesc@" __stringify(__LINE__)" : ", | |
337 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
338 | desc_bytes(desc), 1); | |
339 | ||
340 | /* shared descriptor for first invocation of ahash_update */ | |
341 | desc = ctx->sh_desc_update_first; | |
342 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len, | |
a2fb864c | 343 | ctx->ctx_len); |
87870cfb IP |
344 | dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, |
345 | desc_bytes(desc), ctx->dir); | |
6e005503 SH |
346 | print_hex_dump_debug("acmac update first shdesc@" __stringify(__LINE__) |
347 | " : ", DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
87870cfb IP |
348 | desc_bytes(desc), 1); |
349 | ||
350 | /* shared descriptor for ahash_digest */ | |
351 | desc = ctx->sh_desc_digest; | |
352 | cnstr_shdsc_sk_hash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, | |
a2fb864c | 353 | digestsize, ctx->ctx_len); |
87870cfb IP |
354 | dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, |
355 | desc_bytes(desc), ctx->dir); | |
356 | print_hex_dump_debug("acmac digest shdesc@" __stringify(__LINE__)" : ", | |
357 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
358 | desc_bytes(desc), 1); | |
12b8567f IP |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
045e3678 | 363 | /* Digest hash size if it is too large */ |
30724445 HG |
364 | static int hash_digest_key(struct caam_hash_ctx *ctx, u32 *keylen, u8 *key, |
365 | u32 digestsize) | |
045e3678 YK |
366 | { |
367 | struct device *jrdev = ctx->jrdev; | |
368 | u32 *desc; | |
369 | struct split_key_result result; | |
30724445 | 370 | dma_addr_t key_dma; |
9e6df0fd | 371 | int ret; |
045e3678 | 372 | |
199354d7 | 373 | desc = kmalloc(CAAM_CMD_SZ * 8 + CAAM_PTR_SZ * 2, GFP_KERNEL); |
3de0152b | 374 | if (!desc) |
2af8f4a2 | 375 | return -ENOMEM; |
045e3678 YK |
376 | |
377 | init_job_desc(desc, 0); | |
378 | ||
30724445 HG |
379 | key_dma = dma_map_single(jrdev, key, *keylen, DMA_BIDIRECTIONAL); |
380 | if (dma_mapping_error(jrdev, key_dma)) { | |
381 | dev_err(jrdev, "unable to map key memory\n"); | |
045e3678 YK |
382 | kfree(desc); |
383 | return -ENOMEM; | |
384 | } | |
385 | ||
386 | /* Job descriptor to perform unkeyed hash on key_in */ | |
db57656b | 387 | append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT | |
045e3678 | 388 | OP_ALG_AS_INITFINAL); |
30724445 | 389 | append_seq_in_ptr(desc, key_dma, *keylen, 0); |
045e3678 YK |
390 | append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 | |
391 | FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG); | |
30724445 | 392 | append_seq_out_ptr(desc, key_dma, digestsize, 0); |
045e3678 YK |
393 | append_seq_store(desc, digestsize, LDST_CLASS_2_CCB | |
394 | LDST_SRCDST_BYTE_CONTEXT); | |
395 | ||
6e005503 SH |
396 | print_hex_dump_debug("key_in@"__stringify(__LINE__)": ", |
397 | DUMP_PREFIX_ADDRESS, 16, 4, key, *keylen, 1); | |
398 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", | |
399 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
400 | 1); | |
045e3678 YK |
401 | |
402 | result.err = 0; | |
403 | init_completion(&result.completion); | |
404 | ||
405 | ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result); | |
4d370a10 | 406 | if (ret == -EINPROGRESS) { |
045e3678 | 407 | /* in progress */ |
7459e1d2 | 408 | wait_for_completion(&result.completion); |
045e3678 | 409 | ret = result.err; |
6e005503 SH |
410 | |
411 | print_hex_dump_debug("digested key@"__stringify(__LINE__)": ", | |
412 | DUMP_PREFIX_ADDRESS, 16, 4, key, | |
413 | digestsize, 1); | |
045e3678 | 414 | } |
30724445 | 415 | dma_unmap_single(jrdev, key_dma, *keylen, DMA_BIDIRECTIONAL); |
045e3678 | 416 | |
e11aa9f1 HG |
417 | *keylen = digestsize; |
418 | ||
045e3678 YK |
419 | kfree(desc); |
420 | ||
421 | return ret; | |
422 | } | |
423 | ||
424 | static int ahash_setkey(struct crypto_ahash *ahash, | |
425 | const u8 *key, unsigned int keylen) | |
426 | { | |
4cb4f7c1 | 427 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
6e005503 | 428 | struct device *jrdev = ctx->jrdev; |
045e3678 YK |
429 | int blocksize = crypto_tfm_alg_blocksize(&ahash->base); |
430 | int digestsize = crypto_ahash_digestsize(ahash); | |
7e0880b9 | 431 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); |
9e6df0fd | 432 | int ret; |
045e3678 YK |
433 | u8 *hashed_key = NULL; |
434 | ||
6e005503 | 435 | dev_dbg(jrdev, "keylen %d\n", keylen); |
045e3678 YK |
436 | |
437 | if (keylen > blocksize) { | |
199354d7 HX |
438 | unsigned int aligned_len = |
439 | ALIGN(keylen, dma_get_cache_alignment()); | |
440 | ||
441 | if (aligned_len < keylen) | |
442 | return -EOVERFLOW; | |
443 | ||
444 | hashed_key = kmemdup(key, keylen, GFP_KERNEL); | |
045e3678 YK |
445 | if (!hashed_key) |
446 | return -ENOMEM; | |
30724445 | 447 | ret = hash_digest_key(ctx, &keylen, hashed_key, digestsize); |
045e3678 | 448 | if (ret) |
d6e7a7d0 | 449 | goto bad_free_key; |
045e3678 YK |
450 | key = hashed_key; |
451 | } | |
452 | ||
7e0880b9 HG |
453 | /* |
454 | * If DKP is supported, use it in the shared descriptor to generate | |
455 | * the split key. | |
456 | */ | |
457 | if (ctrlpriv->era >= 6) { | |
458 | ctx->adata.key_inline = true; | |
459 | ctx->adata.keylen = keylen; | |
460 | ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & | |
461 | OP_ALG_ALGSEL_MASK); | |
045e3678 | 462 | |
7e0880b9 HG |
463 | if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE) |
464 | goto bad_free_key; | |
465 | ||
466 | memcpy(ctx->key, key, keylen); | |
e9b4913a HG |
467 | |
468 | /* | |
469 | * In case |user key| > |derived key|, using DKP<imm,imm> | |
470 | * would result in invalid opcodes (last bytes of user key) in | |
471 | * the resulting descriptor. Use DKP<ptr,imm> instead => both | |
472 | * virtual and dma key addresses are needed. | |
473 | */ | |
474 | if (keylen > ctx->adata.keylen_pad) | |
475 | dma_sync_single_for_device(ctx->jrdev, | |
476 | ctx->adata.key_dma, | |
477 | ctx->adata.keylen_pad, | |
478 | DMA_TO_DEVICE); | |
7e0880b9 HG |
479 | } else { |
480 | ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key, | |
481 | keylen, CAAM_MAX_HASH_KEY_SIZE); | |
482 | if (ret) | |
483 | goto bad_free_key; | |
484 | } | |
045e3678 | 485 | |
045e3678 | 486 | kfree(hashed_key); |
cfb725f6 | 487 | return ahash_set_sh_desc(ahash); |
d6e7a7d0 | 488 | bad_free_key: |
045e3678 | 489 | kfree(hashed_key); |
045e3678 YK |
490 | return -EINVAL; |
491 | } | |
492 | ||
12b8567f IP |
493 | static int axcbc_setkey(struct crypto_ahash *ahash, const u8 *key, |
494 | unsigned int keylen) | |
495 | { | |
4cb4f7c1 | 496 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
12b8567f IP |
497 | struct device *jrdev = ctx->jrdev; |
498 | ||
674f368a | 499 | if (keylen != AES_KEYSIZE_128) |
836d8f43 | 500 | return -EINVAL; |
836d8f43 | 501 | |
12b8567f | 502 | memcpy(ctx->key, key, keylen); |
a2fb864c HG |
503 | dma_sync_single_for_device(jrdev, ctx->adata.key_dma, keylen, |
504 | DMA_TO_DEVICE); | |
12b8567f IP |
505 | ctx->adata.keylen = keylen; |
506 | ||
507 | print_hex_dump_debug("axcbc ctx.key@" __stringify(__LINE__)" : ", | |
508 | DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, keylen, 1); | |
509 | ||
510 | return axcbc_set_sh_desc(ahash); | |
511 | } | |
87870cfb IP |
512 | |
513 | static int acmac_setkey(struct crypto_ahash *ahash, const u8 *key, | |
514 | unsigned int keylen) | |
515 | { | |
4cb4f7c1 | 516 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
836d8f43 IP |
517 | int err; |
518 | ||
519 | err = aes_check_keylen(keylen); | |
674f368a | 520 | if (err) |
836d8f43 | 521 | return err; |
87870cfb IP |
522 | |
523 | /* key is immediate data for all cmac shared descriptors */ | |
524 | ctx->adata.key_virt = key; | |
525 | ctx->adata.keylen = keylen; | |
526 | ||
527 | print_hex_dump_debug("acmac ctx.key@" __stringify(__LINE__)" : ", | |
528 | DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); | |
529 | ||
530 | return acmac_set_sh_desc(ahash); | |
531 | } | |
532 | ||
045e3678 YK |
533 | /* |
534 | * ahash_edesc - s/w-extended ahash descriptor | |
045e3678 YK |
535 | * @sec4_sg_dma: physical mapped address of h/w link table |
536 | * @src_nents: number of segments in input scatterlist | |
537 | * @sec4_sg_bytes: length of dma mapped sec4_sg space | |
21b014f0 | 538 | * @bklog: stored to determine if the request needs backlog |
045e3678 | 539 | * @hw_desc: the h/w job descriptor followed by any referenced link tables |
343e44b1 | 540 | * @sec4_sg: h/w link table |
045e3678 YK |
541 | */ |
542 | struct ahash_edesc { | |
045e3678 YK |
543 | dma_addr_t sec4_sg_dma; |
544 | int src_nents; | |
545 | int sec4_sg_bytes; | |
21b014f0 | 546 | bool bklog; |
1a3daadc | 547 | u32 hw_desc[DESC_JOB_IO_LEN_MAX / sizeof(u32)] ____cacheline_aligned; |
5a8a0765 | 548 | struct sec4_sg_entry sec4_sg[]; |
045e3678 YK |
549 | }; |
550 | ||
551 | static inline void ahash_unmap(struct device *dev, | |
552 | struct ahash_edesc *edesc, | |
553 | struct ahash_request *req, int dst_len) | |
554 | { | |
4cb4f7c1 | 555 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
944c3d4d | 556 | |
045e3678 | 557 | if (edesc->src_nents) |
13fb8fd7 | 558 | dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE); |
045e3678 YK |
559 | |
560 | if (edesc->sec4_sg_bytes) | |
561 | dma_unmap_single(dev, edesc->sec4_sg_dma, | |
562 | edesc->sec4_sg_bytes, DMA_TO_DEVICE); | |
944c3d4d HG |
563 | |
564 | if (state->buf_dma) { | |
46b49abc | 565 | dma_unmap_single(dev, state->buf_dma, state->buflen, |
944c3d4d HG |
566 | DMA_TO_DEVICE); |
567 | state->buf_dma = 0; | |
568 | } | |
045e3678 YK |
569 | } |
570 | ||
571 | static inline void ahash_unmap_ctx(struct device *dev, | |
572 | struct ahash_edesc *edesc, | |
573 | struct ahash_request *req, int dst_len, u32 flag) | |
574 | { | |
4cb4f7c1 | 575 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
045e3678 | 576 | |
87ec02e7 | 577 | if (state->ctx_dma) { |
65055e21 | 578 | dma_unmap_single(dev, state->ctx_dma, state->ctx_dma_len, flag); |
87ec02e7 HG |
579 | state->ctx_dma = 0; |
580 | } | |
045e3678 YK |
581 | ahash_unmap(dev, edesc, req, dst_len); |
582 | } | |
583 | ||
c3f7394e IP |
584 | static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err, |
585 | void *context, enum dma_data_direction dir) | |
045e3678 YK |
586 | { |
587 | struct ahash_request *req = context; | |
21b014f0 | 588 | struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); |
045e3678 YK |
589 | struct ahash_edesc *edesc; |
590 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
591 | int digestsize = crypto_ahash_digestsize(ahash); | |
4cb4f7c1 HX |
592 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
593 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); | |
1984aaee | 594 | int ecode = 0; |
63db32e6 | 595 | bool has_bklog; |
045e3678 | 596 | |
6e005503 | 597 | dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); |
045e3678 | 598 | |
21b014f0 | 599 | edesc = state->edesc; |
63db32e6 | 600 | has_bklog = edesc->bklog; |
21b014f0 | 601 | |
fa9659cd | 602 | if (err) |
1984aaee | 603 | ecode = caam_jr_strstatus(jrdev, err); |
045e3678 | 604 | |
c3f7394e | 605 | ahash_unmap_ctx(jrdev, edesc, req, digestsize, dir); |
c19650d6 | 606 | memcpy(req->result, state->caam_ctx, digestsize); |
045e3678 YK |
607 | kfree(edesc); |
608 | ||
6e005503 SH |
609 | print_hex_dump_debug("ctx@"__stringify(__LINE__)": ", |
610 | DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, | |
611 | ctx->ctx_len, 1); | |
045e3678 | 612 | |
21b014f0 IP |
613 | /* |
614 | * If no backlog flag, the completion of the request is done | |
615 | * by CAAM, not crypto engine. | |
616 | */ | |
63db32e6 | 617 | if (!has_bklog) |
4bc713a4 | 618 | ahash_request_complete(req, ecode); |
21b014f0 IP |
619 | else |
620 | crypto_finalize_hash_request(jrp->engine, req, ecode); | |
045e3678 YK |
621 | } |
622 | ||
c3f7394e IP |
623 | static void ahash_done(struct device *jrdev, u32 *desc, u32 err, |
624 | void *context) | |
045e3678 | 625 | { |
c3f7394e | 626 | ahash_done_cpy(jrdev, desc, err, context, DMA_FROM_DEVICE); |
045e3678 YK |
627 | } |
628 | ||
629 | static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err, | |
630 | void *context) | |
631 | { | |
c3f7394e | 632 | ahash_done_cpy(jrdev, desc, err, context, DMA_BIDIRECTIONAL); |
045e3678 YK |
633 | } |
634 | ||
c3f7394e IP |
635 | static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err, |
636 | void *context, enum dma_data_direction dir) | |
045e3678 YK |
637 | { |
638 | struct ahash_request *req = context; | |
21b014f0 | 639 | struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); |
045e3678 YK |
640 | struct ahash_edesc *edesc; |
641 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
642 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
643 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 644 | int digestsize = crypto_ahash_digestsize(ahash); |
1984aaee | 645 | int ecode = 0; |
63db32e6 | 646 | bool has_bklog; |
045e3678 | 647 | |
6e005503 | 648 | dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); |
045e3678 | 649 | |
21b014f0 | 650 | edesc = state->edesc; |
63db32e6 | 651 | has_bklog = edesc->bklog; |
fa9659cd | 652 | if (err) |
1984aaee | 653 | ecode = caam_jr_strstatus(jrdev, err); |
045e3678 | 654 | |
c3f7394e | 655 | ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, dir); |
045e3678 YK |
656 | kfree(edesc); |
657 | ||
46b49abc AB |
658 | scatterwalk_map_and_copy(state->buf, req->src, |
659 | req->nbytes - state->next_buflen, | |
660 | state->next_buflen, 0); | |
661 | state->buflen = state->next_buflen; | |
662 | ||
663 | print_hex_dump_debug("buf@" __stringify(__LINE__)": ", | |
664 | DUMP_PREFIX_ADDRESS, 16, 4, state->buf, | |
665 | state->buflen, 1); | |
666 | ||
6e005503 SH |
667 | print_hex_dump_debug("ctx@"__stringify(__LINE__)": ", |
668 | DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, | |
669 | ctx->ctx_len, 1); | |
045e3678 | 670 | if (req->result) |
6e005503 SH |
671 | print_hex_dump_debug("result@"__stringify(__LINE__)": ", |
672 | DUMP_PREFIX_ADDRESS, 16, 4, req->result, | |
673 | digestsize, 1); | |
045e3678 | 674 | |
21b014f0 IP |
675 | /* |
676 | * If no backlog flag, the completion of the request is done | |
677 | * by CAAM, not crypto engine. | |
678 | */ | |
63db32e6 | 679 | if (!has_bklog) |
4bc713a4 | 680 | ahash_request_complete(req, ecode); |
21b014f0 IP |
681 | else |
682 | crypto_finalize_hash_request(jrp->engine, req, ecode); | |
683 | ||
045e3678 YK |
684 | } |
685 | ||
c3f7394e IP |
686 | static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, |
687 | void *context) | |
688 | { | |
689 | ahash_done_switch(jrdev, desc, err, context, DMA_BIDIRECTIONAL); | |
690 | } | |
691 | ||
692 | static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, | |
693 | void *context) | |
694 | { | |
695 | ahash_done_switch(jrdev, desc, err, context, DMA_FROM_DEVICE); | |
696 | } | |
697 | ||
5588d039 RK |
698 | /* |
699 | * Allocate an enhanced descriptor, which contains the hardware descriptor | |
700 | * and space for hardware scatter table containing sg_num entries. | |
701 | */ | |
2ba1e798 | 702 | static struct ahash_edesc *ahash_edesc_alloc(struct ahash_request *req, |
30a43b44 | 703 | int sg_num, u32 *sh_desc, |
2ba1e798 | 704 | dma_addr_t sh_desc_dma) |
5588d039 | 705 | { |
4cb4f7c1 | 706 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
2ba1e798 IP |
707 | gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? |
708 | GFP_KERNEL : GFP_ATOMIC; | |
5588d039 | 709 | struct ahash_edesc *edesc; |
5588d039 | 710 | |
6df04505 | 711 | edesc = kzalloc(struct_size(edesc, sec4_sg, sg_num), flags); |
3de0152b | 712 | if (!edesc) |
5588d039 | 713 | return NULL; |
5588d039 | 714 | |
21b014f0 IP |
715 | state->edesc = edesc; |
716 | ||
30a43b44 RK |
717 | init_job_desc_shared(edesc->hw_desc, sh_desc_dma, desc_len(sh_desc), |
718 | HDR_SHARE_DEFER | HDR_REVERSE); | |
719 | ||
5588d039 RK |
720 | return edesc; |
721 | } | |
722 | ||
65cf164a RK |
723 | static int ahash_edesc_add_src(struct caam_hash_ctx *ctx, |
724 | struct ahash_edesc *edesc, | |
725 | struct ahash_request *req, int nents, | |
726 | unsigned int first_sg, | |
727 | unsigned int first_bytes, size_t to_hash) | |
728 | { | |
729 | dma_addr_t src_dma; | |
730 | u32 options; | |
731 | ||
732 | if (nents > 1 || first_sg) { | |
733 | struct sec4_sg_entry *sg = edesc->sec4_sg; | |
a5e5c133 HG |
734 | unsigned int sgsize = sizeof(*sg) * |
735 | pad_sg_nents(first_sg + nents); | |
65cf164a | 736 | |
059d73ee | 737 | sg_to_sec4_sg_last(req->src, to_hash, sg + first_sg, 0); |
65cf164a RK |
738 | |
739 | src_dma = dma_map_single(ctx->jrdev, sg, sgsize, DMA_TO_DEVICE); | |
740 | if (dma_mapping_error(ctx->jrdev, src_dma)) { | |
741 | dev_err(ctx->jrdev, "unable to map S/G table\n"); | |
742 | return -ENOMEM; | |
743 | } | |
744 | ||
745 | edesc->sec4_sg_bytes = sgsize; | |
746 | edesc->sec4_sg_dma = src_dma; | |
747 | options = LDST_SGF; | |
748 | } else { | |
749 | src_dma = sg_dma_address(req->src); | |
750 | options = 0; | |
751 | } | |
752 | ||
753 | append_seq_in_ptr(edesc->hw_desc, src_dma, first_bytes + to_hash, | |
754 | options); | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
21b014f0 IP |
759 | static int ahash_do_one_req(struct crypto_engine *engine, void *areq) |
760 | { | |
761 | struct ahash_request *req = ahash_request_cast(areq); | |
4cb4f7c1 HX |
762 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(crypto_ahash_reqtfm(req)); |
763 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
21b014f0 IP |
764 | struct device *jrdev = ctx->jrdev; |
765 | u32 *desc = state->edesc->hw_desc; | |
766 | int ret; | |
767 | ||
768 | state->edesc->bklog = true; | |
769 | ||
770 | ret = caam_jr_enqueue(jrdev, desc, state->ahash_op_done, req); | |
771 | ||
087e1d71 GJ |
772 | if (ret == -ENOSPC && engine->retry_support) |
773 | return ret; | |
774 | ||
21b014f0 IP |
775 | if (ret != -EINPROGRESS) { |
776 | ahash_unmap(jrdev, state->edesc, req, 0); | |
777 | kfree(state->edesc); | |
778 | } else { | |
779 | ret = 0; | |
780 | } | |
781 | ||
782 | return ret; | |
783 | } | |
784 | ||
785 | static int ahash_enqueue_req(struct device *jrdev, | |
786 | void (*cbk)(struct device *jrdev, u32 *desc, | |
787 | u32 err, void *context), | |
788 | struct ahash_request *req, | |
789 | int dst_len, enum dma_data_direction dir) | |
790 | { | |
791 | struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); | |
4cb4f7c1 | 792 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
21b014f0 IP |
793 | struct ahash_edesc *edesc = state->edesc; |
794 | u32 *desc = edesc->hw_desc; | |
795 | int ret; | |
796 | ||
797 | state->ahash_op_done = cbk; | |
798 | ||
799 | /* | |
800 | * Only the backlog request are sent to crypto-engine since the others | |
801 | * can be handled by CAAM, if free, especially since JR has up to 1024 | |
802 | * entries (more than the 10 entries from crypto-engine). | |
803 | */ | |
804 | if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG) | |
805 | ret = crypto_transfer_hash_request_to_engine(jrpriv->engine, | |
806 | req); | |
807 | else | |
808 | ret = caam_jr_enqueue(jrdev, desc, cbk, req); | |
809 | ||
810 | if ((ret != -EINPROGRESS) && (ret != -EBUSY)) { | |
811 | ahash_unmap_ctx(jrdev, edesc, req, dst_len, dir); | |
812 | kfree(edesc); | |
813 | } | |
814 | ||
815 | return ret; | |
816 | } | |
817 | ||
045e3678 YK |
818 | /* submit update job descriptor */ |
819 | static int ahash_update_ctx(struct ahash_request *req) | |
820 | { | |
821 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
822 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
823 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 824 | struct device *jrdev = ctx->jrdev; |
46b49abc AB |
825 | u8 *buf = state->buf; |
826 | int *buflen = &state->buflen; | |
827 | int *next_buflen = &state->next_buflen; | |
12b8567f | 828 | int blocksize = crypto_ahash_blocksize(ahash); |
045e3678 | 829 | int in_len = *buflen + req->nbytes, to_hash; |
30a43b44 | 830 | u32 *desc; |
bc13c69e | 831 | int src_nents, mapped_nents, sec4_sg_bytes, sec4_sg_src_index; |
045e3678 YK |
832 | struct ahash_edesc *edesc; |
833 | int ret = 0; | |
045e3678 | 834 | |
12b8567f | 835 | *next_buflen = in_len & (blocksize - 1); |
045e3678 YK |
836 | to_hash = in_len - *next_buflen; |
837 | ||
12b8567f | 838 | /* |
87870cfb | 839 | * For XCBC and CMAC, if to_hash is multiple of block size, |
12b8567f IP |
840 | * keep last block in internal buffer |
841 | */ | |
87870cfb IP |
842 | if ((is_xcbc_aes(ctx->adata.algtype) || |
843 | is_cmac_aes(ctx->adata.algtype)) && to_hash >= blocksize && | |
844 | (*next_buflen == 0)) { | |
12b8567f IP |
845 | *next_buflen = blocksize; |
846 | to_hash -= blocksize; | |
847 | } | |
848 | ||
045e3678 | 849 | if (to_hash) { |
a5e5c133 | 850 | int pad_nents; |
059d73ee | 851 | int src_len = req->nbytes - *next_buflen; |
a5e5c133 | 852 | |
059d73ee | 853 | src_nents = sg_nents_for_len(req->src, src_len); |
f9970c28 LC |
854 | if (src_nents < 0) { |
855 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
856 | return src_nents; | |
857 | } | |
bc13c69e RK |
858 | |
859 | if (src_nents) { | |
860 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
861 | DMA_TO_DEVICE); | |
862 | if (!mapped_nents) { | |
863 | dev_err(jrdev, "unable to DMA map source\n"); | |
864 | return -ENOMEM; | |
865 | } | |
866 | } else { | |
867 | mapped_nents = 0; | |
868 | } | |
869 | ||
045e3678 | 870 | sec4_sg_src_index = 1 + (*buflen ? 1 : 0); |
a5e5c133 HG |
871 | pad_nents = pad_sg_nents(sec4_sg_src_index + mapped_nents); |
872 | sec4_sg_bytes = pad_nents * sizeof(struct sec4_sg_entry); | |
045e3678 YK |
873 | |
874 | /* | |
875 | * allocate space for base edesc and hw desc commands, | |
876 | * link tables | |
877 | */ | |
2ba1e798 IP |
878 | edesc = ahash_edesc_alloc(req, pad_nents, ctx->sh_desc_update, |
879 | ctx->sh_desc_update_dma); | |
045e3678 | 880 | if (!edesc) { |
bc13c69e | 881 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
882 | return -ENOMEM; |
883 | } | |
884 | ||
885 | edesc->src_nents = src_nents; | |
886 | edesc->sec4_sg_bytes = sec4_sg_bytes; | |
045e3678 | 887 | |
dfcd8393 | 888 | ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, |
ce572085 HG |
889 | edesc->sec4_sg, DMA_BIDIRECTIONAL); |
890 | if (ret) | |
58b0e5d0 | 891 | goto unmap_ctx; |
045e3678 | 892 | |
944c3d4d HG |
893 | ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state); |
894 | if (ret) | |
895 | goto unmap_ctx; | |
045e3678 | 896 | |
b4e9e931 | 897 | if (mapped_nents) |
059d73ee | 898 | sg_to_sec4_sg_last(req->src, src_len, |
bc13c69e RK |
899 | edesc->sec4_sg + sec4_sg_src_index, |
900 | 0); | |
b4e9e931 | 901 | else |
297b9ceb HG |
902 | sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index - |
903 | 1); | |
045e3678 | 904 | |
045e3678 | 905 | desc = edesc->hw_desc; |
045e3678 | 906 | |
1da2be33 RG |
907 | edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, |
908 | sec4_sg_bytes, | |
909 | DMA_TO_DEVICE); | |
ce572085 HG |
910 | if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { |
911 | dev_err(jrdev, "unable to map S/G table\n"); | |
32686d34 | 912 | ret = -ENOMEM; |
58b0e5d0 | 913 | goto unmap_ctx; |
ce572085 | 914 | } |
1da2be33 | 915 | |
045e3678 YK |
916 | append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + |
917 | to_hash, LDST_SGF); | |
918 | ||
919 | append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0); | |
920 | ||
6e005503 SH |
921 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
922 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
923 | desc_bytes(desc), 1); | |
045e3678 | 924 | |
21b014f0 IP |
925 | ret = ahash_enqueue_req(jrdev, ahash_done_bi, req, |
926 | ctx->ctx_len, DMA_BIDIRECTIONAL); | |
045e3678 | 927 | } else if (*next_buflen) { |
307fd543 CS |
928 | scatterwalk_map_and_copy(buf + *buflen, req->src, 0, |
929 | req->nbytes, 0); | |
045e3678 | 930 | *buflen = *next_buflen; |
6e005503 | 931 | |
46b49abc AB |
932 | print_hex_dump_debug("buf@" __stringify(__LINE__)": ", |
933 | DUMP_PREFIX_ADDRESS, 16, 4, buf, | |
934 | *buflen, 1); | |
935 | } | |
045e3678 YK |
936 | |
937 | return ret; | |
16c8ad7b | 938 | unmap_ctx: |
32686d34 RK |
939 | ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); |
940 | kfree(edesc); | |
941 | return ret; | |
045e3678 YK |
942 | } |
943 | ||
944 | static int ahash_final_ctx(struct ahash_request *req) | |
945 | { | |
946 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
947 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
948 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 949 | struct device *jrdev = ctx->jrdev; |
46b49abc | 950 | int buflen = state->buflen; |
30a43b44 | 951 | u32 *desc; |
a5e5c133 | 952 | int sec4_sg_bytes; |
045e3678 YK |
953 | int digestsize = crypto_ahash_digestsize(ahash); |
954 | struct ahash_edesc *edesc; | |
9e6df0fd | 955 | int ret; |
045e3678 | 956 | |
a5e5c133 HG |
957 | sec4_sg_bytes = pad_sg_nents(1 + (buflen ? 1 : 0)) * |
958 | sizeof(struct sec4_sg_entry); | |
045e3678 YK |
959 | |
960 | /* allocate space for base edesc and hw desc commands, link tables */ | |
2ba1e798 IP |
961 | edesc = ahash_edesc_alloc(req, 4, ctx->sh_desc_fin, |
962 | ctx->sh_desc_fin_dma); | |
5588d039 | 963 | if (!edesc) |
045e3678 | 964 | return -ENOMEM; |
045e3678 | 965 | |
045e3678 | 966 | desc = edesc->hw_desc; |
045e3678 YK |
967 | |
968 | edesc->sec4_sg_bytes = sec4_sg_bytes; | |
045e3678 | 969 | |
dfcd8393 | 970 | ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, |
c19650d6 | 971 | edesc->sec4_sg, DMA_BIDIRECTIONAL); |
ce572085 | 972 | if (ret) |
58b0e5d0 | 973 | goto unmap_ctx; |
045e3678 | 974 | |
944c3d4d HG |
975 | ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state); |
976 | if (ret) | |
977 | goto unmap_ctx; | |
978 | ||
a5e5c133 | 979 | sg_to_sec4_set_last(edesc->sec4_sg + (buflen ? 1 : 0)); |
045e3678 | 980 | |
1da2be33 RG |
981 | edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, |
982 | sec4_sg_bytes, DMA_TO_DEVICE); | |
ce572085 HG |
983 | if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { |
984 | dev_err(jrdev, "unable to map S/G table\n"); | |
32686d34 | 985 | ret = -ENOMEM; |
58b0e5d0 | 986 | goto unmap_ctx; |
ce572085 | 987 | } |
1da2be33 | 988 | |
045e3678 YK |
989 | append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen, |
990 | LDST_SGF); | |
c19650d6 | 991 | append_seq_out_ptr(desc, state->ctx_dma, digestsize, 0); |
045e3678 | 992 | |
6e005503 SH |
993 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
994 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
995 | 1); | |
045e3678 | 996 | |
21b014f0 IP |
997 | return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, |
998 | digestsize, DMA_BIDIRECTIONAL); | |
58b0e5d0 | 999 | unmap_ctx: |
c19650d6 | 1000 | ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL); |
32686d34 | 1001 | kfree(edesc); |
045e3678 YK |
1002 | return ret; |
1003 | } | |
1004 | ||
1005 | static int ahash_finup_ctx(struct ahash_request *req) | |
1006 | { | |
1007 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1008 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1009 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1010 | struct device *jrdev = ctx->jrdev; |
46b49abc | 1011 | int buflen = state->buflen; |
30a43b44 | 1012 | u32 *desc; |
65cf164a | 1013 | int sec4_sg_src_index; |
bc13c69e | 1014 | int src_nents, mapped_nents; |
045e3678 YK |
1015 | int digestsize = crypto_ahash_digestsize(ahash); |
1016 | struct ahash_edesc *edesc; | |
9e6df0fd | 1017 | int ret; |
045e3678 | 1018 | |
13fb8fd7 | 1019 | src_nents = sg_nents_for_len(req->src, req->nbytes); |
f9970c28 LC |
1020 | if (src_nents < 0) { |
1021 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
1022 | return src_nents; | |
1023 | } | |
bc13c69e RK |
1024 | |
1025 | if (src_nents) { | |
1026 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
1027 | DMA_TO_DEVICE); | |
1028 | if (!mapped_nents) { | |
1029 | dev_err(jrdev, "unable to DMA map source\n"); | |
1030 | return -ENOMEM; | |
1031 | } | |
1032 | } else { | |
1033 | mapped_nents = 0; | |
1034 | } | |
1035 | ||
045e3678 | 1036 | sec4_sg_src_index = 1 + (buflen ? 1 : 0); |
045e3678 YK |
1037 | |
1038 | /* allocate space for base edesc and hw desc commands, link tables */ | |
2ba1e798 IP |
1039 | edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, |
1040 | ctx->sh_desc_fin, ctx->sh_desc_fin_dma); | |
045e3678 | 1041 | if (!edesc) { |
bc13c69e | 1042 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
1043 | return -ENOMEM; |
1044 | } | |
1045 | ||
045e3678 | 1046 | desc = edesc->hw_desc; |
045e3678 YK |
1047 | |
1048 | edesc->src_nents = src_nents; | |
045e3678 | 1049 | |
dfcd8393 | 1050 | ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, |
c19650d6 | 1051 | edesc->sec4_sg, DMA_BIDIRECTIONAL); |
ce572085 | 1052 | if (ret) |
58b0e5d0 | 1053 | goto unmap_ctx; |
045e3678 | 1054 | |
944c3d4d HG |
1055 | ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state); |
1056 | if (ret) | |
1057 | goto unmap_ctx; | |
045e3678 | 1058 | |
65cf164a RK |
1059 | ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, |
1060 | sec4_sg_src_index, ctx->ctx_len + buflen, | |
1061 | req->nbytes); | |
1062 | if (ret) | |
58b0e5d0 | 1063 | goto unmap_ctx; |
045e3678 | 1064 | |
c19650d6 | 1065 | append_seq_out_ptr(desc, state->ctx_dma, digestsize, 0); |
045e3678 | 1066 | |
6e005503 SH |
1067 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1068 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
1069 | 1); | |
045e3678 | 1070 | |
21b014f0 IP |
1071 | return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, |
1072 | digestsize, DMA_BIDIRECTIONAL); | |
58b0e5d0 | 1073 | unmap_ctx: |
c19650d6 | 1074 | ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL); |
32686d34 | 1075 | kfree(edesc); |
045e3678 YK |
1076 | return ret; |
1077 | } | |
1078 | ||
1079 | static int ahash_digest(struct ahash_request *req) | |
1080 | { | |
1081 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1082 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1083 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1084 | struct device *jrdev = ctx->jrdev; |
30a43b44 | 1085 | u32 *desc; |
045e3678 | 1086 | int digestsize = crypto_ahash_digestsize(ahash); |
65cf164a | 1087 | int src_nents, mapped_nents; |
045e3678 | 1088 | struct ahash_edesc *edesc; |
9e6df0fd | 1089 | int ret; |
045e3678 | 1090 | |
944c3d4d HG |
1091 | state->buf_dma = 0; |
1092 | ||
3d5a2db6 | 1093 | src_nents = sg_nents_for_len(req->src, req->nbytes); |
f9970c28 LC |
1094 | if (src_nents < 0) { |
1095 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
1096 | return src_nents; | |
1097 | } | |
bc13c69e RK |
1098 | |
1099 | if (src_nents) { | |
1100 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
1101 | DMA_TO_DEVICE); | |
1102 | if (!mapped_nents) { | |
1103 | dev_err(jrdev, "unable to map source for DMA\n"); | |
1104 | return -ENOMEM; | |
1105 | } | |
1106 | } else { | |
1107 | mapped_nents = 0; | |
1108 | } | |
1109 | ||
045e3678 | 1110 | /* allocate space for base edesc and hw desc commands, link tables */ |
2ba1e798 IP |
1111 | edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? mapped_nents : 0, |
1112 | ctx->sh_desc_digest, ctx->sh_desc_digest_dma); | |
045e3678 | 1113 | if (!edesc) { |
bc13c69e | 1114 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
1115 | return -ENOMEM; |
1116 | } | |
343e44b1 | 1117 | |
045e3678 YK |
1118 | edesc->src_nents = src_nents; |
1119 | ||
65cf164a RK |
1120 | ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0, |
1121 | req->nbytes); | |
1122 | if (ret) { | |
1123 | ahash_unmap(jrdev, edesc, req, digestsize); | |
1124 | kfree(edesc); | |
1125 | return ret; | |
045e3678 | 1126 | } |
65cf164a RK |
1127 | |
1128 | desc = edesc->hw_desc; | |
045e3678 | 1129 | |
c19650d6 HG |
1130 | ret = map_seq_out_ptr_ctx(desc, jrdev, state, digestsize); |
1131 | if (ret) { | |
32686d34 RK |
1132 | ahash_unmap(jrdev, edesc, req, digestsize); |
1133 | kfree(edesc); | |
ce572085 HG |
1134 | return -ENOMEM; |
1135 | } | |
045e3678 | 1136 | |
6e005503 SH |
1137 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1138 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
1139 | 1); | |
045e3678 | 1140 | |
21b014f0 IP |
1141 | return ahash_enqueue_req(jrdev, ahash_done, req, digestsize, |
1142 | DMA_FROM_DEVICE); | |
045e3678 YK |
1143 | } |
1144 | ||
1145 | /* submit ahash final if it the first job descriptor */ | |
1146 | static int ahash_final_no_ctx(struct ahash_request *req) | |
1147 | { | |
1148 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1149 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1150 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1151 | struct device *jrdev = ctx->jrdev; |
46b49abc AB |
1152 | u8 *buf = state->buf; |
1153 | int buflen = state->buflen; | |
30a43b44 | 1154 | u32 *desc; |
045e3678 YK |
1155 | int digestsize = crypto_ahash_digestsize(ahash); |
1156 | struct ahash_edesc *edesc; | |
9e6df0fd | 1157 | int ret; |
045e3678 YK |
1158 | |
1159 | /* allocate space for base edesc and hw desc commands, link tables */ | |
2ba1e798 IP |
1160 | edesc = ahash_edesc_alloc(req, 0, ctx->sh_desc_digest, |
1161 | ctx->sh_desc_digest_dma); | |
5588d039 | 1162 | if (!edesc) |
045e3678 | 1163 | return -ENOMEM; |
045e3678 | 1164 | |
045e3678 | 1165 | desc = edesc->hw_desc; |
045e3678 | 1166 | |
04e6d25c AS |
1167 | if (buflen) { |
1168 | state->buf_dma = dma_map_single(jrdev, buf, buflen, | |
1169 | DMA_TO_DEVICE); | |
1170 | if (dma_mapping_error(jrdev, state->buf_dma)) { | |
1171 | dev_err(jrdev, "unable to map src\n"); | |
1172 | goto unmap; | |
1173 | } | |
045e3678 | 1174 | |
04e6d25c AS |
1175 | append_seq_in_ptr(desc, state->buf_dma, buflen, 0); |
1176 | } | |
045e3678 | 1177 | |
c19650d6 HG |
1178 | ret = map_seq_out_ptr_ctx(desc, jrdev, state, digestsize); |
1179 | if (ret) | |
06435f34 | 1180 | goto unmap; |
045e3678 | 1181 | |
6e005503 SH |
1182 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1183 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
1184 | 1); | |
045e3678 | 1185 | |
21b014f0 IP |
1186 | return ahash_enqueue_req(jrdev, ahash_done, req, |
1187 | digestsize, DMA_FROM_DEVICE); | |
06435f34 ME |
1188 | unmap: |
1189 | ahash_unmap(jrdev, edesc, req, digestsize); | |
1190 | kfree(edesc); | |
1191 | return -ENOMEM; | |
045e3678 YK |
1192 | } |
1193 | ||
1194 | /* submit ahash update if it the first job descriptor after update */ | |
1195 | static int ahash_update_no_ctx(struct ahash_request *req) | |
1196 | { | |
1197 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1198 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1199 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1200 | struct device *jrdev = ctx->jrdev; |
46b49abc AB |
1201 | u8 *buf = state->buf; |
1202 | int *buflen = &state->buflen; | |
1203 | int *next_buflen = &state->next_buflen; | |
12b8567f | 1204 | int blocksize = crypto_ahash_blocksize(ahash); |
045e3678 | 1205 | int in_len = *buflen + req->nbytes, to_hash; |
bc13c69e | 1206 | int sec4_sg_bytes, src_nents, mapped_nents; |
045e3678 | 1207 | struct ahash_edesc *edesc; |
30a43b44 | 1208 | u32 *desc; |
045e3678 | 1209 | int ret = 0; |
045e3678 | 1210 | |
12b8567f | 1211 | *next_buflen = in_len & (blocksize - 1); |
045e3678 YK |
1212 | to_hash = in_len - *next_buflen; |
1213 | ||
12b8567f | 1214 | /* |
87870cfb | 1215 | * For XCBC and CMAC, if to_hash is multiple of block size, |
12b8567f IP |
1216 | * keep last block in internal buffer |
1217 | */ | |
87870cfb IP |
1218 | if ((is_xcbc_aes(ctx->adata.algtype) || |
1219 | is_cmac_aes(ctx->adata.algtype)) && to_hash >= blocksize && | |
1220 | (*next_buflen == 0)) { | |
12b8567f IP |
1221 | *next_buflen = blocksize; |
1222 | to_hash -= blocksize; | |
1223 | } | |
1224 | ||
045e3678 | 1225 | if (to_hash) { |
a5e5c133 | 1226 | int pad_nents; |
059d73ee | 1227 | int src_len = req->nbytes - *next_buflen; |
a5e5c133 | 1228 | |
059d73ee | 1229 | src_nents = sg_nents_for_len(req->src, src_len); |
f9970c28 LC |
1230 | if (src_nents < 0) { |
1231 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
1232 | return src_nents; | |
1233 | } | |
bc13c69e RK |
1234 | |
1235 | if (src_nents) { | |
1236 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
1237 | DMA_TO_DEVICE); | |
1238 | if (!mapped_nents) { | |
1239 | dev_err(jrdev, "unable to DMA map source\n"); | |
1240 | return -ENOMEM; | |
1241 | } | |
1242 | } else { | |
1243 | mapped_nents = 0; | |
1244 | } | |
1245 | ||
a5e5c133 HG |
1246 | pad_nents = pad_sg_nents(1 + mapped_nents); |
1247 | sec4_sg_bytes = pad_nents * sizeof(struct sec4_sg_entry); | |
045e3678 YK |
1248 | |
1249 | /* | |
1250 | * allocate space for base edesc and hw desc commands, | |
1251 | * link tables | |
1252 | */ | |
2ba1e798 | 1253 | edesc = ahash_edesc_alloc(req, pad_nents, |
30a43b44 | 1254 | ctx->sh_desc_update_first, |
2ba1e798 | 1255 | ctx->sh_desc_update_first_dma); |
045e3678 | 1256 | if (!edesc) { |
bc13c69e | 1257 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
1258 | return -ENOMEM; |
1259 | } | |
1260 | ||
1261 | edesc->src_nents = src_nents; | |
1262 | edesc->sec4_sg_bytes = sec4_sg_bytes; | |
045e3678 | 1263 | |
944c3d4d HG |
1264 | ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state); |
1265 | if (ret) | |
1266 | goto unmap_ctx; | |
1267 | ||
059d73ee | 1268 | sg_to_sec4_sg_last(req->src, src_len, edesc->sec4_sg + 1, 0); |
bc13c69e | 1269 | |
045e3678 | 1270 | desc = edesc->hw_desc; |
045e3678 | 1271 | |
1da2be33 RG |
1272 | edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, |
1273 | sec4_sg_bytes, | |
1274 | DMA_TO_DEVICE); | |
ce572085 HG |
1275 | if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { |
1276 | dev_err(jrdev, "unable to map S/G table\n"); | |
32686d34 | 1277 | ret = -ENOMEM; |
58b0e5d0 | 1278 | goto unmap_ctx; |
ce572085 | 1279 | } |
1da2be33 | 1280 | |
045e3678 YK |
1281 | append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF); |
1282 | ||
ce572085 HG |
1283 | ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); |
1284 | if (ret) | |
58b0e5d0 | 1285 | goto unmap_ctx; |
045e3678 | 1286 | |
6e005503 SH |
1287 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1288 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
1289 | desc_bytes(desc), 1); | |
045e3678 | 1290 | |
21b014f0 IP |
1291 | ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, |
1292 | ctx->ctx_len, DMA_TO_DEVICE); | |
1293 | if ((ret != -EINPROGRESS) && (ret != -EBUSY)) | |
1294 | return ret; | |
32686d34 RK |
1295 | state->update = ahash_update_ctx; |
1296 | state->finup = ahash_finup_ctx; | |
1297 | state->final = ahash_final_ctx; | |
045e3678 | 1298 | } else if (*next_buflen) { |
307fd543 CS |
1299 | scatterwalk_map_and_copy(buf + *buflen, req->src, 0, |
1300 | req->nbytes, 0); | |
045e3678 | 1301 | *buflen = *next_buflen; |
6e005503 | 1302 | |
46b49abc AB |
1303 | print_hex_dump_debug("buf@" __stringify(__LINE__)": ", |
1304 | DUMP_PREFIX_ADDRESS, 16, 4, buf, | |
1305 | *buflen, 1); | |
1306 | } | |
045e3678 YK |
1307 | |
1308 | return ret; | |
58b0e5d0 | 1309 | unmap_ctx: |
32686d34 RK |
1310 | ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); |
1311 | kfree(edesc); | |
1312 | return ret; | |
045e3678 YK |
1313 | } |
1314 | ||
1315 | /* submit ahash finup if it the first job descriptor after update */ | |
1316 | static int ahash_finup_no_ctx(struct ahash_request *req) | |
1317 | { | |
1318 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1319 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1320 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1321 | struct device *jrdev = ctx->jrdev; |
46b49abc | 1322 | int buflen = state->buflen; |
30a43b44 | 1323 | u32 *desc; |
bc13c69e | 1324 | int sec4_sg_bytes, sec4_sg_src_index, src_nents, mapped_nents; |
045e3678 YK |
1325 | int digestsize = crypto_ahash_digestsize(ahash); |
1326 | struct ahash_edesc *edesc; | |
9e6df0fd | 1327 | int ret; |
045e3678 | 1328 | |
13fb8fd7 | 1329 | src_nents = sg_nents_for_len(req->src, req->nbytes); |
f9970c28 LC |
1330 | if (src_nents < 0) { |
1331 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
1332 | return src_nents; | |
1333 | } | |
bc13c69e RK |
1334 | |
1335 | if (src_nents) { | |
1336 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
1337 | DMA_TO_DEVICE); | |
1338 | if (!mapped_nents) { | |
1339 | dev_err(jrdev, "unable to DMA map source\n"); | |
1340 | return -ENOMEM; | |
1341 | } | |
1342 | } else { | |
1343 | mapped_nents = 0; | |
1344 | } | |
1345 | ||
045e3678 | 1346 | sec4_sg_src_index = 2; |
bc13c69e | 1347 | sec4_sg_bytes = (sec4_sg_src_index + mapped_nents) * |
045e3678 YK |
1348 | sizeof(struct sec4_sg_entry); |
1349 | ||
1350 | /* allocate space for base edesc and hw desc commands, link tables */ | |
2ba1e798 IP |
1351 | edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, |
1352 | ctx->sh_desc_digest, ctx->sh_desc_digest_dma); | |
045e3678 | 1353 | if (!edesc) { |
bc13c69e | 1354 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
1355 | return -ENOMEM; |
1356 | } | |
1357 | ||
045e3678 | 1358 | desc = edesc->hw_desc; |
045e3678 YK |
1359 | |
1360 | edesc->src_nents = src_nents; | |
1361 | edesc->sec4_sg_bytes = sec4_sg_bytes; | |
045e3678 | 1362 | |
944c3d4d HG |
1363 | ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state); |
1364 | if (ret) | |
1365 | goto unmap; | |
045e3678 | 1366 | |
65cf164a RK |
1367 | ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 1, buflen, |
1368 | req->nbytes); | |
1369 | if (ret) { | |
ce572085 | 1370 | dev_err(jrdev, "unable to map S/G table\n"); |
06435f34 | 1371 | goto unmap; |
ce572085 | 1372 | } |
1da2be33 | 1373 | |
c19650d6 HG |
1374 | ret = map_seq_out_ptr_ctx(desc, jrdev, state, digestsize); |
1375 | if (ret) | |
06435f34 | 1376 | goto unmap; |
045e3678 | 1377 | |
6e005503 SH |
1378 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1379 | DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), | |
1380 | 1); | |
045e3678 | 1381 | |
21b014f0 IP |
1382 | return ahash_enqueue_req(jrdev, ahash_done, req, |
1383 | digestsize, DMA_FROM_DEVICE); | |
06435f34 ME |
1384 | unmap: |
1385 | ahash_unmap(jrdev, edesc, req, digestsize); | |
1386 | kfree(edesc); | |
1387 | return -ENOMEM; | |
1388 | ||
045e3678 YK |
1389 | } |
1390 | ||
1391 | /* submit first update job descriptor after init */ | |
1392 | static int ahash_update_first(struct ahash_request *req) | |
1393 | { | |
1394 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | |
4cb4f7c1 HX |
1395 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
1396 | struct caam_hash_state *state = ahash_request_ctx_dma(req); | |
045e3678 | 1397 | struct device *jrdev = ctx->jrdev; |
46b49abc AB |
1398 | u8 *buf = state->buf; |
1399 | int *buflen = &state->buflen; | |
1400 | int *next_buflen = &state->next_buflen; | |
045e3678 | 1401 | int to_hash; |
12b8567f | 1402 | int blocksize = crypto_ahash_blocksize(ahash); |
30a43b44 | 1403 | u32 *desc; |
65cf164a | 1404 | int src_nents, mapped_nents; |
045e3678 YK |
1405 | struct ahash_edesc *edesc; |
1406 | int ret = 0; | |
045e3678 | 1407 | |
12b8567f | 1408 | *next_buflen = req->nbytes & (blocksize - 1); |
045e3678 YK |
1409 | to_hash = req->nbytes - *next_buflen; |
1410 | ||
12b8567f | 1411 | /* |
87870cfb | 1412 | * For XCBC and CMAC, if to_hash is multiple of block size, |
12b8567f IP |
1413 | * keep last block in internal buffer |
1414 | */ | |
87870cfb IP |
1415 | if ((is_xcbc_aes(ctx->adata.algtype) || |
1416 | is_cmac_aes(ctx->adata.algtype)) && to_hash >= blocksize && | |
1417 | (*next_buflen == 0)) { | |
12b8567f IP |
1418 | *next_buflen = blocksize; |
1419 | to_hash -= blocksize; | |
1420 | } | |
1421 | ||
045e3678 | 1422 | if (to_hash) { |
3d5a2db6 RK |
1423 | src_nents = sg_nents_for_len(req->src, |
1424 | req->nbytes - *next_buflen); | |
f9970c28 LC |
1425 | if (src_nents < 0) { |
1426 | dev_err(jrdev, "Invalid number of src SG.\n"); | |
1427 | return src_nents; | |
1428 | } | |
bc13c69e RK |
1429 | |
1430 | if (src_nents) { | |
1431 | mapped_nents = dma_map_sg(jrdev, req->src, src_nents, | |
1432 | DMA_TO_DEVICE); | |
1433 | if (!mapped_nents) { | |
1434 | dev_err(jrdev, "unable to map source for DMA\n"); | |
1435 | return -ENOMEM; | |
1436 | } | |
1437 | } else { | |
1438 | mapped_nents = 0; | |
1439 | } | |
045e3678 YK |
1440 | |
1441 | /* | |
1442 | * allocate space for base edesc and hw desc commands, | |
1443 | * link tables | |
1444 | */ | |
2ba1e798 | 1445 | edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? |
30a43b44 RK |
1446 | mapped_nents : 0, |
1447 | ctx->sh_desc_update_first, | |
2ba1e798 | 1448 | ctx->sh_desc_update_first_dma); |
045e3678 | 1449 | if (!edesc) { |
bc13c69e | 1450 | dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); |
045e3678 YK |
1451 | return -ENOMEM; |
1452 | } | |
1453 | ||
1454 | edesc->src_nents = src_nents; | |
045e3678 | 1455 | |
65cf164a RK |
1456 | ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0, |
1457 | to_hash); | |
1458 | if (ret) | |
58b0e5d0 | 1459 | goto unmap_ctx; |
045e3678 | 1460 | |
045e3678 | 1461 | desc = edesc->hw_desc; |
045e3678 | 1462 | |
ce572085 HG |
1463 | ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); |
1464 | if (ret) | |
58b0e5d0 | 1465 | goto unmap_ctx; |
045e3678 | 1466 | |
6e005503 SH |
1467 | print_hex_dump_debug("jobdesc@"__stringify(__LINE__)": ", |
1468 | DUMP_PREFIX_ADDRESS, 16, 4, desc, | |
1469 | desc_bytes(desc), 1); | |
045e3678 | 1470 | |
21b014f0 IP |
1471 | ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, |
1472 | ctx->ctx_len, DMA_TO_DEVICE); | |
1473 | if ((ret != -EINPROGRESS) && (ret != -EBUSY)) | |
1474 | return ret; | |
32686d34 RK |
1475 | state->update = ahash_update_ctx; |
1476 | state->finup = ahash_finup_ctx; | |
1477 | state->final = ahash_final_ctx; | |
045e3678 YK |
1478 | } else if (*next_buflen) { |
1479 | state->update = ahash_update_no_ctx; | |
1480 | state->finup = ahash_finup_no_ctx; | |
1481 | state->final = ahash_final_no_ctx; | |
46b49abc | 1482 | scatterwalk_map_and_copy(buf, req->src, 0, |
307fd543 | 1483 | req->nbytes, 0); |
46b49abc | 1484 | *buflen = *next_buflen; |
6e005503 | 1485 | |
46b49abc AB |
1486 | print_hex_dump_debug("buf@" __stringify(__LINE__)": ", |
1487 | DUMP_PREFIX_ADDRESS, 16, 4, buf, | |
1488 | *buflen, 1); | |
1489 | } | |
045e3678 YK |
1490 | |
1491 | return ret; | |
58b0e5d0 | 1492 | unmap_ctx: |
32686d34 RK |
1493 | ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); |
1494 | kfree(edesc); | |
1495 | return ret; | |
045e3678 YK |
1496 | } |
1497 | ||
1498 | static int ahash_finup_first(struct ahash_request *req) | |
1499 | { | |
1500 | return ahash_digest(req); | |
1501 | } | |
1502 | ||
1503 | static int ahash_init(struct ahash_request *req) | |
1504 | { | |
4cb4f7c1 | 1505 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
045e3678 YK |
1506 | |
1507 | state->update = ahash_update_first; | |
1508 | state->finup = ahash_finup_first; | |
1509 | state->final = ahash_final_no_ctx; | |
1510 | ||
87ec02e7 | 1511 | state->ctx_dma = 0; |
65055e21 | 1512 | state->ctx_dma_len = 0; |
de0e35ec | 1513 | state->buf_dma = 0; |
46b49abc AB |
1514 | state->buflen = 0; |
1515 | state->next_buflen = 0; | |
045e3678 YK |
1516 | |
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | static int ahash_update(struct ahash_request *req) | |
1521 | { | |
4cb4f7c1 | 1522 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
045e3678 YK |
1523 | |
1524 | return state->update(req); | |
1525 | } | |
1526 | ||
1527 | static int ahash_finup(struct ahash_request *req) | |
1528 | { | |
4cb4f7c1 | 1529 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
045e3678 YK |
1530 | |
1531 | return state->finup(req); | |
1532 | } | |
1533 | ||
1534 | static int ahash_final(struct ahash_request *req) | |
1535 | { | |
4cb4f7c1 | 1536 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
045e3678 YK |
1537 | |
1538 | return state->final(req); | |
1539 | } | |
1540 | ||
1541 | static int ahash_export(struct ahash_request *req, void *out) | |
1542 | { | |
4cb4f7c1 | 1543 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
5ec90831 | 1544 | struct caam_export_state *export = out; |
46b49abc AB |
1545 | u8 *buf = state->buf; |
1546 | int len = state->buflen; | |
5ec90831 RK |
1547 | |
1548 | memcpy(export->buf, buf, len); | |
1549 | memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx)); | |
1550 | export->buflen = len; | |
1551 | export->update = state->update; | |
1552 | export->final = state->final; | |
1553 | export->finup = state->finup; | |
434b4212 | 1554 | |
045e3678 YK |
1555 | return 0; |
1556 | } | |
1557 | ||
1558 | static int ahash_import(struct ahash_request *req, const void *in) | |
1559 | { | |
4cb4f7c1 | 1560 | struct caam_hash_state *state = ahash_request_ctx_dma(req); |
5ec90831 | 1561 | const struct caam_export_state *export = in; |
045e3678 | 1562 | |
5ec90831 | 1563 | memset(state, 0, sizeof(*state)); |
46b49abc | 1564 | memcpy(state->buf, export->buf, export->buflen); |
5ec90831 | 1565 | memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx)); |
46b49abc | 1566 | state->buflen = export->buflen; |
5ec90831 RK |
1567 | state->update = export->update; |
1568 | state->final = export->final; | |
1569 | state->finup = export->finup; | |
434b4212 | 1570 | |
045e3678 YK |
1571 | return 0; |
1572 | } | |
1573 | ||
1574 | struct caam_hash_template { | |
1575 | char name[CRYPTO_MAX_ALG_NAME]; | |
1576 | char driver_name[CRYPTO_MAX_ALG_NAME]; | |
b0e09bae YK |
1577 | char hmac_name[CRYPTO_MAX_ALG_NAME]; |
1578 | char hmac_driver_name[CRYPTO_MAX_ALG_NAME]; | |
045e3678 YK |
1579 | unsigned int blocksize; |
1580 | struct ahash_alg template_ahash; | |
1581 | u32 alg_type; | |
045e3678 YK |
1582 | }; |
1583 | ||
1584 | /* ahash descriptors */ | |
1585 | static struct caam_hash_template driver_hash[] = { | |
1586 | { | |
b0e09bae YK |
1587 | .name = "sha1", |
1588 | .driver_name = "sha1-caam", | |
1589 | .hmac_name = "hmac(sha1)", | |
1590 | .hmac_driver_name = "hmac-sha1-caam", | |
045e3678 YK |
1591 | .blocksize = SHA1_BLOCK_SIZE, |
1592 | .template_ahash = { | |
1593 | .init = ahash_init, | |
1594 | .update = ahash_update, | |
1595 | .final = ahash_final, | |
1596 | .finup = ahash_finup, | |
1597 | .digest = ahash_digest, | |
1598 | .export = ahash_export, | |
1599 | .import = ahash_import, | |
1600 | .setkey = ahash_setkey, | |
1601 | .halg = { | |
1602 | .digestsize = SHA1_DIGEST_SIZE, | |
5ec90831 | 1603 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1604 | }, |
659f313d | 1605 | }, |
045e3678 | 1606 | .alg_type = OP_ALG_ALGSEL_SHA1, |
045e3678 | 1607 | }, { |
b0e09bae YK |
1608 | .name = "sha224", |
1609 | .driver_name = "sha224-caam", | |
1610 | .hmac_name = "hmac(sha224)", | |
1611 | .hmac_driver_name = "hmac-sha224-caam", | |
045e3678 YK |
1612 | .blocksize = SHA224_BLOCK_SIZE, |
1613 | .template_ahash = { | |
1614 | .init = ahash_init, | |
1615 | .update = ahash_update, | |
1616 | .final = ahash_final, | |
1617 | .finup = ahash_finup, | |
1618 | .digest = ahash_digest, | |
1619 | .export = ahash_export, | |
1620 | .import = ahash_import, | |
1621 | .setkey = ahash_setkey, | |
1622 | .halg = { | |
1623 | .digestsize = SHA224_DIGEST_SIZE, | |
5ec90831 | 1624 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1625 | }, |
659f313d | 1626 | }, |
045e3678 | 1627 | .alg_type = OP_ALG_ALGSEL_SHA224, |
045e3678 | 1628 | }, { |
b0e09bae YK |
1629 | .name = "sha256", |
1630 | .driver_name = "sha256-caam", | |
1631 | .hmac_name = "hmac(sha256)", | |
1632 | .hmac_driver_name = "hmac-sha256-caam", | |
045e3678 YK |
1633 | .blocksize = SHA256_BLOCK_SIZE, |
1634 | .template_ahash = { | |
1635 | .init = ahash_init, | |
1636 | .update = ahash_update, | |
1637 | .final = ahash_final, | |
1638 | .finup = ahash_finup, | |
1639 | .digest = ahash_digest, | |
1640 | .export = ahash_export, | |
1641 | .import = ahash_import, | |
1642 | .setkey = ahash_setkey, | |
1643 | .halg = { | |
1644 | .digestsize = SHA256_DIGEST_SIZE, | |
5ec90831 | 1645 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1646 | }, |
659f313d | 1647 | }, |
045e3678 | 1648 | .alg_type = OP_ALG_ALGSEL_SHA256, |
045e3678 | 1649 | }, { |
b0e09bae YK |
1650 | .name = "sha384", |
1651 | .driver_name = "sha384-caam", | |
1652 | .hmac_name = "hmac(sha384)", | |
1653 | .hmac_driver_name = "hmac-sha384-caam", | |
045e3678 YK |
1654 | .blocksize = SHA384_BLOCK_SIZE, |
1655 | .template_ahash = { | |
1656 | .init = ahash_init, | |
1657 | .update = ahash_update, | |
1658 | .final = ahash_final, | |
1659 | .finup = ahash_finup, | |
1660 | .digest = ahash_digest, | |
1661 | .export = ahash_export, | |
1662 | .import = ahash_import, | |
1663 | .setkey = ahash_setkey, | |
1664 | .halg = { | |
1665 | .digestsize = SHA384_DIGEST_SIZE, | |
5ec90831 | 1666 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1667 | }, |
659f313d | 1668 | }, |
045e3678 | 1669 | .alg_type = OP_ALG_ALGSEL_SHA384, |
045e3678 | 1670 | }, { |
b0e09bae YK |
1671 | .name = "sha512", |
1672 | .driver_name = "sha512-caam", | |
1673 | .hmac_name = "hmac(sha512)", | |
1674 | .hmac_driver_name = "hmac-sha512-caam", | |
045e3678 YK |
1675 | .blocksize = SHA512_BLOCK_SIZE, |
1676 | .template_ahash = { | |
1677 | .init = ahash_init, | |
1678 | .update = ahash_update, | |
1679 | .final = ahash_final, | |
1680 | .finup = ahash_finup, | |
1681 | .digest = ahash_digest, | |
1682 | .export = ahash_export, | |
1683 | .import = ahash_import, | |
1684 | .setkey = ahash_setkey, | |
1685 | .halg = { | |
1686 | .digestsize = SHA512_DIGEST_SIZE, | |
5ec90831 | 1687 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1688 | }, |
659f313d | 1689 | }, |
045e3678 | 1690 | .alg_type = OP_ALG_ALGSEL_SHA512, |
045e3678 | 1691 | }, { |
b0e09bae YK |
1692 | .name = "md5", |
1693 | .driver_name = "md5-caam", | |
1694 | .hmac_name = "hmac(md5)", | |
1695 | .hmac_driver_name = "hmac-md5-caam", | |
045e3678 YK |
1696 | .blocksize = MD5_BLOCK_WORDS * 4, |
1697 | .template_ahash = { | |
1698 | .init = ahash_init, | |
1699 | .update = ahash_update, | |
1700 | .final = ahash_final, | |
1701 | .finup = ahash_finup, | |
1702 | .digest = ahash_digest, | |
1703 | .export = ahash_export, | |
1704 | .import = ahash_import, | |
1705 | .setkey = ahash_setkey, | |
1706 | .halg = { | |
1707 | .digestsize = MD5_DIGEST_SIZE, | |
5ec90831 | 1708 | .statesize = sizeof(struct caam_export_state), |
045e3678 | 1709 | }, |
659f313d | 1710 | }, |
045e3678 | 1711 | .alg_type = OP_ALG_ALGSEL_MD5, |
12b8567f IP |
1712 | }, { |
1713 | .hmac_name = "xcbc(aes)", | |
1714 | .hmac_driver_name = "xcbc-aes-caam", | |
1715 | .blocksize = AES_BLOCK_SIZE, | |
1716 | .template_ahash = { | |
1717 | .init = ahash_init, | |
1718 | .update = ahash_update, | |
1719 | .final = ahash_final, | |
1720 | .finup = ahash_finup, | |
1721 | .digest = ahash_digest, | |
1722 | .export = ahash_export, | |
1723 | .import = ahash_import, | |
1724 | .setkey = axcbc_setkey, | |
1725 | .halg = { | |
1726 | .digestsize = AES_BLOCK_SIZE, | |
1727 | .statesize = sizeof(struct caam_export_state), | |
1728 | }, | |
1729 | }, | |
1730 | .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC, | |
87870cfb IP |
1731 | }, { |
1732 | .hmac_name = "cmac(aes)", | |
1733 | .hmac_driver_name = "cmac-aes-caam", | |
1734 | .blocksize = AES_BLOCK_SIZE, | |
1735 | .template_ahash = { | |
1736 | .init = ahash_init, | |
1737 | .update = ahash_update, | |
1738 | .final = ahash_final, | |
1739 | .finup = ahash_finup, | |
1740 | .digest = ahash_digest, | |
1741 | .export = ahash_export, | |
1742 | .import = ahash_import, | |
1743 | .setkey = acmac_setkey, | |
1744 | .halg = { | |
1745 | .digestsize = AES_BLOCK_SIZE, | |
1746 | .statesize = sizeof(struct caam_export_state), | |
1747 | }, | |
1748 | }, | |
1749 | .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CMAC, | |
045e3678 YK |
1750 | }, |
1751 | }; | |
1752 | ||
1753 | struct caam_hash_alg { | |
1754 | struct list_head entry; | |
045e3678 | 1755 | int alg_type; |
c5a2f74d | 1756 | bool is_hmac; |
623814c0 | 1757 | struct ahash_engine_alg ahash_alg; |
045e3678 YK |
1758 | }; |
1759 | ||
1760 | static int caam_hash_cra_init(struct crypto_tfm *tfm) | |
1761 | { | |
1762 | struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); | |
1763 | struct crypto_alg *base = tfm->__crt_alg; | |
1764 | struct hash_alg_common *halg = | |
1765 | container_of(base, struct hash_alg_common, base); | |
1766 | struct ahash_alg *alg = | |
1767 | container_of(halg, struct ahash_alg, halg); | |
1768 | struct caam_hash_alg *caam_hash = | |
623814c0 | 1769 | container_of(alg, struct caam_hash_alg, ahash_alg.base); |
4cb4f7c1 | 1770 | struct caam_hash_ctx *ctx = crypto_ahash_ctx_dma(ahash); |
045e3678 YK |
1771 | /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */ |
1772 | static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE, | |
1773 | HASH_MSG_LEN + SHA1_DIGEST_SIZE, | |
1774 | HASH_MSG_LEN + 32, | |
1775 | HASH_MSG_LEN + SHA256_DIGEST_SIZE, | |
1776 | HASH_MSG_LEN + 64, | |
1777 | HASH_MSG_LEN + SHA512_DIGEST_SIZE }; | |
21b014f0 IP |
1778 | const size_t sh_desc_update_offset = offsetof(struct caam_hash_ctx, |
1779 | sh_desc_update); | |
bbf22344 | 1780 | dma_addr_t dma_addr; |
7e0880b9 | 1781 | struct caam_drv_private *priv; |
045e3678 YK |
1782 | |
1783 | /* | |
cfc6f11b | 1784 | * Get a Job ring from Job Ring driver to ensure in-order |
045e3678 YK |
1785 | * crypto request processing per tfm |
1786 | */ | |
cfc6f11b RG |
1787 | ctx->jrdev = caam_jr_alloc(); |
1788 | if (IS_ERR(ctx->jrdev)) { | |
1789 | pr_err("Job Ring Device allocation for transform failed\n"); | |
1790 | return PTR_ERR(ctx->jrdev); | |
1791 | } | |
bbf22344 | 1792 | |
7e0880b9 | 1793 | priv = dev_get_drvdata(ctx->jrdev->parent); |
12b8567f IP |
1794 | |
1795 | if (is_xcbc_aes(caam_hash->alg_type)) { | |
1796 | ctx->dir = DMA_TO_DEVICE; | |
e9b4913a | 1797 | ctx->key_dir = DMA_BIDIRECTIONAL; |
12b8567f IP |
1798 | ctx->adata.algtype = OP_TYPE_CLASS1_ALG | caam_hash->alg_type; |
1799 | ctx->ctx_len = 48; | |
87870cfb IP |
1800 | } else if (is_cmac_aes(caam_hash->alg_type)) { |
1801 | ctx->dir = DMA_TO_DEVICE; | |
e9b4913a | 1802 | ctx->key_dir = DMA_NONE; |
87870cfb IP |
1803 | ctx->adata.algtype = OP_TYPE_CLASS1_ALG | caam_hash->alg_type; |
1804 | ctx->ctx_len = 32; | |
12b8567f | 1805 | } else { |
e9b4913a HG |
1806 | if (priv->era >= 6) { |
1807 | ctx->dir = DMA_BIDIRECTIONAL; | |
c5a2f74d | 1808 | ctx->key_dir = caam_hash->is_hmac ? DMA_TO_DEVICE : DMA_NONE; |
e9b4913a HG |
1809 | } else { |
1810 | ctx->dir = DMA_TO_DEVICE; | |
1811 | ctx->key_dir = DMA_NONE; | |
1812 | } | |
12b8567f IP |
1813 | ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type; |
1814 | ctx->ctx_len = runninglen[(ctx->adata.algtype & | |
1815 | OP_ALG_ALGSEL_SUBMASK) >> | |
1816 | OP_ALG_ALGSEL_SHIFT]; | |
1817 | } | |
7e0880b9 | 1818 | |
e9b4913a HG |
1819 | if (ctx->key_dir != DMA_NONE) { |
1820 | ctx->adata.key_dma = dma_map_single_attrs(ctx->jrdev, ctx->key, | |
1821 | ARRAY_SIZE(ctx->key), | |
1822 | ctx->key_dir, | |
1823 | DMA_ATTR_SKIP_CPU_SYNC); | |
1824 | if (dma_mapping_error(ctx->jrdev, ctx->adata.key_dma)) { | |
1825 | dev_err(ctx->jrdev, "unable to map key\n"); | |
1826 | caam_jr_free(ctx->jrdev); | |
1827 | return -ENOMEM; | |
1828 | } | |
1829 | } | |
1830 | ||
bbf22344 | 1831 | dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_update, |
21b014f0 IP |
1832 | offsetof(struct caam_hash_ctx, key) - |
1833 | sh_desc_update_offset, | |
7e0880b9 | 1834 | ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); |
bbf22344 HG |
1835 | if (dma_mapping_error(ctx->jrdev, dma_addr)) { |
1836 | dev_err(ctx->jrdev, "unable to map shared descriptors\n"); | |
12b8567f | 1837 | |
e9b4913a | 1838 | if (ctx->key_dir != DMA_NONE) |
a2fb864c | 1839 | dma_unmap_single_attrs(ctx->jrdev, ctx->adata.key_dma, |
12b8567f | 1840 | ARRAY_SIZE(ctx->key), |
e9b4913a | 1841 | ctx->key_dir, |
12b8567f IP |
1842 | DMA_ATTR_SKIP_CPU_SYNC); |
1843 | ||
bbf22344 HG |
1844 | caam_jr_free(ctx->jrdev); |
1845 | return -ENOMEM; | |
1846 | } | |
1847 | ||
1848 | ctx->sh_desc_update_dma = dma_addr; | |
1849 | ctx->sh_desc_update_first_dma = dma_addr + | |
1850 | offsetof(struct caam_hash_ctx, | |
21b014f0 IP |
1851 | sh_desc_update_first) - |
1852 | sh_desc_update_offset; | |
bbf22344 | 1853 | ctx->sh_desc_fin_dma = dma_addr + offsetof(struct caam_hash_ctx, |
21b014f0 IP |
1854 | sh_desc_fin) - |
1855 | sh_desc_update_offset; | |
bbf22344 | 1856 | ctx->sh_desc_digest_dma = dma_addr + offsetof(struct caam_hash_ctx, |
21b014f0 IP |
1857 | sh_desc_digest) - |
1858 | sh_desc_update_offset; | |
1859 | ||
4cb4f7c1 | 1860 | crypto_ahash_set_reqsize_dma(ahash, sizeof(struct caam_hash_state)); |
9a2537d0 IP |
1861 | |
1862 | /* | |
1863 | * For keyed hash algorithms shared descriptors | |
1864 | * will be created later in setkey() callback | |
1865 | */ | |
c5a2f74d | 1866 | return caam_hash->is_hmac ? 0 : ahash_set_sh_desc(ahash); |
045e3678 YK |
1867 | } |
1868 | ||
1869 | static void caam_hash_cra_exit(struct crypto_tfm *tfm) | |
1870 | { | |
4cb4f7c1 | 1871 | struct caam_hash_ctx *ctx = crypto_tfm_ctx_dma(tfm); |
045e3678 | 1872 | |
bbf22344 | 1873 | dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_update_dma, |
21b014f0 IP |
1874 | offsetof(struct caam_hash_ctx, key) - |
1875 | offsetof(struct caam_hash_ctx, sh_desc_update), | |
7e0880b9 | 1876 | ctx->dir, DMA_ATTR_SKIP_CPU_SYNC); |
e9b4913a | 1877 | if (ctx->key_dir != DMA_NONE) |
a2fb864c | 1878 | dma_unmap_single_attrs(ctx->jrdev, ctx->adata.key_dma, |
e9b4913a | 1879 | ARRAY_SIZE(ctx->key), ctx->key_dir, |
12b8567f | 1880 | DMA_ATTR_SKIP_CPU_SYNC); |
cfc6f11b | 1881 | caam_jr_free(ctx->jrdev); |
045e3678 YK |
1882 | } |
1883 | ||
1b46c90c | 1884 | void caam_algapi_hash_exit(void) |
045e3678 | 1885 | { |
045e3678 YK |
1886 | struct caam_hash_alg *t_alg, *n; |
1887 | ||
cfc6f11b | 1888 | if (!hash_list.next) |
045e3678 YK |
1889 | return; |
1890 | ||
cfc6f11b | 1891 | list_for_each_entry_safe(t_alg, n, &hash_list, entry) { |
623814c0 | 1892 | crypto_engine_unregister_ahash(&t_alg->ahash_alg); |
045e3678 YK |
1893 | list_del(&t_alg->entry); |
1894 | kfree(t_alg); | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | static struct caam_hash_alg * | |
cfc6f11b | 1899 | caam_hash_alloc(struct caam_hash_template *template, |
b0e09bae | 1900 | bool keyed) |
045e3678 YK |
1901 | { |
1902 | struct caam_hash_alg *t_alg; | |
1903 | struct ahash_alg *halg; | |
1904 | struct crypto_alg *alg; | |
1905 | ||
9c4f9733 | 1906 | t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); |
3de0152b | 1907 | if (!t_alg) |
045e3678 | 1908 | return ERR_PTR(-ENOMEM); |
045e3678 | 1909 | |
623814c0 HX |
1910 | t_alg->ahash_alg.base = template->template_ahash; |
1911 | halg = &t_alg->ahash_alg.base; | |
045e3678 YK |
1912 | alg = &halg->halg.base; |
1913 | ||
b0e09bae YK |
1914 | if (keyed) { |
1915 | snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", | |
1916 | template->hmac_name); | |
1917 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", | |
1918 | template->hmac_driver_name); | |
c5a2f74d | 1919 | t_alg->is_hmac = true; |
b0e09bae YK |
1920 | } else { |
1921 | snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", | |
1922 | template->name); | |
1923 | snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", | |
1924 | template->driver_name); | |
623814c0 | 1925 | halg->setkey = NULL; |
c5a2f74d | 1926 | t_alg->is_hmac = false; |
b0e09bae | 1927 | } |
045e3678 YK |
1928 | alg->cra_module = THIS_MODULE; |
1929 | alg->cra_init = caam_hash_cra_init; | |
1930 | alg->cra_exit = caam_hash_cra_exit; | |
4cb4f7c1 | 1931 | alg->cra_ctxsize = sizeof(struct caam_hash_ctx) + crypto_dma_padding(); |
045e3678 YK |
1932 | alg->cra_priority = CAAM_CRA_PRIORITY; |
1933 | alg->cra_blocksize = template->blocksize; | |
1934 | alg->cra_alignmask = 0; | |
b8aa7dc5 | 1935 | alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY; |
045e3678 YK |
1936 | |
1937 | t_alg->alg_type = template->alg_type; | |
623814c0 | 1938 | t_alg->ahash_alg.op.do_one_request = ahash_do_one_req; |
045e3678 YK |
1939 | |
1940 | return t_alg; | |
1941 | } | |
1942 | ||
1b46c90c | 1943 | int caam_algapi_hash_init(struct device *ctrldev) |
045e3678 | 1944 | { |
045e3678 | 1945 | int i = 0, err = 0; |
1b46c90c | 1946 | struct caam_drv_private *priv = dev_get_drvdata(ctrldev); |
bf83490e | 1947 | unsigned int md_limit = SHA512_DIGEST_SIZE; |
d239b10d | 1948 | u32 md_inst, md_vid; |
045e3678 | 1949 | |
bf83490e VM |
1950 | /* |
1951 | * Register crypto algorithms the device supports. First, identify | |
1952 | * presence and attributes of MD block. | |
1953 | */ | |
d239b10d | 1954 | if (priv->era < 10) { |
ae1dd17d HG |
1955 | struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; |
1956 | ||
1957 | md_vid = (rd_reg32(&perfmon->cha_id_ls) & | |
d239b10d | 1958 | CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; |
ae1dd17d | 1959 | md_inst = (rd_reg32(&perfmon->cha_num_ls) & |
d239b10d HG |
1960 | CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; |
1961 | } else { | |
ae1dd17d | 1962 | u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha); |
d239b10d HG |
1963 | |
1964 | md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; | |
1965 | md_inst = mdha & CHA_VER_NUM_MASK; | |
1966 | } | |
bf83490e VM |
1967 | |
1968 | /* | |
1969 | * Skip registration of any hashing algorithms if MD block | |
1970 | * is not present. | |
1971 | */ | |
1b46c90c | 1972 | if (!md_inst) |
0435d47e | 1973 | return 0; |
bf83490e VM |
1974 | |
1975 | /* Limit digest size based on LP256 */ | |
d239b10d | 1976 | if (md_vid == CHA_VER_VID_MD_LP256) |
bf83490e VM |
1977 | md_limit = SHA256_DIGEST_SIZE; |
1978 | ||
cfc6f11b | 1979 | INIT_LIST_HEAD(&hash_list); |
045e3678 YK |
1980 | |
1981 | /* register crypto algorithms the device supports */ | |
1982 | for (i = 0; i < ARRAY_SIZE(driver_hash); i++) { | |
045e3678 | 1983 | struct caam_hash_alg *t_alg; |
bf83490e VM |
1984 | struct caam_hash_template *alg = driver_hash + i; |
1985 | ||
1986 | /* If MD size is not supported by device, skip registration */ | |
12b8567f IP |
1987 | if (is_mdha(alg->alg_type) && |
1988 | alg->template_ahash.halg.digestsize > md_limit) | |
bf83490e | 1989 | continue; |
045e3678 | 1990 | |
b0e09bae | 1991 | /* register hmac version */ |
bf83490e | 1992 | t_alg = caam_hash_alloc(alg, true); |
b0e09bae YK |
1993 | if (IS_ERR(t_alg)) { |
1994 | err = PTR_ERR(t_alg); | |
0f103b37 IP |
1995 | pr_warn("%s alg allocation failed\n", |
1996 | alg->hmac_driver_name); | |
b0e09bae YK |
1997 | continue; |
1998 | } | |
1999 | ||
623814c0 | 2000 | err = crypto_engine_register_ahash(&t_alg->ahash_alg); |
b0e09bae | 2001 | if (err) { |
6ea30f0a | 2002 | pr_warn("%s alg registration failed: %d\n", |
623814c0 | 2003 | t_alg->ahash_alg.base.halg.base.cra_driver_name, |
6ea30f0a | 2004 | err); |
b0e09bae YK |
2005 | kfree(t_alg); |
2006 | } else | |
cfc6f11b | 2007 | list_add_tail(&t_alg->entry, &hash_list); |
b0e09bae | 2008 | |
12b8567f IP |
2009 | if ((alg->alg_type & OP_ALG_ALGSEL_MASK) == OP_ALG_ALGSEL_AES) |
2010 | continue; | |
2011 | ||
b0e09bae | 2012 | /* register unkeyed version */ |
bf83490e | 2013 | t_alg = caam_hash_alloc(alg, false); |
045e3678 YK |
2014 | if (IS_ERR(t_alg)) { |
2015 | err = PTR_ERR(t_alg); | |
bf83490e | 2016 | pr_warn("%s alg allocation failed\n", alg->driver_name); |
045e3678 YK |
2017 | continue; |
2018 | } | |
2019 | ||
623814c0 | 2020 | err = crypto_engine_register_ahash(&t_alg->ahash_alg); |
045e3678 | 2021 | if (err) { |
6ea30f0a | 2022 | pr_warn("%s alg registration failed: %d\n", |
623814c0 | 2023 | t_alg->ahash_alg.base.halg.base.cra_driver_name, |
6ea30f0a | 2024 | err); |
045e3678 YK |
2025 | kfree(t_alg); |
2026 | } else | |
cfc6f11b | 2027 | list_add_tail(&t_alg->entry, &hash_list); |
045e3678 YK |
2028 | } |
2029 | ||
2030 | return err; | |
2031 | } |