Commit | Line | Data |
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b8840098 SZ |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support Blackfin CRC HW acceleration. | |
5 | * | |
6 | * Copyright 2012 Analog Devices Inc. | |
7 | * | |
8 | * Licensed under the GPL-2. | |
9 | */ | |
10 | ||
11 | #include <linux/err.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/scatterlist.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/unaligned/access_ok.h> | |
25 | #include <linux/crypto.h> | |
26 | #include <linux/cryptohash.h> | |
27 | #include <crypto/scatterwalk.h> | |
28 | #include <crypto/algapi.h> | |
29 | #include <crypto/hash.h> | |
30 | #include <crypto/internal/hash.h> | |
31 | ||
32 | #include <asm/blackfin.h> | |
b8840098 SZ |
33 | #include <asm/dma.h> |
34 | #include <asm/portmux.h> | |
52e6e543 SZ |
35 | #include <asm/io.h> |
36 | ||
37 | #include "bfin_crc.h" | |
b8840098 SZ |
38 | |
39 | #define CRC_CCRYPTO_QUEUE_LENGTH 5 | |
40 | ||
41 | #define DRIVER_NAME "bfin-hmac-crc" | |
42 | #define CHKSUM_DIGEST_SIZE 4 | |
43 | #define CHKSUM_BLOCK_SIZE 1 | |
44 | ||
45 | #define CRC_MAX_DMA_DESC 100 | |
46 | ||
47 | #define CRC_CRYPTO_STATE_UPDATE 1 | |
48 | #define CRC_CRYPTO_STATE_FINALUPDATE 2 | |
49 | #define CRC_CRYPTO_STATE_FINISH 3 | |
50 | ||
51 | struct bfin_crypto_crc { | |
52 | struct list_head list; | |
53 | struct device *dev; | |
54 | spinlock_t lock; | |
55 | ||
56 | int irq; | |
57 | int dma_ch; | |
58 | u32 poly; | |
52e6e543 | 59 | struct crc_register *regs; |
b8840098 SZ |
60 | |
61 | struct ahash_request *req; /* current request in operation */ | |
62 | struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */ | |
63 | dma_addr_t sg_dma; /* phy addr of sg dma descriptors */ | |
64 | u8 *sg_mid_buf; | |
65 | ||
66 | struct tasklet_struct done_task; | |
67 | struct crypto_queue queue; /* waiting requests */ | |
68 | ||
69 | u8 busy:1; /* crc device in operation flag */ | |
70 | }; | |
71 | ||
72 | static struct bfin_crypto_crc_list { | |
73 | struct list_head dev_list; | |
74 | spinlock_t lock; | |
75 | } crc_list; | |
76 | ||
77 | struct bfin_crypto_crc_reqctx { | |
78 | struct bfin_crypto_crc *crc; | |
79 | ||
80 | unsigned int total; /* total request bytes */ | |
81 | size_t sg_buflen; /* bytes for this update */ | |
82 | unsigned int sg_nents; | |
83 | struct scatterlist *sg; /* sg list head for this update*/ | |
84 | struct scatterlist bufsl[2]; /* chained sg list */ | |
85 | ||
86 | size_t bufnext_len; | |
87 | size_t buflast_len; | |
88 | u8 bufnext[CHKSUM_DIGEST_SIZE]; /* extra bytes for next udpate */ | |
89 | u8 buflast[CHKSUM_DIGEST_SIZE]; /* extra bytes from last udpate */ | |
90 | ||
91 | u8 flag; | |
92 | }; | |
93 | ||
94 | struct bfin_crypto_crc_ctx { | |
95 | struct bfin_crypto_crc *crc; | |
96 | u32 key; | |
97 | }; | |
98 | ||
99 | ||
100 | /* | |
101 | * derive number of elements in scatterlist | |
102 | */ | |
103 | static int sg_count(struct scatterlist *sg_list) | |
104 | { | |
105 | struct scatterlist *sg = sg_list; | |
106 | int sg_nents = 1; | |
107 | ||
108 | if (sg_list == NULL) | |
109 | return 0; | |
110 | ||
111 | while (!sg_is_last(sg)) { | |
112 | sg_nents++; | |
113 | sg = scatterwalk_sg_next(sg); | |
114 | } | |
115 | ||
116 | return sg_nents; | |
117 | } | |
118 | ||
119 | /* | |
120 | * get element in scatter list by given index | |
121 | */ | |
122 | static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nents, | |
123 | unsigned int index) | |
124 | { | |
125 | struct scatterlist *sg = NULL; | |
126 | int i; | |
127 | ||
128 | for_each_sg(sg_list, sg, nents, i) | |
129 | if (i == index) | |
130 | break; | |
131 | ||
132 | return sg; | |
133 | } | |
134 | ||
135 | static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key) | |
136 | { | |
52e6e543 SZ |
137 | writel(0, &crc->regs->datacntrld); |
138 | writel(MODE_CALC_CRC << OPMODE_OFFSET, &crc->regs->control); | |
139 | writel(key, &crc->regs->curresult); | |
b8840098 SZ |
140 | |
141 | /* setup CRC interrupts */ | |
52e6e543 SZ |
142 | writel(CMPERRI | DCNTEXPI, &crc->regs->status); |
143 | writel(CMPERRI | DCNTEXPI, &crc->regs->intrenset); | |
b8840098 SZ |
144 | |
145 | return 0; | |
146 | } | |
147 | ||
148 | static int bfin_crypto_crc_init(struct ahash_request *req) | |
149 | { | |
150 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
151 | struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm); | |
152 | struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req); | |
153 | struct bfin_crypto_crc *crc; | |
154 | ||
fb1dd794 | 155 | dev_dbg(ctx->crc->dev, "crc_init\n"); |
b8840098 SZ |
156 | spin_lock_bh(&crc_list.lock); |
157 | list_for_each_entry(crc, &crc_list.dev_list, list) { | |
158 | crc_ctx->crc = crc; | |
159 | break; | |
160 | } | |
161 | spin_unlock_bh(&crc_list.lock); | |
162 | ||
163 | if (sg_count(req->src) > CRC_MAX_DMA_DESC) { | |
fb1dd794 | 164 | dev_dbg(ctx->crc->dev, "init: requested sg list is too big > %d\n", |
b8840098 SZ |
165 | CRC_MAX_DMA_DESC); |
166 | return -EINVAL; | |
167 | } | |
168 | ||
169 | ctx->crc = crc; | |
170 | ctx->bufnext_len = 0; | |
171 | ctx->buflast_len = 0; | |
172 | ctx->sg_buflen = 0; | |
173 | ctx->total = 0; | |
174 | ctx->flag = 0; | |
175 | ||
176 | /* init crc results */ | |
177 | put_unaligned_le32(crc_ctx->key, req->result); | |
178 | ||
fb1dd794 | 179 | dev_dbg(ctx->crc->dev, "init: digest size: %d\n", |
b8840098 SZ |
180 | crypto_ahash_digestsize(tfm)); |
181 | ||
182 | return bfin_crypto_crc_init_hw(crc, crc_ctx->key); | |
183 | } | |
184 | ||
185 | static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc) | |
186 | { | |
187 | struct scatterlist *sg; | |
188 | struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(crc->req); | |
189 | int i = 0, j = 0; | |
190 | unsigned long dma_config; | |
191 | unsigned int dma_count; | |
192 | unsigned int dma_addr; | |
193 | unsigned int mid_dma_count = 0; | |
194 | int dma_mod; | |
195 | ||
196 | dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE); | |
197 | ||
198 | for_each_sg(ctx->sg, sg, ctx->sg_nents, j) { | |
199 | dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32; | |
200 | dma_addr = sg_dma_address(sg); | |
201 | /* deduce extra bytes in last sg */ | |
202 | if (sg_is_last(sg)) | |
203 | dma_count = sg_dma_len(sg) - ctx->bufnext_len; | |
204 | else | |
205 | dma_count = sg_dma_len(sg); | |
206 | ||
207 | if (mid_dma_count) { | |
208 | /* Append last middle dma buffer to 4 bytes with first | |
209 | bytes in current sg buffer. Move addr of current | |
210 | sg and deduce the length of current sg. | |
211 | */ | |
212 | memcpy(crc->sg_mid_buf +((i-1) << 2) + mid_dma_count, | |
213 | (void *)dma_addr, | |
214 | CHKSUM_DIGEST_SIZE - mid_dma_count); | |
215 | dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count; | |
216 | dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count; | |
217 | } | |
218 | /* chop current sg dma len to multiple of 32 bits */ | |
219 | mid_dma_count = dma_count % 4; | |
220 | dma_count &= ~0x3; | |
221 | ||
222 | if (dma_addr % 4 == 0) { | |
223 | dma_config |= WDSIZE_32; | |
224 | dma_count >>= 2; | |
225 | dma_mod = 4; | |
226 | } else if (dma_addr % 2 == 0) { | |
227 | dma_config |= WDSIZE_16; | |
228 | dma_count >>= 1; | |
229 | dma_mod = 2; | |
230 | } else { | |
231 | dma_config |= WDSIZE_8; | |
232 | dma_mod = 1; | |
233 | } | |
234 | ||
235 | crc->sg_cpu[i].start_addr = dma_addr; | |
236 | crc->sg_cpu[i].cfg = dma_config; | |
237 | crc->sg_cpu[i].x_count = dma_count; | |
238 | crc->sg_cpu[i].x_modify = dma_mod; | |
239 | dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, " | |
240 | "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n", | |
241 | i, crc->sg_cpu[i].start_addr, | |
242 | crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count, | |
243 | crc->sg_cpu[i].x_modify); | |
244 | i++; | |
245 | ||
246 | if (mid_dma_count) { | |
247 | /* copy extra bytes to next middle dma buffer */ | |
248 | dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | | |
249 | DMAEN | PSIZE_32 | WDSIZE_32; | |
250 | memcpy(crc->sg_mid_buf + (i << 2), | |
251 | (void *)(dma_addr + (dma_count << 2)), | |
252 | mid_dma_count); | |
253 | /* setup new dma descriptor for next middle dma */ | |
254 | crc->sg_cpu[i].start_addr = dma_map_single(crc->dev, | |
255 | crc->sg_mid_buf + (i << 2), | |
256 | CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE); | |
257 | crc->sg_cpu[i].cfg = dma_config; | |
258 | crc->sg_cpu[i].x_count = 1; | |
259 | crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE; | |
260 | dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, " | |
261 | "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n", | |
262 | i, crc->sg_cpu[i].start_addr, | |
263 | crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count, | |
264 | crc->sg_cpu[i].x_modify); | |
265 | i++; | |
266 | } | |
267 | } | |
268 | ||
269 | dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32 | WDSIZE_32; | |
270 | /* For final update req, append the buffer for next update as well*/ | |
271 | if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE || | |
272 | ctx->flag == CRC_CRYPTO_STATE_FINISH)) { | |
273 | crc->sg_cpu[i].start_addr = dma_map_single(crc->dev, ctx->bufnext, | |
274 | CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE); | |
275 | crc->sg_cpu[i].cfg = dma_config; | |
276 | crc->sg_cpu[i].x_count = 1; | |
277 | crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE; | |
278 | dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, " | |
279 | "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n", | |
280 | i, crc->sg_cpu[i].start_addr, | |
281 | crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count, | |
282 | crc->sg_cpu[i].x_modify); | |
283 | i++; | |
284 | } | |
285 | ||
286 | if (i == 0) | |
287 | return; | |
288 | ||
b8840098 SZ |
289 | /* Set the last descriptor to stop mode */ |
290 | crc->sg_cpu[i - 1].cfg &= ~(DMAFLOW | NDSIZE); | |
291 | crc->sg_cpu[i - 1].cfg |= DI_EN; | |
292 | set_dma_curr_desc_addr(crc->dma_ch, (unsigned long *)crc->sg_dma); | |
293 | set_dma_x_count(crc->dma_ch, 0); | |
294 | set_dma_x_modify(crc->dma_ch, 0); | |
b8840098 SZ |
295 | set_dma_config(crc->dma_ch, dma_config); |
296 | } | |
297 | ||
298 | static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc, | |
299 | struct ahash_request *req) | |
300 | { | |
301 | struct crypto_async_request *async_req, *backlog; | |
302 | struct bfin_crypto_crc_reqctx *ctx; | |
303 | struct scatterlist *sg; | |
304 | int ret = 0; | |
305 | int nsg, i, j; | |
306 | unsigned int nextlen; | |
307 | unsigned long flags; | |
52e6e543 | 308 | u32 reg; |
b8840098 SZ |
309 | |
310 | spin_lock_irqsave(&crc->lock, flags); | |
311 | if (req) | |
312 | ret = ahash_enqueue_request(&crc->queue, req); | |
313 | if (crc->busy) { | |
314 | spin_unlock_irqrestore(&crc->lock, flags); | |
315 | return ret; | |
316 | } | |
317 | backlog = crypto_get_backlog(&crc->queue); | |
318 | async_req = crypto_dequeue_request(&crc->queue); | |
319 | if (async_req) | |
320 | crc->busy = 1; | |
321 | spin_unlock_irqrestore(&crc->lock, flags); | |
322 | ||
323 | if (!async_req) | |
324 | return ret; | |
325 | ||
326 | if (backlog) | |
327 | backlog->complete(backlog, -EINPROGRESS); | |
328 | ||
329 | req = ahash_request_cast(async_req); | |
330 | crc->req = req; | |
331 | ctx = ahash_request_ctx(req); | |
332 | ctx->sg = NULL; | |
333 | ctx->sg_buflen = 0; | |
334 | ctx->sg_nents = 0; | |
335 | ||
336 | dev_dbg(crc->dev, "handling new req, flag=%u, nbytes: %d\n", | |
337 | ctx->flag, req->nbytes); | |
338 | ||
339 | if (ctx->flag == CRC_CRYPTO_STATE_FINISH) { | |
340 | if (ctx->bufnext_len == 0) { | |
341 | crc->busy = 0; | |
342 | return 0; | |
343 | } | |
344 | ||
345 | /* Pack last crc update buffer to 32bit */ | |
346 | memset(ctx->bufnext + ctx->bufnext_len, 0, | |
347 | CHKSUM_DIGEST_SIZE - ctx->bufnext_len); | |
348 | } else { | |
349 | /* Pack small data which is less than 32bit to buffer for next update. */ | |
350 | if (ctx->bufnext_len + req->nbytes < CHKSUM_DIGEST_SIZE) { | |
351 | memcpy(ctx->bufnext + ctx->bufnext_len, | |
352 | sg_virt(req->src), req->nbytes); | |
353 | ctx->bufnext_len += req->nbytes; | |
354 | if (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE && | |
355 | ctx->bufnext_len) { | |
356 | goto finish_update; | |
357 | } else { | |
358 | crc->busy = 0; | |
359 | return 0; | |
360 | } | |
361 | } | |
362 | ||
363 | if (ctx->bufnext_len) { | |
364 | /* Chain in extra bytes of last update */ | |
365 | ctx->buflast_len = ctx->bufnext_len; | |
366 | memcpy(ctx->buflast, ctx->bufnext, ctx->buflast_len); | |
367 | ||
368 | nsg = ctx->sg_buflen ? 2 : 1; | |
369 | sg_init_table(ctx->bufsl, nsg); | |
370 | sg_set_buf(ctx->bufsl, ctx->buflast, ctx->buflast_len); | |
371 | if (nsg > 1) | |
372 | scatterwalk_sg_chain(ctx->bufsl, nsg, | |
373 | req->src); | |
374 | ctx->sg = ctx->bufsl; | |
375 | } else | |
376 | ctx->sg = req->src; | |
377 | ||
378 | /* Chop crc buffer size to multiple of 32 bit */ | |
379 | nsg = ctx->sg_nents = sg_count(ctx->sg); | |
380 | ctx->sg_buflen = ctx->buflast_len + req->nbytes; | |
381 | ctx->bufnext_len = ctx->sg_buflen % 4; | |
382 | ctx->sg_buflen &= ~0x3; | |
383 | ||
384 | if (ctx->bufnext_len) { | |
385 | /* copy extra bytes to buffer for next update */ | |
386 | memset(ctx->bufnext, 0, CHKSUM_DIGEST_SIZE); | |
387 | nextlen = ctx->bufnext_len; | |
388 | for (i = nsg - 1; i >= 0; i--) { | |
389 | sg = sg_get(ctx->sg, nsg, i); | |
390 | j = min(nextlen, sg_dma_len(sg)); | |
391 | memcpy(ctx->bufnext + nextlen - j, | |
392 | sg_virt(sg) + sg_dma_len(sg) - j, j); | |
393 | if (j == sg_dma_len(sg)) | |
394 | ctx->sg_nents--; | |
395 | nextlen -= j; | |
396 | if (nextlen == 0) | |
397 | break; | |
398 | } | |
399 | } | |
400 | } | |
401 | ||
402 | finish_update: | |
403 | if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE || | |
404 | ctx->flag == CRC_CRYPTO_STATE_FINISH)) | |
405 | ctx->sg_buflen += CHKSUM_DIGEST_SIZE; | |
406 | ||
407 | /* set CRC data count before start DMA */ | |
52e6e543 | 408 | writel(ctx->sg_buflen >> 2, &crc->regs->datacnt); |
b8840098 SZ |
409 | |
410 | /* setup and enable CRC DMA */ | |
411 | bfin_crypto_crc_config_dma(crc); | |
412 | ||
413 | /* finally kick off CRC operation */ | |
52e6e543 SZ |
414 | reg = readl(&crc->regs->control); |
415 | writel(reg | BLKEN, &crc->regs->control); | |
b8840098 SZ |
416 | |
417 | return -EINPROGRESS; | |
418 | } | |
419 | ||
420 | static int bfin_crypto_crc_update(struct ahash_request *req) | |
421 | { | |
422 | struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req); | |
423 | ||
424 | if (!req->nbytes) | |
425 | return 0; | |
426 | ||
427 | dev_dbg(ctx->crc->dev, "crc_update\n"); | |
428 | ctx->total += req->nbytes; | |
429 | ctx->flag = CRC_CRYPTO_STATE_UPDATE; | |
430 | ||
431 | return bfin_crypto_crc_handle_queue(ctx->crc, req); | |
432 | } | |
433 | ||
434 | static int bfin_crypto_crc_final(struct ahash_request *req) | |
435 | { | |
436 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
437 | struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm); | |
438 | struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req); | |
439 | ||
440 | dev_dbg(ctx->crc->dev, "crc_final\n"); | |
441 | ctx->flag = CRC_CRYPTO_STATE_FINISH; | |
442 | crc_ctx->key = 0; | |
443 | ||
444 | return bfin_crypto_crc_handle_queue(ctx->crc, req); | |
445 | } | |
446 | ||
447 | static int bfin_crypto_crc_finup(struct ahash_request *req) | |
448 | { | |
449 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
450 | struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm); | |
451 | struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req); | |
452 | ||
453 | dev_dbg(ctx->crc->dev, "crc_finishupdate\n"); | |
454 | ctx->total += req->nbytes; | |
455 | ctx->flag = CRC_CRYPTO_STATE_FINALUPDATE; | |
456 | crc_ctx->key = 0; | |
457 | ||
458 | return bfin_crypto_crc_handle_queue(ctx->crc, req); | |
459 | } | |
460 | ||
461 | static int bfin_crypto_crc_digest(struct ahash_request *req) | |
462 | { | |
463 | int ret; | |
464 | ||
465 | ret = bfin_crypto_crc_init(req); | |
466 | if (ret) | |
467 | return ret; | |
468 | ||
469 | return bfin_crypto_crc_finup(req); | |
470 | } | |
471 | ||
472 | static int bfin_crypto_crc_setkey(struct crypto_ahash *tfm, const u8 *key, | |
473 | unsigned int keylen) | |
474 | { | |
475 | struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm); | |
476 | ||
477 | dev_dbg(crc_ctx->crc->dev, "crc_setkey\n"); | |
478 | if (keylen != CHKSUM_DIGEST_SIZE) { | |
479 | crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | crc_ctx->key = get_unaligned_le32(key); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int bfin_crypto_crc_cra_init(struct crypto_tfm *tfm) | |
489 | { | |
490 | struct bfin_crypto_crc_ctx *crc_ctx = crypto_tfm_ctx(tfm); | |
491 | ||
492 | crc_ctx->key = 0; | |
493 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
494 | sizeof(struct bfin_crypto_crc_reqctx)); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static void bfin_crypto_crc_cra_exit(struct crypto_tfm *tfm) | |
500 | { | |
501 | } | |
502 | ||
503 | static struct ahash_alg algs = { | |
504 | .init = bfin_crypto_crc_init, | |
505 | .update = bfin_crypto_crc_update, | |
506 | .final = bfin_crypto_crc_final, | |
507 | .finup = bfin_crypto_crc_finup, | |
508 | .digest = bfin_crypto_crc_digest, | |
509 | .setkey = bfin_crypto_crc_setkey, | |
510 | .halg.digestsize = CHKSUM_DIGEST_SIZE, | |
511 | .halg.base = { | |
512 | .cra_name = "hmac(crc32)", | |
513 | .cra_driver_name = DRIVER_NAME, | |
514 | .cra_priority = 100, | |
515 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
516 | CRYPTO_ALG_ASYNC, | |
517 | .cra_blocksize = CHKSUM_BLOCK_SIZE, | |
518 | .cra_ctxsize = sizeof(struct bfin_crypto_crc_ctx), | |
519 | .cra_alignmask = 3, | |
520 | .cra_module = THIS_MODULE, | |
521 | .cra_init = bfin_crypto_crc_cra_init, | |
522 | .cra_exit = bfin_crypto_crc_cra_exit, | |
523 | } | |
524 | }; | |
525 | ||
526 | static void bfin_crypto_crc_done_task(unsigned long data) | |
527 | { | |
528 | struct bfin_crypto_crc *crc = (struct bfin_crypto_crc *)data; | |
529 | ||
530 | bfin_crypto_crc_handle_queue(crc, NULL); | |
531 | } | |
532 | ||
533 | static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id) | |
534 | { | |
535 | struct bfin_crypto_crc *crc = dev_id; | |
52e6e543 | 536 | u32 reg; |
b8840098 | 537 | |
52e6e543 SZ |
538 | if (readl(&crc->regs->status) & DCNTEXP) { |
539 | writel(DCNTEXP, &crc->regs->status); | |
b8840098 SZ |
540 | |
541 | /* prepare results */ | |
52e6e543 SZ |
542 | put_unaligned_le32(readl(&crc->regs->result), |
543 | crc->req->result); | |
b8840098 | 544 | |
52e6e543 SZ |
545 | reg = readl(&crc->regs->control); |
546 | writel(reg & ~BLKEN, &crc->regs->control); | |
b8840098 SZ |
547 | crc->busy = 0; |
548 | ||
549 | if (crc->req->base.complete) | |
550 | crc->req->base.complete(&crc->req->base, 0); | |
551 | ||
552 | tasklet_schedule(&crc->done_task); | |
553 | ||
554 | return IRQ_HANDLED; | |
555 | } else | |
556 | return IRQ_NONE; | |
557 | } | |
558 | ||
559 | #ifdef CONFIG_PM | |
560 | /** | |
561 | * bfin_crypto_crc_suspend - suspend crc device | |
562 | * @pdev: device being suspended | |
563 | * @state: requested suspend state | |
564 | */ | |
565 | static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t state) | |
566 | { | |
567 | struct bfin_crypto_crc *crc = platform_get_drvdata(pdev); | |
568 | int i = 100000; | |
569 | ||
52e6e543 | 570 | while ((readl(&crc->regs->control) & BLKEN) && --i) |
b8840098 SZ |
571 | cpu_relax(); |
572 | ||
573 | if (i == 0) | |
574 | return -EBUSY; | |
575 | ||
576 | return 0; | |
577 | } | |
578 | #else | |
579 | # define bfin_crypto_crc_suspend NULL | |
580 | #endif | |
581 | ||
582 | #define bfin_crypto_crc_resume NULL | |
583 | ||
584 | /** | |
585 | * bfin_crypto_crc_probe - Initialize module | |
586 | * | |
587 | */ | |
49cfe4db | 588 | static int bfin_crypto_crc_probe(struct platform_device *pdev) |
b8840098 SZ |
589 | { |
590 | struct device *dev = &pdev->dev; | |
591 | struct resource *res; | |
592 | struct bfin_crypto_crc *crc; | |
593 | unsigned int timeout = 100000; | |
594 | int ret; | |
595 | ||
4ea5d999 | 596 | crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); |
b8840098 SZ |
597 | if (!crc) { |
598 | dev_err(&pdev->dev, "fail to malloc bfin_crypto_crc\n"); | |
599 | return -ENOMEM; | |
600 | } | |
601 | ||
602 | crc->dev = dev; | |
603 | ||
604 | INIT_LIST_HEAD(&crc->list); | |
605 | spin_lock_init(&crc->lock); | |
606 | tasklet_init(&crc->done_task, bfin_crypto_crc_done_task, (unsigned long)crc); | |
607 | crypto_init_queue(&crc->queue, CRC_CCRYPTO_QUEUE_LENGTH); | |
608 | ||
609 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
610 | if (res == NULL) { | |
611 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
4ea5d999 | 612 | return -ENOENT; |
b8840098 SZ |
613 | } |
614 | ||
4ea5d999 SZ |
615 | crc->regs = devm_ioremap_resource(dev, res); |
616 | if (IS_ERR((void *)crc->regs)) { | |
b8840098 | 617 | dev_err(&pdev->dev, "Cannot map CRC IO\n"); |
4ea5d999 | 618 | return PTR_ERR((void *)crc->regs); |
b8840098 SZ |
619 | } |
620 | ||
621 | crc->irq = platform_get_irq(pdev, 0); | |
622 | if (crc->irq < 0) { | |
623 | dev_err(&pdev->dev, "No CRC DCNTEXP IRQ specified\n"); | |
4ea5d999 | 624 | return -ENOENT; |
b8840098 SZ |
625 | } |
626 | ||
4ea5d999 SZ |
627 | ret = devm_request_irq(dev, crc->irq, bfin_crypto_crc_handler, |
628 | IRQF_SHARED, dev_name(dev), crc); | |
b8840098 SZ |
629 | if (ret) { |
630 | dev_err(&pdev->dev, "Unable to request blackfin crc irq\n"); | |
4ea5d999 | 631 | return ret; |
b8840098 SZ |
632 | } |
633 | ||
634 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
635 | if (res == NULL) { | |
636 | dev_err(&pdev->dev, "No CRC DMA channel specified\n"); | |
4ea5d999 | 637 | return -ENOENT; |
b8840098 SZ |
638 | } |
639 | crc->dma_ch = res->start; | |
640 | ||
641 | ret = request_dma(crc->dma_ch, dev_name(dev)); | |
642 | if (ret) { | |
643 | dev_err(&pdev->dev, "Unable to attach Blackfin CRC DMA channel\n"); | |
4ea5d999 | 644 | return ret; |
b8840098 SZ |
645 | } |
646 | ||
647 | crc->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &crc->sg_dma, GFP_KERNEL); | |
648 | if (crc->sg_cpu == NULL) { | |
649 | ret = -ENOMEM; | |
650 | goto out_error_dma; | |
651 | } | |
652 | /* | |
653 | * need at most CRC_MAX_DMA_DESC sg + CRC_MAX_DMA_DESC middle + | |
654 | * 1 last + 1 next dma descriptors | |
655 | */ | |
656 | crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1)); | |
657 | ||
52e6e543 SZ |
658 | writel(0, &crc->regs->control); |
659 | crc->poly = (u32)pdev->dev.platform_data; | |
660 | writel(crc->poly, &crc->regs->poly); | |
b8840098 | 661 | |
52e6e543 | 662 | while (!(readl(&crc->regs->status) & LUTDONE) && (--timeout) > 0) |
b8840098 SZ |
663 | cpu_relax(); |
664 | ||
665 | if (timeout == 0) | |
666 | dev_info(&pdev->dev, "init crc poly timeout\n"); | |
667 | ||
8d390395 SZ |
668 | platform_set_drvdata(pdev, crc); |
669 | ||
b8840098 SZ |
670 | spin_lock(&crc_list.lock); |
671 | list_add(&crc->list, &crc_list.dev_list); | |
672 | spin_unlock(&crc_list.lock); | |
673 | ||
8d390395 SZ |
674 | if (list_is_singular(&crc_list.dev_list)) { |
675 | ret = crypto_register_ahash(&algs); | |
676 | if (ret) { | |
677 | dev_err(&pdev->dev, | |
678 | "Can't register crypto ahash device\n"); | |
679 | goto out_error_dma; | |
680 | } | |
b8840098 SZ |
681 | } |
682 | ||
683 | dev_info(&pdev->dev, "initialized\n"); | |
684 | ||
685 | return 0; | |
686 | ||
687 | out_error_dma: | |
688 | if (crc->sg_cpu) | |
689 | dma_free_coherent(&pdev->dev, PAGE_SIZE, crc->sg_cpu, crc->sg_dma); | |
690 | free_dma(crc->dma_ch); | |
b8840098 SZ |
691 | |
692 | return ret; | |
693 | } | |
694 | ||
695 | /** | |
696 | * bfin_crypto_crc_remove - Initialize module | |
697 | * | |
698 | */ | |
49cfe4db | 699 | static int bfin_crypto_crc_remove(struct platform_device *pdev) |
b8840098 SZ |
700 | { |
701 | struct bfin_crypto_crc *crc = platform_get_drvdata(pdev); | |
702 | ||
703 | if (!crc) | |
704 | return -ENODEV; | |
705 | ||
706 | spin_lock(&crc_list.lock); | |
707 | list_del(&crc->list); | |
708 | spin_unlock(&crc_list.lock); | |
709 | ||
710 | crypto_unregister_ahash(&algs); | |
711 | tasklet_kill(&crc->done_task); | |
b8840098 | 712 | free_dma(crc->dma_ch); |
b8840098 SZ |
713 | |
714 | return 0; | |
715 | } | |
716 | ||
717 | static struct platform_driver bfin_crypto_crc_driver = { | |
718 | .probe = bfin_crypto_crc_probe, | |
49cfe4db | 719 | .remove = bfin_crypto_crc_remove, |
b8840098 SZ |
720 | .suspend = bfin_crypto_crc_suspend, |
721 | .resume = bfin_crypto_crc_resume, | |
722 | .driver = { | |
723 | .name = DRIVER_NAME, | |
724 | .owner = THIS_MODULE, | |
725 | }, | |
726 | }; | |
727 | ||
728 | /** | |
729 | * bfin_crypto_crc_mod_init - Initialize module | |
730 | * | |
731 | * Checks the module params and registers the platform driver. | |
732 | * Real work is in the platform probe function. | |
733 | */ | |
734 | static int __init bfin_crypto_crc_mod_init(void) | |
735 | { | |
736 | int ret; | |
737 | ||
738 | pr_info("Blackfin hardware CRC crypto driver\n"); | |
739 | ||
740 | INIT_LIST_HEAD(&crc_list.dev_list); | |
741 | spin_lock_init(&crc_list.lock); | |
742 | ||
743 | ret = platform_driver_register(&bfin_crypto_crc_driver); | |
744 | if (ret) { | |
745 | pr_info(KERN_ERR "unable to register driver\n"); | |
746 | return ret; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | /** | |
753 | * bfin_crypto_crc_mod_exit - Deinitialize module | |
754 | */ | |
755 | static void __exit bfin_crypto_crc_mod_exit(void) | |
756 | { | |
757 | platform_driver_unregister(&bfin_crypto_crc_driver); | |
758 | } | |
759 | ||
760 | module_init(bfin_crypto_crc_mod_init); | |
761 | module_exit(bfin_crypto_crc_mod_exit); | |
762 | ||
763 | MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); | |
764 | MODULE_DESCRIPTION("Blackfin CRC hardware crypto driver"); | |
765 | MODULE_LICENSE("GPL"); |