Commit | Line | Data |
---|---|---|
ebc82efa NR |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for ATMEL SHA1/SHA256 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2012 Eukréa Electromatique - ATMEL | |
7 | * Author: Nicolas Royer <nicolas@eukrea.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | * | |
13 | * Some ideas are from omap-sham.c drivers. | |
14 | */ | |
15 | ||
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/hw_random.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include <linux/device.h> | |
ebc82efa NR |
27 | #include <linux/init.h> |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
ebc82efa | 30 | #include <linux/irq.h> |
ebc82efa NR |
31 | #include <linux/scatterlist.h> |
32 | #include <linux/dma-mapping.h> | |
abfe7ae4 | 33 | #include <linux/of_device.h> |
ebc82efa NR |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
36 | #include <linux/cryptohash.h> | |
37 | #include <crypto/scatterwalk.h> | |
38 | #include <crypto/algapi.h> | |
39 | #include <crypto/sha.h> | |
40 | #include <crypto/hash.h> | |
41 | #include <crypto/internal/hash.h> | |
d4905b38 | 42 | #include <linux/platform_data/crypto-atmel.h> |
ebc82efa NR |
43 | #include "atmel-sha-regs.h" |
44 | ||
45 | /* SHA flags */ | |
46 | #define SHA_FLAGS_BUSY BIT(0) | |
47 | #define SHA_FLAGS_FINAL BIT(1) | |
48 | #define SHA_FLAGS_DMA_ACTIVE BIT(2) | |
49 | #define SHA_FLAGS_OUTPUT_READY BIT(3) | |
50 | #define SHA_FLAGS_INIT BIT(4) | |
51 | #define SHA_FLAGS_CPU BIT(5) | |
52 | #define SHA_FLAGS_DMA_READY BIT(6) | |
53 | ||
54 | #define SHA_FLAGS_FINUP BIT(16) | |
55 | #define SHA_FLAGS_SG BIT(17) | |
56 | #define SHA_FLAGS_SHA1 BIT(18) | |
d4905b38 NR |
57 | #define SHA_FLAGS_SHA224 BIT(19) |
58 | #define SHA_FLAGS_SHA256 BIT(20) | |
59 | #define SHA_FLAGS_SHA384 BIT(21) | |
60 | #define SHA_FLAGS_SHA512 BIT(22) | |
61 | #define SHA_FLAGS_ERROR BIT(23) | |
62 | #define SHA_FLAGS_PAD BIT(24) | |
ebc82efa NR |
63 | |
64 | #define SHA_OP_UPDATE 1 | |
65 | #define SHA_OP_FINAL 2 | |
66 | ||
67 | #define SHA_BUFFER_LEN PAGE_SIZE | |
68 | ||
69 | #define ATMEL_SHA_DMA_THRESHOLD 56 | |
70 | ||
d4905b38 NR |
71 | struct atmel_sha_caps { |
72 | bool has_dma; | |
73 | bool has_dualbuff; | |
74 | bool has_sha224; | |
75 | bool has_sha_384_512; | |
76 | }; | |
ebc82efa NR |
77 | |
78 | struct atmel_sha_dev; | |
79 | ||
80 | struct atmel_sha_reqctx { | |
81 | struct atmel_sha_dev *dd; | |
82 | unsigned long flags; | |
83 | unsigned long op; | |
84 | ||
d4905b38 NR |
85 | u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32)); |
86 | u64 digcnt[2]; | |
ebc82efa NR |
87 | size_t bufcnt; |
88 | size_t buflen; | |
89 | dma_addr_t dma_addr; | |
90 | ||
91 | /* walk state */ | |
92 | struct scatterlist *sg; | |
93 | unsigned int offset; /* offset in current sg */ | |
94 | unsigned int total; /* total request */ | |
95 | ||
d4905b38 NR |
96 | size_t block_size; |
97 | ||
ebc82efa NR |
98 | u8 buffer[0] __aligned(sizeof(u32)); |
99 | }; | |
100 | ||
101 | struct atmel_sha_ctx { | |
102 | struct atmel_sha_dev *dd; | |
103 | ||
104 | unsigned long flags; | |
ebc82efa NR |
105 | }; |
106 | ||
d4905b38 NR |
107 | #define ATMEL_SHA_QUEUE_LENGTH 50 |
108 | ||
109 | struct atmel_sha_dma { | |
110 | struct dma_chan *chan; | |
111 | struct dma_slave_config dma_conf; | |
112 | }; | |
ebc82efa NR |
113 | |
114 | struct atmel_sha_dev { | |
115 | struct list_head list; | |
116 | unsigned long phys_base; | |
117 | struct device *dev; | |
118 | struct clk *iclk; | |
119 | int irq; | |
120 | void __iomem *io_base; | |
121 | ||
122 | spinlock_t lock; | |
123 | int err; | |
124 | struct tasklet_struct done_task; | |
f56809c3 | 125 | struct tasklet_struct queue_task; |
ebc82efa NR |
126 | |
127 | unsigned long flags; | |
128 | struct crypto_queue queue; | |
129 | struct ahash_request *req; | |
d4905b38 NR |
130 | |
131 | struct atmel_sha_dma dma_lch_in; | |
132 | ||
133 | struct atmel_sha_caps caps; | |
134 | ||
135 | u32 hw_version; | |
ebc82efa NR |
136 | }; |
137 | ||
138 | struct atmel_sha_drv { | |
139 | struct list_head dev_list; | |
140 | spinlock_t lock; | |
141 | }; | |
142 | ||
143 | static struct atmel_sha_drv atmel_sha = { | |
144 | .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list), | |
145 | .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock), | |
146 | }; | |
147 | ||
148 | static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset) | |
149 | { | |
150 | return readl_relaxed(dd->io_base + offset); | |
151 | } | |
152 | ||
153 | static inline void atmel_sha_write(struct atmel_sha_dev *dd, | |
154 | u32 offset, u32 value) | |
155 | { | |
156 | writel_relaxed(value, dd->io_base + offset); | |
157 | } | |
158 | ||
ebc82efa NR |
159 | static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx) |
160 | { | |
161 | size_t count; | |
162 | ||
163 | while ((ctx->bufcnt < ctx->buflen) && ctx->total) { | |
164 | count = min(ctx->sg->length - ctx->offset, ctx->total); | |
165 | count = min(count, ctx->buflen - ctx->bufcnt); | |
166 | ||
803eeae8 LZ |
167 | if (count <= 0) { |
168 | /* | |
169 | * Check if count <= 0 because the buffer is full or | |
170 | * because the sg length is 0. In the latest case, | |
171 | * check if there is another sg in the list, a 0 length | |
172 | * sg doesn't necessarily mean the end of the sg list. | |
173 | */ | |
174 | if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) { | |
175 | ctx->sg = sg_next(ctx->sg); | |
176 | continue; | |
177 | } else { | |
178 | break; | |
179 | } | |
180 | } | |
ebc82efa NR |
181 | |
182 | scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg, | |
183 | ctx->offset, count, 0); | |
184 | ||
185 | ctx->bufcnt += count; | |
186 | ctx->offset += count; | |
187 | ctx->total -= count; | |
188 | ||
189 | if (ctx->offset == ctx->sg->length) { | |
190 | ctx->sg = sg_next(ctx->sg); | |
191 | if (ctx->sg) | |
192 | ctx->offset = 0; | |
193 | else | |
194 | ctx->total = 0; | |
195 | } | |
196 | } | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | /* | |
d4905b38 NR |
202 | * The purpose of this padding is to ensure that the padded message is a |
203 | * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). | |
204 | * The bit "1" is appended at the end of the message followed by | |
205 | * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or | |
206 | * 128 bits block (SHA384/SHA512) equals to the message length in bits | |
207 | * is appended. | |
ebc82efa | 208 | * |
d4905b38 | 209 | * For SHA1/SHA224/SHA256, padlen is calculated as followed: |
ebc82efa NR |
210 | * - if message length < 56 bytes then padlen = 56 - message length |
211 | * - else padlen = 64 + 56 - message length | |
d4905b38 NR |
212 | * |
213 | * For SHA384/SHA512, padlen is calculated as followed: | |
214 | * - if message length < 112 bytes then padlen = 112 - message length | |
215 | * - else padlen = 128 + 112 - message length | |
ebc82efa NR |
216 | */ |
217 | static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length) | |
218 | { | |
219 | unsigned int index, padlen; | |
d4905b38 NR |
220 | u64 bits[2]; |
221 | u64 size[2]; | |
222 | ||
223 | size[0] = ctx->digcnt[0]; | |
224 | size[1] = ctx->digcnt[1]; | |
225 | ||
226 | size[0] += ctx->bufcnt; | |
227 | if (size[0] < ctx->bufcnt) | |
228 | size[1]++; | |
229 | ||
230 | size[0] += length; | |
231 | if (size[0] < length) | |
232 | size[1]++; | |
233 | ||
234 | bits[1] = cpu_to_be64(size[0] << 3); | |
235 | bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61); | |
236 | ||
237 | if (ctx->flags & (SHA_FLAGS_SHA384 | SHA_FLAGS_SHA512)) { | |
238 | index = ctx->bufcnt & 0x7f; | |
239 | padlen = (index < 112) ? (112 - index) : ((128+112) - index); | |
240 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
241 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
242 | memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16); | |
243 | ctx->bufcnt += padlen + 16; | |
244 | ctx->flags |= SHA_FLAGS_PAD; | |
245 | } else { | |
246 | index = ctx->bufcnt & 0x3f; | |
247 | padlen = (index < 56) ? (56 - index) : ((64+56) - index); | |
248 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
249 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
250 | memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8); | |
251 | ctx->bufcnt += padlen + 8; | |
252 | ctx->flags |= SHA_FLAGS_PAD; | |
253 | } | |
ebc82efa NR |
254 | } |
255 | ||
256 | static int atmel_sha_init(struct ahash_request *req) | |
257 | { | |
258 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
259 | struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm); | |
260 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
261 | struct atmel_sha_dev *dd = NULL; | |
262 | struct atmel_sha_dev *tmp; | |
263 | ||
264 | spin_lock_bh(&atmel_sha.lock); | |
265 | if (!tctx->dd) { | |
266 | list_for_each_entry(tmp, &atmel_sha.dev_list, list) { | |
267 | dd = tmp; | |
268 | break; | |
269 | } | |
270 | tctx->dd = dd; | |
271 | } else { | |
272 | dd = tctx->dd; | |
273 | } | |
274 | ||
275 | spin_unlock_bh(&atmel_sha.lock); | |
276 | ||
277 | ctx->dd = dd; | |
278 | ||
279 | ctx->flags = 0; | |
280 | ||
281 | dev_dbg(dd->dev, "init: digest size: %d\n", | |
282 | crypto_ahash_digestsize(tfm)); | |
283 | ||
d4905b38 NR |
284 | switch (crypto_ahash_digestsize(tfm)) { |
285 | case SHA1_DIGEST_SIZE: | |
ebc82efa | 286 | ctx->flags |= SHA_FLAGS_SHA1; |
d4905b38 NR |
287 | ctx->block_size = SHA1_BLOCK_SIZE; |
288 | break; | |
289 | case SHA224_DIGEST_SIZE: | |
290 | ctx->flags |= SHA_FLAGS_SHA224; | |
291 | ctx->block_size = SHA224_BLOCK_SIZE; | |
292 | break; | |
293 | case SHA256_DIGEST_SIZE: | |
ebc82efa | 294 | ctx->flags |= SHA_FLAGS_SHA256; |
d4905b38 NR |
295 | ctx->block_size = SHA256_BLOCK_SIZE; |
296 | break; | |
297 | case SHA384_DIGEST_SIZE: | |
298 | ctx->flags |= SHA_FLAGS_SHA384; | |
299 | ctx->block_size = SHA384_BLOCK_SIZE; | |
300 | break; | |
301 | case SHA512_DIGEST_SIZE: | |
302 | ctx->flags |= SHA_FLAGS_SHA512; | |
303 | ctx->block_size = SHA512_BLOCK_SIZE; | |
304 | break; | |
305 | default: | |
306 | return -EINVAL; | |
307 | break; | |
308 | } | |
ebc82efa NR |
309 | |
310 | ctx->bufcnt = 0; | |
d4905b38 NR |
311 | ctx->digcnt[0] = 0; |
312 | ctx->digcnt[1] = 0; | |
ebc82efa NR |
313 | ctx->buflen = SHA_BUFFER_LEN; |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma) | |
319 | { | |
320 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
321 | u32 valcr = 0, valmr = SHA_MR_MODE_AUTO; | |
322 | ||
323 | if (likely(dma)) { | |
d4905b38 NR |
324 | if (!dd->caps.has_dma) |
325 | atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE); | |
ebc82efa | 326 | valmr = SHA_MR_MODE_PDC; |
d4905b38 NR |
327 | if (dd->caps.has_dualbuff) |
328 | valmr |= SHA_MR_DUALBUFF; | |
ebc82efa NR |
329 | } else { |
330 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
331 | } | |
332 | ||
d4905b38 NR |
333 | if (ctx->flags & SHA_FLAGS_SHA1) |
334 | valmr |= SHA_MR_ALGO_SHA1; | |
335 | else if (ctx->flags & SHA_FLAGS_SHA224) | |
336 | valmr |= SHA_MR_ALGO_SHA224; | |
337 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa | 338 | valmr |= SHA_MR_ALGO_SHA256; |
d4905b38 NR |
339 | else if (ctx->flags & SHA_FLAGS_SHA384) |
340 | valmr |= SHA_MR_ALGO_SHA384; | |
341 | else if (ctx->flags & SHA_FLAGS_SHA512) | |
342 | valmr |= SHA_MR_ALGO_SHA512; | |
ebc82efa NR |
343 | |
344 | /* Setting CR_FIRST only for the first iteration */ | |
d4905b38 | 345 | if (!(ctx->digcnt[0] || ctx->digcnt[1])) |
ebc82efa NR |
346 | valcr = SHA_CR_FIRST; |
347 | ||
348 | atmel_sha_write(dd, SHA_CR, valcr); | |
349 | atmel_sha_write(dd, SHA_MR, valmr); | |
350 | } | |
351 | ||
352 | static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf, | |
353 | size_t length, int final) | |
354 | { | |
355 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
356 | int count, len32; | |
357 | const u32 *buffer = (const u32 *)buf; | |
358 | ||
d4905b38 NR |
359 | dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
360 | ctx->digcnt[1], ctx->digcnt[0], length, final); | |
ebc82efa NR |
361 | |
362 | atmel_sha_write_ctrl(dd, 0); | |
363 | ||
364 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
365 | ctx->digcnt[0] += length; |
366 | if (ctx->digcnt[0] < length) | |
367 | ctx->digcnt[1]++; | |
ebc82efa NR |
368 | |
369 | if (final) | |
370 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
371 | ||
372 | len32 = DIV_ROUND_UP(length, sizeof(u32)); | |
373 | ||
374 | dd->flags |= SHA_FLAGS_CPU; | |
375 | ||
376 | for (count = 0; count < len32; count++) | |
377 | atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]); | |
378 | ||
379 | return -EINPROGRESS; | |
380 | } | |
381 | ||
382 | static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
383 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
384 | { | |
385 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
386 | int len32; | |
387 | ||
d4905b38 NR |
388 | dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
389 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
ebc82efa NR |
390 | |
391 | len32 = DIV_ROUND_UP(length1, sizeof(u32)); | |
392 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS); | |
393 | atmel_sha_write(dd, SHA_TPR, dma_addr1); | |
394 | atmel_sha_write(dd, SHA_TCR, len32); | |
395 | ||
396 | len32 = DIV_ROUND_UP(length2, sizeof(u32)); | |
397 | atmel_sha_write(dd, SHA_TNPR, dma_addr2); | |
398 | atmel_sha_write(dd, SHA_TNCR, len32); | |
399 | ||
400 | atmel_sha_write_ctrl(dd, 1); | |
401 | ||
402 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
403 | ctx->digcnt[0] += length1; |
404 | if (ctx->digcnt[0] < length1) | |
405 | ctx->digcnt[1]++; | |
ebc82efa NR |
406 | |
407 | if (final) | |
408 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
409 | ||
410 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
411 | ||
412 | /* Start DMA transfer */ | |
413 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN); | |
414 | ||
415 | return -EINPROGRESS; | |
416 | } | |
417 | ||
d4905b38 NR |
418 | static void atmel_sha_dma_callback(void *data) |
419 | { | |
420 | struct atmel_sha_dev *dd = data; | |
421 | ||
422 | /* dma_lch_in - completed - wait DATRDY */ | |
423 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
424 | } | |
425 | ||
426 | static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
427 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
428 | { | |
429 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
430 | struct dma_async_tx_descriptor *in_desc; | |
431 | struct scatterlist sg[2]; | |
432 | ||
433 | dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", | |
434 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
435 | ||
3f1992c0 LZ |
436 | dd->dma_lch_in.dma_conf.src_maxburst = 16; |
437 | dd->dma_lch_in.dma_conf.dst_maxburst = 16; | |
d4905b38 NR |
438 | |
439 | dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); | |
440 | ||
441 | if (length2) { | |
442 | sg_init_table(sg, 2); | |
443 | sg_dma_address(&sg[0]) = dma_addr1; | |
444 | sg_dma_len(&sg[0]) = length1; | |
445 | sg_dma_address(&sg[1]) = dma_addr2; | |
446 | sg_dma_len(&sg[1]) = length2; | |
447 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2, | |
448 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
449 | } else { | |
450 | sg_init_table(sg, 1); | |
451 | sg_dma_address(&sg[0]) = dma_addr1; | |
452 | sg_dma_len(&sg[0]) = length1; | |
453 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1, | |
454 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
455 | } | |
456 | if (!in_desc) | |
457 | return -EINVAL; | |
458 | ||
459 | in_desc->callback = atmel_sha_dma_callback; | |
460 | in_desc->callback_param = dd; | |
461 | ||
462 | atmel_sha_write_ctrl(dd, 1); | |
463 | ||
464 | /* should be non-zero before next lines to disable clocks later */ | |
465 | ctx->digcnt[0] += length1; | |
466 | if (ctx->digcnt[0] < length1) | |
467 | ctx->digcnt[1]++; | |
468 | ||
469 | if (final) | |
470 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
471 | ||
472 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
473 | ||
474 | /* Start DMA transfer */ | |
475 | dmaengine_submit(in_desc); | |
476 | dma_async_issue_pending(dd->dma_lch_in.chan); | |
477 | ||
478 | return -EINPROGRESS; | |
479 | } | |
480 | ||
481 | static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
482 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
483 | { | |
484 | if (dd->caps.has_dma) | |
485 | return atmel_sha_xmit_dma(dd, dma_addr1, length1, | |
486 | dma_addr2, length2, final); | |
487 | else | |
488 | return atmel_sha_xmit_pdc(dd, dma_addr1, length1, | |
489 | dma_addr2, length2, final); | |
490 | } | |
491 | ||
ebc82efa NR |
492 | static int atmel_sha_update_cpu(struct atmel_sha_dev *dd) |
493 | { | |
494 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
495 | int bufcnt; | |
496 | ||
497 | atmel_sha_append_sg(ctx); | |
498 | atmel_sha_fill_padding(ctx, 0); | |
ebc82efa NR |
499 | bufcnt = ctx->bufcnt; |
500 | ctx->bufcnt = 0; | |
501 | ||
502 | return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1); | |
503 | } | |
504 | ||
505 | static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd, | |
506 | struct atmel_sha_reqctx *ctx, | |
507 | size_t length, int final) | |
508 | { | |
509 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 510 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
511 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
512 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen + | |
d4905b38 | 513 | ctx->block_size); |
ebc82efa NR |
514 | return -EINVAL; |
515 | } | |
516 | ||
517 | ctx->flags &= ~SHA_FLAGS_SG; | |
518 | ||
519 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 520 | return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final); |
ebc82efa NR |
521 | } |
522 | ||
523 | static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd) | |
524 | { | |
525 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
526 | unsigned int final; | |
527 | size_t count; | |
528 | ||
529 | atmel_sha_append_sg(ctx); | |
530 | ||
531 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
532 | ||
d4905b38 NR |
533 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n", |
534 | ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final); | |
ebc82efa NR |
535 | |
536 | if (final) | |
537 | atmel_sha_fill_padding(ctx, 0); | |
538 | ||
0099286b | 539 | if (final || (ctx->bufcnt == ctx->buflen)) { |
ebc82efa NR |
540 | count = ctx->bufcnt; |
541 | ctx->bufcnt = 0; | |
542 | return atmel_sha_xmit_dma_map(dd, ctx, count, final); | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd) | |
549 | { | |
550 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
551 | unsigned int length, final, tail; | |
552 | struct scatterlist *sg; | |
553 | unsigned int count; | |
554 | ||
555 | if (!ctx->total) | |
556 | return 0; | |
557 | ||
558 | if (ctx->bufcnt || ctx->offset) | |
559 | return atmel_sha_update_dma_slow(dd); | |
560 | ||
d4905b38 NR |
561 | dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n", |
562 | ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total); | |
ebc82efa NR |
563 | |
564 | sg = ctx->sg; | |
565 | ||
566 | if (!IS_ALIGNED(sg->offset, sizeof(u32))) | |
567 | return atmel_sha_update_dma_slow(dd); | |
568 | ||
d4905b38 NR |
569 | if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size)) |
570 | /* size is not ctx->block_size aligned */ | |
ebc82efa NR |
571 | return atmel_sha_update_dma_slow(dd); |
572 | ||
573 | length = min(ctx->total, sg->length); | |
574 | ||
575 | if (sg_is_last(sg)) { | |
576 | if (!(ctx->flags & SHA_FLAGS_FINUP)) { | |
d4905b38 NR |
577 | /* not last sg must be ctx->block_size aligned */ |
578 | tail = length & (ctx->block_size - 1); | |
ebc82efa | 579 | length -= tail; |
ebc82efa NR |
580 | } |
581 | } | |
582 | ||
583 | ctx->total -= length; | |
584 | ctx->offset = length; /* offset where to start slow */ | |
585 | ||
586 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
587 | ||
588 | /* Add padding */ | |
589 | if (final) { | |
d4905b38 | 590 | tail = length & (ctx->block_size - 1); |
ebc82efa NR |
591 | length -= tail; |
592 | ctx->total += tail; | |
593 | ctx->offset = length; /* offset where to start slow */ | |
594 | ||
595 | sg = ctx->sg; | |
596 | atmel_sha_append_sg(ctx); | |
597 | ||
598 | atmel_sha_fill_padding(ctx, length); | |
599 | ||
600 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 601 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
602 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
603 | dev_err(dd->dev, "dma %u bytes error\n", | |
d4905b38 | 604 | ctx->buflen + ctx->block_size); |
ebc82efa NR |
605 | return -EINVAL; |
606 | } | |
607 | ||
608 | if (length == 0) { | |
609 | ctx->flags &= ~SHA_FLAGS_SG; | |
610 | count = ctx->bufcnt; | |
611 | ctx->bufcnt = 0; | |
d4905b38 | 612 | return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0, |
ebc82efa NR |
613 | 0, final); |
614 | } else { | |
615 | ctx->sg = sg; | |
616 | if (!dma_map_sg(dd->dev, ctx->sg, 1, | |
617 | DMA_TO_DEVICE)) { | |
618 | dev_err(dd->dev, "dma_map_sg error\n"); | |
619 | return -EINVAL; | |
620 | } | |
621 | ||
622 | ctx->flags |= SHA_FLAGS_SG; | |
623 | ||
624 | count = ctx->bufcnt; | |
625 | ctx->bufcnt = 0; | |
d4905b38 | 626 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), |
ebc82efa NR |
627 | length, ctx->dma_addr, count, final); |
628 | } | |
629 | } | |
630 | ||
631 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
632 | dev_err(dd->dev, "dma_map_sg error\n"); | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
636 | ctx->flags |= SHA_FLAGS_SG; | |
637 | ||
638 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 639 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0, |
ebc82efa NR |
640 | 0, final); |
641 | } | |
642 | ||
643 | static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd) | |
644 | { | |
645 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
646 | ||
647 | if (ctx->flags & SHA_FLAGS_SG) { | |
648 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); | |
649 | if (ctx->sg->length == ctx->offset) { | |
650 | ctx->sg = sg_next(ctx->sg); | |
651 | if (ctx->sg) | |
652 | ctx->offset = 0; | |
653 | } | |
d4905b38 | 654 | if (ctx->flags & SHA_FLAGS_PAD) { |
ebc82efa | 655 | dma_unmap_single(dd->dev, ctx->dma_addr, |
d4905b38 NR |
656 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
657 | } | |
ebc82efa NR |
658 | } else { |
659 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen + | |
d4905b38 | 660 | ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
661 | } |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
666 | static int atmel_sha_update_req(struct atmel_sha_dev *dd) | |
667 | { | |
668 | struct ahash_request *req = dd->req; | |
669 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
670 | int err; | |
671 | ||
d4905b38 NR |
672 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n", |
673 | ctx->total, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
674 | |
675 | if (ctx->flags & SHA_FLAGS_CPU) | |
676 | err = atmel_sha_update_cpu(dd); | |
677 | else | |
678 | err = atmel_sha_update_dma_start(dd); | |
679 | ||
680 | /* wait for dma completion before can take more data */ | |
d4905b38 NR |
681 | dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n", |
682 | err, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
683 | |
684 | return err; | |
685 | } | |
686 | ||
687 | static int atmel_sha_final_req(struct atmel_sha_dev *dd) | |
688 | { | |
689 | struct ahash_request *req = dd->req; | |
690 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
691 | int err = 0; | |
692 | int count; | |
693 | ||
694 | if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) { | |
695 | atmel_sha_fill_padding(ctx, 0); | |
696 | count = ctx->bufcnt; | |
697 | ctx->bufcnt = 0; | |
698 | err = atmel_sha_xmit_dma_map(dd, ctx, count, 1); | |
699 | } | |
700 | /* faster to handle last block with cpu */ | |
701 | else { | |
702 | atmel_sha_fill_padding(ctx, 0); | |
703 | count = ctx->bufcnt; | |
704 | ctx->bufcnt = 0; | |
705 | err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1); | |
706 | } | |
707 | ||
708 | dev_dbg(dd->dev, "final_req: err: %d\n", err); | |
709 | ||
710 | return err; | |
711 | } | |
712 | ||
713 | static void atmel_sha_copy_hash(struct ahash_request *req) | |
714 | { | |
715 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
716 | u32 *hash = (u32 *)ctx->digest; | |
717 | int i; | |
718 | ||
d4905b38 | 719 | if (ctx->flags & SHA_FLAGS_SHA1) |
ebc82efa NR |
720 | for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) |
721 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
d4905b38 NR |
722 | else if (ctx->flags & SHA_FLAGS_SHA224) |
723 | for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++) | |
724 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
725 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa NR |
726 | for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++) |
727 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
d4905b38 NR |
728 | else if (ctx->flags & SHA_FLAGS_SHA384) |
729 | for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++) | |
730 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
731 | else | |
732 | for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++) | |
733 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
ebc82efa NR |
734 | } |
735 | ||
736 | static void atmel_sha_copy_ready_hash(struct ahash_request *req) | |
737 | { | |
738 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
739 | ||
740 | if (!req->result) | |
741 | return; | |
742 | ||
d4905b38 | 743 | if (ctx->flags & SHA_FLAGS_SHA1) |
ebc82efa | 744 | memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE); |
d4905b38 NR |
745 | else if (ctx->flags & SHA_FLAGS_SHA224) |
746 | memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE); | |
747 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa | 748 | memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE); |
d4905b38 NR |
749 | else if (ctx->flags & SHA_FLAGS_SHA384) |
750 | memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE); | |
751 | else | |
752 | memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE); | |
ebc82efa NR |
753 | } |
754 | ||
755 | static int atmel_sha_finish(struct ahash_request *req) | |
756 | { | |
757 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
758 | struct atmel_sha_dev *dd = ctx->dd; | |
ebc82efa | 759 | |
d4905b38 | 760 | if (ctx->digcnt[0] || ctx->digcnt[1]) |
ebc82efa NR |
761 | atmel_sha_copy_ready_hash(req); |
762 | ||
d4905b38 NR |
763 | dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1], |
764 | ctx->digcnt[0], ctx->bufcnt); | |
ebc82efa | 765 | |
871b88a8 | 766 | return 0; |
ebc82efa NR |
767 | } |
768 | ||
769 | static void atmel_sha_finish_req(struct ahash_request *req, int err) | |
770 | { | |
771 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
772 | struct atmel_sha_dev *dd = ctx->dd; | |
773 | ||
774 | if (!err) { | |
775 | atmel_sha_copy_hash(req); | |
776 | if (SHA_FLAGS_FINAL & dd->flags) | |
777 | err = atmel_sha_finish(req); | |
778 | } else { | |
779 | ctx->flags |= SHA_FLAGS_ERROR; | |
780 | } | |
781 | ||
782 | /* atomic operation is not needed here */ | |
783 | dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU | | |
784 | SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY); | |
785 | ||
786 | clk_disable_unprepare(dd->iclk); | |
787 | ||
788 | if (req->base.complete) | |
789 | req->base.complete(&req->base, err); | |
790 | ||
791 | /* handle new request */ | |
f56809c3 | 792 | tasklet_schedule(&dd->queue_task); |
ebc82efa NR |
793 | } |
794 | ||
795 | static int atmel_sha_hw_init(struct atmel_sha_dev *dd) | |
796 | { | |
9d83d299 LC |
797 | int err; |
798 | ||
799 | err = clk_prepare_enable(dd->iclk); | |
800 | if (err) | |
801 | return err; | |
ebc82efa | 802 | |
d4905b38 | 803 | if (!(SHA_FLAGS_INIT & dd->flags)) { |
ebc82efa | 804 | atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST); |
ebc82efa NR |
805 | dd->flags |= SHA_FLAGS_INIT; |
806 | dd->err = 0; | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
d4905b38 NR |
812 | static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd) |
813 | { | |
814 | return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff; | |
815 | } | |
816 | ||
817 | static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd) | |
818 | { | |
819 | atmel_sha_hw_init(dd); | |
820 | ||
821 | dd->hw_version = atmel_sha_get_version(dd); | |
822 | ||
823 | dev_info(dd->dev, | |
824 | "version: 0x%x\n", dd->hw_version); | |
825 | ||
826 | clk_disable_unprepare(dd->iclk); | |
827 | } | |
828 | ||
ebc82efa NR |
829 | static int atmel_sha_handle_queue(struct atmel_sha_dev *dd, |
830 | struct ahash_request *req) | |
831 | { | |
832 | struct crypto_async_request *async_req, *backlog; | |
833 | struct atmel_sha_reqctx *ctx; | |
834 | unsigned long flags; | |
835 | int err = 0, ret = 0; | |
836 | ||
837 | spin_lock_irqsave(&dd->lock, flags); | |
838 | if (req) | |
839 | ret = ahash_enqueue_request(&dd->queue, req); | |
840 | ||
841 | if (SHA_FLAGS_BUSY & dd->flags) { | |
842 | spin_unlock_irqrestore(&dd->lock, flags); | |
843 | return ret; | |
844 | } | |
845 | ||
846 | backlog = crypto_get_backlog(&dd->queue); | |
847 | async_req = crypto_dequeue_request(&dd->queue); | |
848 | if (async_req) | |
849 | dd->flags |= SHA_FLAGS_BUSY; | |
850 | ||
851 | spin_unlock_irqrestore(&dd->lock, flags); | |
852 | ||
853 | if (!async_req) | |
854 | return ret; | |
855 | ||
856 | if (backlog) | |
857 | backlog->complete(backlog, -EINPROGRESS); | |
858 | ||
859 | req = ahash_request_cast(async_req); | |
860 | dd->req = req; | |
861 | ctx = ahash_request_ctx(req); | |
862 | ||
863 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", | |
864 | ctx->op, req->nbytes); | |
865 | ||
866 | err = atmel_sha_hw_init(dd); | |
867 | ||
868 | if (err) | |
869 | goto err1; | |
870 | ||
871 | if (ctx->op == SHA_OP_UPDATE) { | |
872 | err = atmel_sha_update_req(dd); | |
d4905b38 | 873 | if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP)) |
ebc82efa NR |
874 | /* no final() after finup() */ |
875 | err = atmel_sha_final_req(dd); | |
ebc82efa NR |
876 | } else if (ctx->op == SHA_OP_FINAL) { |
877 | err = atmel_sha_final_req(dd); | |
878 | } | |
879 | ||
880 | err1: | |
881 | if (err != -EINPROGRESS) | |
882 | /* done_task will not finish it, so do it here */ | |
883 | atmel_sha_finish_req(req, err); | |
884 | ||
885 | dev_dbg(dd->dev, "exit, err: %d\n", err); | |
886 | ||
887 | return ret; | |
888 | } | |
889 | ||
890 | static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op) | |
891 | { | |
892 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
893 | struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
894 | struct atmel_sha_dev *dd = tctx->dd; | |
895 | ||
896 | ctx->op = op; | |
897 | ||
898 | return atmel_sha_handle_queue(dd, req); | |
899 | } | |
900 | ||
901 | static int atmel_sha_update(struct ahash_request *req) | |
902 | { | |
903 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
904 | ||
905 | if (!req->nbytes) | |
906 | return 0; | |
907 | ||
908 | ctx->total = req->nbytes; | |
909 | ctx->sg = req->src; | |
910 | ctx->offset = 0; | |
911 | ||
912 | if (ctx->flags & SHA_FLAGS_FINUP) { | |
913 | if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD) | |
914 | /* faster to use CPU for short transfers */ | |
915 | ctx->flags |= SHA_FLAGS_CPU; | |
916 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { | |
917 | atmel_sha_append_sg(ctx); | |
918 | return 0; | |
919 | } | |
920 | return atmel_sha_enqueue(req, SHA_OP_UPDATE); | |
921 | } | |
922 | ||
923 | static int atmel_sha_final(struct ahash_request *req) | |
924 | { | |
925 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
926 | struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
927 | struct atmel_sha_dev *dd = tctx->dd; | |
928 | ||
929 | int err = 0; | |
930 | ||
931 | ctx->flags |= SHA_FLAGS_FINUP; | |
932 | ||
933 | if (ctx->flags & SHA_FLAGS_ERROR) | |
934 | return 0; /* uncompleted hash is not needed */ | |
935 | ||
936 | if (ctx->bufcnt) { | |
937 | return atmel_sha_enqueue(req, SHA_OP_FINAL); | |
938 | } else if (!(ctx->flags & SHA_FLAGS_PAD)) { /* add padding */ | |
939 | err = atmel_sha_hw_init(dd); | |
940 | if (err) | |
941 | goto err1; | |
942 | ||
1900c583 | 943 | dd->req = req; |
ebc82efa NR |
944 | dd->flags |= SHA_FLAGS_BUSY; |
945 | err = atmel_sha_final_req(dd); | |
946 | } else { | |
947 | /* copy ready hash (+ finalize hmac) */ | |
948 | return atmel_sha_finish(req); | |
949 | } | |
950 | ||
951 | err1: | |
952 | if (err != -EINPROGRESS) | |
953 | /* done_task will not finish it, so do it here */ | |
954 | atmel_sha_finish_req(req, err); | |
955 | ||
956 | return err; | |
957 | } | |
958 | ||
959 | static int atmel_sha_finup(struct ahash_request *req) | |
960 | { | |
961 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
962 | int err1, err2; | |
963 | ||
964 | ctx->flags |= SHA_FLAGS_FINUP; | |
965 | ||
966 | err1 = atmel_sha_update(req); | |
967 | if (err1 == -EINPROGRESS || err1 == -EBUSY) | |
968 | return err1; | |
969 | ||
970 | /* | |
971 | * final() has to be always called to cleanup resources | |
972 | * even if udpate() failed, except EINPROGRESS | |
973 | */ | |
974 | err2 = atmel_sha_final(req); | |
975 | ||
976 | return err1 ?: err2; | |
977 | } | |
978 | ||
979 | static int atmel_sha_digest(struct ahash_request *req) | |
980 | { | |
981 | return atmel_sha_init(req) ?: atmel_sha_finup(req); | |
982 | } | |
983 | ||
be95f0fa | 984 | static int atmel_sha_cra_init(struct crypto_tfm *tfm) |
ebc82efa | 985 | { |
ebc82efa NR |
986 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
987 | sizeof(struct atmel_sha_reqctx) + | |
d4905b38 | 988 | SHA_BUFFER_LEN + SHA512_BLOCK_SIZE); |
ebc82efa NR |
989 | |
990 | return 0; | |
991 | } | |
992 | ||
d4905b38 | 993 | static struct ahash_alg sha_1_256_algs[] = { |
ebc82efa NR |
994 | { |
995 | .init = atmel_sha_init, | |
996 | .update = atmel_sha_update, | |
997 | .final = atmel_sha_final, | |
998 | .finup = atmel_sha_finup, | |
999 | .digest = atmel_sha_digest, | |
1000 | .halg = { | |
1001 | .digestsize = SHA1_DIGEST_SIZE, | |
1002 | .base = { | |
1003 | .cra_name = "sha1", | |
1004 | .cra_driver_name = "atmel-sha1", | |
1005 | .cra_priority = 100, | |
be95f0fa | 1006 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1007 | .cra_blocksize = SHA1_BLOCK_SIZE, |
1008 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1009 | .cra_alignmask = 0, | |
1010 | .cra_module = THIS_MODULE, | |
1011 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1012 | } |
1013 | } | |
1014 | }, | |
1015 | { | |
1016 | .init = atmel_sha_init, | |
1017 | .update = atmel_sha_update, | |
1018 | .final = atmel_sha_final, | |
1019 | .finup = atmel_sha_finup, | |
1020 | .digest = atmel_sha_digest, | |
1021 | .halg = { | |
1022 | .digestsize = SHA256_DIGEST_SIZE, | |
1023 | .base = { | |
1024 | .cra_name = "sha256", | |
1025 | .cra_driver_name = "atmel-sha256", | |
1026 | .cra_priority = 100, | |
be95f0fa | 1027 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1028 | .cra_blocksize = SHA256_BLOCK_SIZE, |
1029 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1030 | .cra_alignmask = 0, | |
1031 | .cra_module = THIS_MODULE, | |
1032 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1033 | } |
1034 | } | |
1035 | }, | |
1036 | }; | |
1037 | ||
d4905b38 NR |
1038 | static struct ahash_alg sha_224_alg = { |
1039 | .init = atmel_sha_init, | |
1040 | .update = atmel_sha_update, | |
1041 | .final = atmel_sha_final, | |
1042 | .finup = atmel_sha_finup, | |
1043 | .digest = atmel_sha_digest, | |
1044 | .halg = { | |
1045 | .digestsize = SHA224_DIGEST_SIZE, | |
1046 | .base = { | |
1047 | .cra_name = "sha224", | |
1048 | .cra_driver_name = "atmel-sha224", | |
1049 | .cra_priority = 100, | |
be95f0fa | 1050 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1051 | .cra_blocksize = SHA224_BLOCK_SIZE, |
1052 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1053 | .cra_alignmask = 0, | |
1054 | .cra_module = THIS_MODULE, | |
1055 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1056 | } |
1057 | } | |
1058 | }; | |
1059 | ||
1060 | static struct ahash_alg sha_384_512_algs[] = { | |
1061 | { | |
1062 | .init = atmel_sha_init, | |
1063 | .update = atmel_sha_update, | |
1064 | .final = atmel_sha_final, | |
1065 | .finup = atmel_sha_finup, | |
1066 | .digest = atmel_sha_digest, | |
1067 | .halg = { | |
1068 | .digestsize = SHA384_DIGEST_SIZE, | |
1069 | .base = { | |
1070 | .cra_name = "sha384", | |
1071 | .cra_driver_name = "atmel-sha384", | |
1072 | .cra_priority = 100, | |
be95f0fa | 1073 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1074 | .cra_blocksize = SHA384_BLOCK_SIZE, |
1075 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1076 | .cra_alignmask = 0x3, | |
1077 | .cra_module = THIS_MODULE, | |
1078 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1079 | } |
1080 | } | |
1081 | }, | |
1082 | { | |
1083 | .init = atmel_sha_init, | |
1084 | .update = atmel_sha_update, | |
1085 | .final = atmel_sha_final, | |
1086 | .finup = atmel_sha_finup, | |
1087 | .digest = atmel_sha_digest, | |
1088 | .halg = { | |
1089 | .digestsize = SHA512_DIGEST_SIZE, | |
1090 | .base = { | |
1091 | .cra_name = "sha512", | |
1092 | .cra_driver_name = "atmel-sha512", | |
1093 | .cra_priority = 100, | |
be95f0fa | 1094 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1095 | .cra_blocksize = SHA512_BLOCK_SIZE, |
1096 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1097 | .cra_alignmask = 0x3, | |
1098 | .cra_module = THIS_MODULE, | |
1099 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1100 | } |
1101 | } | |
1102 | }, | |
1103 | }; | |
1104 | ||
f56809c3 CP |
1105 | static void atmel_sha_queue_task(unsigned long data) |
1106 | { | |
1107 | struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; | |
1108 | ||
1109 | atmel_sha_handle_queue(dd, NULL); | |
1110 | } | |
1111 | ||
ebc82efa NR |
1112 | static void atmel_sha_done_task(unsigned long data) |
1113 | { | |
1114 | struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; | |
1115 | int err = 0; | |
1116 | ||
ebc82efa NR |
1117 | if (SHA_FLAGS_CPU & dd->flags) { |
1118 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1119 | dd->flags &= ~SHA_FLAGS_OUTPUT_READY; | |
1120 | goto finish; | |
1121 | } | |
1122 | } else if (SHA_FLAGS_DMA_READY & dd->flags) { | |
1123 | if (SHA_FLAGS_DMA_ACTIVE & dd->flags) { | |
1124 | dd->flags &= ~SHA_FLAGS_DMA_ACTIVE; | |
1125 | atmel_sha_update_dma_stop(dd); | |
1126 | if (dd->err) { | |
1127 | err = dd->err; | |
1128 | goto finish; | |
1129 | } | |
1130 | } | |
1131 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1132 | /* hash or semi-hash ready */ | |
1133 | dd->flags &= ~(SHA_FLAGS_DMA_READY | | |
1134 | SHA_FLAGS_OUTPUT_READY); | |
1135 | err = atmel_sha_update_dma_start(dd); | |
1136 | if (err != -EINPROGRESS) | |
1137 | goto finish; | |
1138 | } | |
1139 | } | |
1140 | return; | |
1141 | ||
1142 | finish: | |
1143 | /* finish curent request */ | |
1144 | atmel_sha_finish_req(dd->req, err); | |
1145 | } | |
1146 | ||
1147 | static irqreturn_t atmel_sha_irq(int irq, void *dev_id) | |
1148 | { | |
1149 | struct atmel_sha_dev *sha_dd = dev_id; | |
1150 | u32 reg; | |
1151 | ||
1152 | reg = atmel_sha_read(sha_dd, SHA_ISR); | |
1153 | if (reg & atmel_sha_read(sha_dd, SHA_IMR)) { | |
1154 | atmel_sha_write(sha_dd, SHA_IDR, reg); | |
1155 | if (SHA_FLAGS_BUSY & sha_dd->flags) { | |
1156 | sha_dd->flags |= SHA_FLAGS_OUTPUT_READY; | |
1157 | if (!(SHA_FLAGS_CPU & sha_dd->flags)) | |
1158 | sha_dd->flags |= SHA_FLAGS_DMA_READY; | |
1159 | tasklet_schedule(&sha_dd->done_task); | |
1160 | } else { | |
1161 | dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n"); | |
1162 | } | |
1163 | return IRQ_HANDLED; | |
1164 | } | |
1165 | ||
1166 | return IRQ_NONE; | |
1167 | } | |
1168 | ||
1169 | static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd) | |
1170 | { | |
1171 | int i; | |
1172 | ||
d4905b38 NR |
1173 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) |
1174 | crypto_unregister_ahash(&sha_1_256_algs[i]); | |
1175 | ||
1176 | if (dd->caps.has_sha224) | |
1177 | crypto_unregister_ahash(&sha_224_alg); | |
1178 | ||
1179 | if (dd->caps.has_sha_384_512) { | |
1180 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) | |
1181 | crypto_unregister_ahash(&sha_384_512_algs[i]); | |
1182 | } | |
ebc82efa NR |
1183 | } |
1184 | ||
1185 | static int atmel_sha_register_algs(struct atmel_sha_dev *dd) | |
1186 | { | |
1187 | int err, i, j; | |
1188 | ||
d4905b38 NR |
1189 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) { |
1190 | err = crypto_register_ahash(&sha_1_256_algs[i]); | |
ebc82efa | 1191 | if (err) |
d4905b38 NR |
1192 | goto err_sha_1_256_algs; |
1193 | } | |
1194 | ||
1195 | if (dd->caps.has_sha224) { | |
1196 | err = crypto_register_ahash(&sha_224_alg); | |
1197 | if (err) | |
1198 | goto err_sha_224_algs; | |
1199 | } | |
1200 | ||
1201 | if (dd->caps.has_sha_384_512) { | |
1202 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) { | |
1203 | err = crypto_register_ahash(&sha_384_512_algs[i]); | |
1204 | if (err) | |
1205 | goto err_sha_384_512_algs; | |
1206 | } | |
ebc82efa NR |
1207 | } |
1208 | ||
1209 | return 0; | |
1210 | ||
d4905b38 NR |
1211 | err_sha_384_512_algs: |
1212 | for (j = 0; j < i; j++) | |
1213 | crypto_unregister_ahash(&sha_384_512_algs[j]); | |
1214 | crypto_unregister_ahash(&sha_224_alg); | |
1215 | err_sha_224_algs: | |
1216 | i = ARRAY_SIZE(sha_1_256_algs); | |
1217 | err_sha_1_256_algs: | |
ebc82efa | 1218 | for (j = 0; j < i; j++) |
d4905b38 | 1219 | crypto_unregister_ahash(&sha_1_256_algs[j]); |
ebc82efa NR |
1220 | |
1221 | return err; | |
1222 | } | |
1223 | ||
d4905b38 NR |
1224 | static bool atmel_sha_filter(struct dma_chan *chan, void *slave) |
1225 | { | |
1226 | struct at_dma_slave *sl = slave; | |
1227 | ||
1228 | if (sl && sl->dma_dev == chan->device->dev) { | |
1229 | chan->private = sl; | |
1230 | return true; | |
1231 | } else { | |
1232 | return false; | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | static int atmel_sha_dma_init(struct atmel_sha_dev *dd, | |
1237 | struct crypto_platform_data *pdata) | |
1238 | { | |
1239 | int err = -ENOMEM; | |
1240 | dma_cap_mask_t mask_in; | |
1241 | ||
abfe7ae4 NF |
1242 | /* Try to grab DMA channel */ |
1243 | dma_cap_zero(mask_in); | |
1244 | dma_cap_set(DMA_SLAVE, mask_in); | |
d4905b38 | 1245 | |
abfe7ae4 NF |
1246 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in, |
1247 | atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); | |
1248 | if (!dd->dma_lch_in.chan) { | |
1249 | dev_warn(dd->dev, "no DMA channel available\n"); | |
1250 | return err; | |
d4905b38 NR |
1251 | } |
1252 | ||
abfe7ae4 NF |
1253 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; |
1254 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | |
1255 | SHA_REG_DIN(0); | |
1256 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | |
1257 | dd->dma_lch_in.dma_conf.src_addr_width = | |
1258 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1259 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | |
1260 | dd->dma_lch_in.dma_conf.dst_addr_width = | |
1261 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1262 | dd->dma_lch_in.dma_conf.device_fc = false; | |
1263 | ||
1264 | return 0; | |
d4905b38 NR |
1265 | } |
1266 | ||
1267 | static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) | |
1268 | { | |
1269 | dma_release_channel(dd->dma_lch_in.chan); | |
1270 | } | |
1271 | ||
1272 | static void atmel_sha_get_cap(struct atmel_sha_dev *dd) | |
1273 | { | |
1274 | ||
1275 | dd->caps.has_dma = 0; | |
1276 | dd->caps.has_dualbuff = 0; | |
1277 | dd->caps.has_sha224 = 0; | |
1278 | dd->caps.has_sha_384_512 = 0; | |
1279 | ||
1280 | /* keep only major version number */ | |
1281 | switch (dd->hw_version & 0xff0) { | |
141824d0 LZ |
1282 | case 0x420: |
1283 | dd->caps.has_dma = 1; | |
1284 | dd->caps.has_dualbuff = 1; | |
1285 | dd->caps.has_sha224 = 1; | |
1286 | dd->caps.has_sha_384_512 = 1; | |
1287 | break; | |
d4905b38 NR |
1288 | case 0x410: |
1289 | dd->caps.has_dma = 1; | |
1290 | dd->caps.has_dualbuff = 1; | |
1291 | dd->caps.has_sha224 = 1; | |
1292 | dd->caps.has_sha_384_512 = 1; | |
1293 | break; | |
1294 | case 0x400: | |
1295 | dd->caps.has_dma = 1; | |
1296 | dd->caps.has_dualbuff = 1; | |
1297 | dd->caps.has_sha224 = 1; | |
1298 | break; | |
1299 | case 0x320: | |
1300 | break; | |
1301 | default: | |
1302 | dev_warn(dd->dev, | |
1303 | "Unmanaged sha version, set minimum capabilities\n"); | |
1304 | break; | |
1305 | } | |
1306 | } | |
1307 | ||
abfe7ae4 NF |
1308 | #if defined(CONFIG_OF) |
1309 | static const struct of_device_id atmel_sha_dt_ids[] = { | |
1310 | { .compatible = "atmel,at91sam9g46-sha" }, | |
1311 | { /* sentinel */ } | |
1312 | }; | |
1313 | ||
1314 | MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids); | |
1315 | ||
1316 | static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev) | |
1317 | { | |
1318 | struct device_node *np = pdev->dev.of_node; | |
1319 | struct crypto_platform_data *pdata; | |
1320 | ||
1321 | if (!np) { | |
1322 | dev_err(&pdev->dev, "device node not found\n"); | |
1323 | return ERR_PTR(-EINVAL); | |
1324 | } | |
1325 | ||
1326 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1327 | if (!pdata) { | |
1328 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
1329 | return ERR_PTR(-ENOMEM); | |
1330 | } | |
1331 | ||
1332 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | |
1333 | sizeof(*(pdata->dma_slave)), | |
1334 | GFP_KERNEL); | |
1335 | if (!pdata->dma_slave) { | |
1336 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | |
abfe7ae4 NF |
1337 | return ERR_PTR(-ENOMEM); |
1338 | } | |
1339 | ||
1340 | return pdata; | |
1341 | } | |
1342 | #else /* CONFIG_OF */ | |
1343 | static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev) | |
1344 | { | |
1345 | return ERR_PTR(-EINVAL); | |
1346 | } | |
1347 | #endif | |
1348 | ||
49cfe4db | 1349 | static int atmel_sha_probe(struct platform_device *pdev) |
ebc82efa NR |
1350 | { |
1351 | struct atmel_sha_dev *sha_dd; | |
d4905b38 | 1352 | struct crypto_platform_data *pdata; |
ebc82efa NR |
1353 | struct device *dev = &pdev->dev; |
1354 | struct resource *sha_res; | |
ebc82efa NR |
1355 | int err; |
1356 | ||
b0e8b341 | 1357 | sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL); |
ebc82efa NR |
1358 | if (sha_dd == NULL) { |
1359 | dev_err(dev, "unable to alloc data struct.\n"); | |
1360 | err = -ENOMEM; | |
1361 | goto sha_dd_err; | |
1362 | } | |
1363 | ||
1364 | sha_dd->dev = dev; | |
1365 | ||
1366 | platform_set_drvdata(pdev, sha_dd); | |
1367 | ||
1368 | INIT_LIST_HEAD(&sha_dd->list); | |
62728e82 | 1369 | spin_lock_init(&sha_dd->lock); |
ebc82efa NR |
1370 | |
1371 | tasklet_init(&sha_dd->done_task, atmel_sha_done_task, | |
1372 | (unsigned long)sha_dd); | |
f56809c3 CP |
1373 | tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task, |
1374 | (unsigned long)sha_dd); | |
ebc82efa NR |
1375 | |
1376 | crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH); | |
1377 | ||
1378 | sha_dd->irq = -1; | |
1379 | ||
1380 | /* Get the base address */ | |
1381 | sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1382 | if (!sha_res) { | |
1383 | dev_err(dev, "no MEM resource info\n"); | |
1384 | err = -ENODEV; | |
1385 | goto res_err; | |
1386 | } | |
1387 | sha_dd->phys_base = sha_res->start; | |
ebc82efa NR |
1388 | |
1389 | /* Get the IRQ */ | |
1390 | sha_dd->irq = platform_get_irq(pdev, 0); | |
1391 | if (sha_dd->irq < 0) { | |
1392 | dev_err(dev, "no IRQ resource info\n"); | |
1393 | err = sha_dd->irq; | |
1394 | goto res_err; | |
1395 | } | |
1396 | ||
b0e8b341 LC |
1397 | err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq, |
1398 | IRQF_SHARED, "atmel-sha", sha_dd); | |
ebc82efa NR |
1399 | if (err) { |
1400 | dev_err(dev, "unable to request sha irq.\n"); | |
1401 | goto res_err; | |
1402 | } | |
1403 | ||
1404 | /* Initializing the clock */ | |
b0e8b341 | 1405 | sha_dd->iclk = devm_clk_get(&pdev->dev, "sha_clk"); |
ebc82efa | 1406 | if (IS_ERR(sha_dd->iclk)) { |
be208356 | 1407 | dev_err(dev, "clock initialization failed.\n"); |
ebc82efa | 1408 | err = PTR_ERR(sha_dd->iclk); |
b0e8b341 | 1409 | goto res_err; |
ebc82efa NR |
1410 | } |
1411 | ||
b0e8b341 | 1412 | sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res); |
ebc82efa NR |
1413 | if (!sha_dd->io_base) { |
1414 | dev_err(dev, "can't ioremap\n"); | |
1415 | err = -ENOMEM; | |
b0e8b341 | 1416 | goto res_err; |
ebc82efa NR |
1417 | } |
1418 | ||
d4905b38 NR |
1419 | atmel_sha_hw_version_init(sha_dd); |
1420 | ||
1421 | atmel_sha_get_cap(sha_dd); | |
1422 | ||
1423 | if (sha_dd->caps.has_dma) { | |
1424 | pdata = pdev->dev.platform_data; | |
1425 | if (!pdata) { | |
abfe7ae4 NF |
1426 | pdata = atmel_sha_of_init(pdev); |
1427 | if (IS_ERR(pdata)) { | |
1428 | dev_err(&pdev->dev, "platform data not available\n"); | |
1429 | err = PTR_ERR(pdata); | |
b0e8b341 | 1430 | goto res_err; |
abfe7ae4 NF |
1431 | } |
1432 | } | |
1433 | if (!pdata->dma_slave) { | |
d4905b38 | 1434 | err = -ENXIO; |
b0e8b341 | 1435 | goto res_err; |
d4905b38 NR |
1436 | } |
1437 | err = atmel_sha_dma_init(sha_dd, pdata); | |
1438 | if (err) | |
1439 | goto err_sha_dma; | |
abfe7ae4 NF |
1440 | |
1441 | dev_info(dev, "using %s for DMA transfers\n", | |
1442 | dma_chan_name(sha_dd->dma_lch_in.chan)); | |
d4905b38 NR |
1443 | } |
1444 | ||
ebc82efa NR |
1445 | spin_lock(&atmel_sha.lock); |
1446 | list_add_tail(&sha_dd->list, &atmel_sha.dev_list); | |
1447 | spin_unlock(&atmel_sha.lock); | |
1448 | ||
1449 | err = atmel_sha_register_algs(sha_dd); | |
1450 | if (err) | |
1451 | goto err_algs; | |
1452 | ||
1ca5b7d9 NF |
1453 | dev_info(dev, "Atmel SHA1/SHA256%s%s\n", |
1454 | sha_dd->caps.has_sha224 ? "/SHA224" : "", | |
1455 | sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : ""); | |
ebc82efa NR |
1456 | |
1457 | return 0; | |
1458 | ||
1459 | err_algs: | |
1460 | spin_lock(&atmel_sha.lock); | |
1461 | list_del(&sha_dd->list); | |
1462 | spin_unlock(&atmel_sha.lock); | |
d4905b38 NR |
1463 | if (sha_dd->caps.has_dma) |
1464 | atmel_sha_dma_cleanup(sha_dd); | |
1465 | err_sha_dma: | |
ebc82efa | 1466 | res_err: |
f56809c3 | 1467 | tasklet_kill(&sha_dd->queue_task); |
ebc82efa | 1468 | tasklet_kill(&sha_dd->done_task); |
ebc82efa NR |
1469 | sha_dd_err: |
1470 | dev_err(dev, "initialization failed.\n"); | |
1471 | ||
1472 | return err; | |
1473 | } | |
1474 | ||
49cfe4db | 1475 | static int atmel_sha_remove(struct platform_device *pdev) |
ebc82efa NR |
1476 | { |
1477 | static struct atmel_sha_dev *sha_dd; | |
1478 | ||
1479 | sha_dd = platform_get_drvdata(pdev); | |
1480 | if (!sha_dd) | |
1481 | return -ENODEV; | |
1482 | spin_lock(&atmel_sha.lock); | |
1483 | list_del(&sha_dd->list); | |
1484 | spin_unlock(&atmel_sha.lock); | |
1485 | ||
1486 | atmel_sha_unregister_algs(sha_dd); | |
1487 | ||
f56809c3 | 1488 | tasklet_kill(&sha_dd->queue_task); |
ebc82efa NR |
1489 | tasklet_kill(&sha_dd->done_task); |
1490 | ||
d4905b38 NR |
1491 | if (sha_dd->caps.has_dma) |
1492 | atmel_sha_dma_cleanup(sha_dd); | |
1493 | ||
ebc82efa NR |
1494 | iounmap(sha_dd->io_base); |
1495 | ||
1496 | clk_put(sha_dd->iclk); | |
1497 | ||
1498 | if (sha_dd->irq >= 0) | |
1499 | free_irq(sha_dd->irq, sha_dd); | |
1500 | ||
ebc82efa NR |
1501 | return 0; |
1502 | } | |
1503 | ||
1504 | static struct platform_driver atmel_sha_driver = { | |
1505 | .probe = atmel_sha_probe, | |
49cfe4db | 1506 | .remove = atmel_sha_remove, |
ebc82efa NR |
1507 | .driver = { |
1508 | .name = "atmel_sha", | |
abfe7ae4 | 1509 | .of_match_table = of_match_ptr(atmel_sha_dt_ids), |
ebc82efa NR |
1510 | }, |
1511 | }; | |
1512 | ||
1513 | module_platform_driver(atmel_sha_driver); | |
1514 | ||
d4905b38 | 1515 | MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support."); |
ebc82efa NR |
1516 | MODULE_LICENSE("GPL v2"); |
1517 | MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); |