Commit | Line | Data |
---|---|---|
ebc82efa NR |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for ATMEL SHA1/SHA256 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2012 Eukréa Electromatique - ATMEL | |
7 | * Author: Nicolas Royer <nicolas@eukrea.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | * | |
13 | * Some ideas are from omap-sham.c drivers. | |
14 | */ | |
15 | ||
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/hw_random.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include <linux/device.h> | |
ebc82efa NR |
27 | #include <linux/init.h> |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
ebc82efa | 30 | #include <linux/irq.h> |
ebc82efa NR |
31 | #include <linux/scatterlist.h> |
32 | #include <linux/dma-mapping.h> | |
abfe7ae4 | 33 | #include <linux/of_device.h> |
ebc82efa NR |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
36 | #include <linux/cryptohash.h> | |
37 | #include <crypto/scatterwalk.h> | |
38 | #include <crypto/algapi.h> | |
39 | #include <crypto/sha.h> | |
40 | #include <crypto/hash.h> | |
41 | #include <crypto/internal/hash.h> | |
d4905b38 | 42 | #include <linux/platform_data/crypto-atmel.h> |
ebc82efa NR |
43 | #include "atmel-sha-regs.h" |
44 | ||
45 | /* SHA flags */ | |
46 | #define SHA_FLAGS_BUSY BIT(0) | |
47 | #define SHA_FLAGS_FINAL BIT(1) | |
48 | #define SHA_FLAGS_DMA_ACTIVE BIT(2) | |
49 | #define SHA_FLAGS_OUTPUT_READY BIT(3) | |
50 | #define SHA_FLAGS_INIT BIT(4) | |
51 | #define SHA_FLAGS_CPU BIT(5) | |
52 | #define SHA_FLAGS_DMA_READY BIT(6) | |
53 | ||
54 | #define SHA_FLAGS_FINUP BIT(16) | |
55 | #define SHA_FLAGS_SG BIT(17) | |
56 | #define SHA_FLAGS_SHA1 BIT(18) | |
d4905b38 NR |
57 | #define SHA_FLAGS_SHA224 BIT(19) |
58 | #define SHA_FLAGS_SHA256 BIT(20) | |
59 | #define SHA_FLAGS_SHA384 BIT(21) | |
60 | #define SHA_FLAGS_SHA512 BIT(22) | |
61 | #define SHA_FLAGS_ERROR BIT(23) | |
62 | #define SHA_FLAGS_PAD BIT(24) | |
ebc82efa NR |
63 | |
64 | #define SHA_OP_UPDATE 1 | |
65 | #define SHA_OP_FINAL 2 | |
66 | ||
67 | #define SHA_BUFFER_LEN PAGE_SIZE | |
68 | ||
69 | #define ATMEL_SHA_DMA_THRESHOLD 56 | |
70 | ||
d4905b38 NR |
71 | struct atmel_sha_caps { |
72 | bool has_dma; | |
73 | bool has_dualbuff; | |
74 | bool has_sha224; | |
75 | bool has_sha_384_512; | |
76 | }; | |
ebc82efa NR |
77 | |
78 | struct atmel_sha_dev; | |
79 | ||
80 | struct atmel_sha_reqctx { | |
81 | struct atmel_sha_dev *dd; | |
82 | unsigned long flags; | |
83 | unsigned long op; | |
84 | ||
d4905b38 NR |
85 | u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32)); |
86 | u64 digcnt[2]; | |
ebc82efa NR |
87 | size_t bufcnt; |
88 | size_t buflen; | |
89 | dma_addr_t dma_addr; | |
90 | ||
91 | /* walk state */ | |
92 | struct scatterlist *sg; | |
93 | unsigned int offset; /* offset in current sg */ | |
94 | unsigned int total; /* total request */ | |
95 | ||
d4905b38 NR |
96 | size_t block_size; |
97 | ||
ebc82efa NR |
98 | u8 buffer[0] __aligned(sizeof(u32)); |
99 | }; | |
100 | ||
101 | struct atmel_sha_ctx { | |
102 | struct atmel_sha_dev *dd; | |
103 | ||
104 | unsigned long flags; | |
ebc82efa NR |
105 | }; |
106 | ||
d4905b38 NR |
107 | #define ATMEL_SHA_QUEUE_LENGTH 50 |
108 | ||
109 | struct atmel_sha_dma { | |
110 | struct dma_chan *chan; | |
111 | struct dma_slave_config dma_conf; | |
112 | }; | |
ebc82efa NR |
113 | |
114 | struct atmel_sha_dev { | |
115 | struct list_head list; | |
116 | unsigned long phys_base; | |
117 | struct device *dev; | |
118 | struct clk *iclk; | |
119 | int irq; | |
120 | void __iomem *io_base; | |
121 | ||
122 | spinlock_t lock; | |
123 | int err; | |
124 | struct tasklet_struct done_task; | |
125 | ||
126 | unsigned long flags; | |
127 | struct crypto_queue queue; | |
128 | struct ahash_request *req; | |
d4905b38 NR |
129 | |
130 | struct atmel_sha_dma dma_lch_in; | |
131 | ||
132 | struct atmel_sha_caps caps; | |
133 | ||
134 | u32 hw_version; | |
ebc82efa NR |
135 | }; |
136 | ||
137 | struct atmel_sha_drv { | |
138 | struct list_head dev_list; | |
139 | spinlock_t lock; | |
140 | }; | |
141 | ||
142 | static struct atmel_sha_drv atmel_sha = { | |
143 | .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list), | |
144 | .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock), | |
145 | }; | |
146 | ||
147 | static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset) | |
148 | { | |
149 | return readl_relaxed(dd->io_base + offset); | |
150 | } | |
151 | ||
152 | static inline void atmel_sha_write(struct atmel_sha_dev *dd, | |
153 | u32 offset, u32 value) | |
154 | { | |
155 | writel_relaxed(value, dd->io_base + offset); | |
156 | } | |
157 | ||
ebc82efa NR |
158 | static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx) |
159 | { | |
160 | size_t count; | |
161 | ||
162 | while ((ctx->bufcnt < ctx->buflen) && ctx->total) { | |
163 | count = min(ctx->sg->length - ctx->offset, ctx->total); | |
164 | count = min(count, ctx->buflen - ctx->bufcnt); | |
165 | ||
803eeae8 LZ |
166 | if (count <= 0) { |
167 | /* | |
168 | * Check if count <= 0 because the buffer is full or | |
169 | * because the sg length is 0. In the latest case, | |
170 | * check if there is another sg in the list, a 0 length | |
171 | * sg doesn't necessarily mean the end of the sg list. | |
172 | */ | |
173 | if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) { | |
174 | ctx->sg = sg_next(ctx->sg); | |
175 | continue; | |
176 | } else { | |
177 | break; | |
178 | } | |
179 | } | |
ebc82efa NR |
180 | |
181 | scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg, | |
182 | ctx->offset, count, 0); | |
183 | ||
184 | ctx->bufcnt += count; | |
185 | ctx->offset += count; | |
186 | ctx->total -= count; | |
187 | ||
188 | if (ctx->offset == ctx->sg->length) { | |
189 | ctx->sg = sg_next(ctx->sg); | |
190 | if (ctx->sg) | |
191 | ctx->offset = 0; | |
192 | else | |
193 | ctx->total = 0; | |
194 | } | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /* | |
d4905b38 NR |
201 | * The purpose of this padding is to ensure that the padded message is a |
202 | * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). | |
203 | * The bit "1" is appended at the end of the message followed by | |
204 | * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or | |
205 | * 128 bits block (SHA384/SHA512) equals to the message length in bits | |
206 | * is appended. | |
ebc82efa | 207 | * |
d4905b38 | 208 | * For SHA1/SHA224/SHA256, padlen is calculated as followed: |
ebc82efa NR |
209 | * - if message length < 56 bytes then padlen = 56 - message length |
210 | * - else padlen = 64 + 56 - message length | |
d4905b38 NR |
211 | * |
212 | * For SHA384/SHA512, padlen is calculated as followed: | |
213 | * - if message length < 112 bytes then padlen = 112 - message length | |
214 | * - else padlen = 128 + 112 - message length | |
ebc82efa NR |
215 | */ |
216 | static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length) | |
217 | { | |
218 | unsigned int index, padlen; | |
d4905b38 NR |
219 | u64 bits[2]; |
220 | u64 size[2]; | |
221 | ||
222 | size[0] = ctx->digcnt[0]; | |
223 | size[1] = ctx->digcnt[1]; | |
224 | ||
225 | size[0] += ctx->bufcnt; | |
226 | if (size[0] < ctx->bufcnt) | |
227 | size[1]++; | |
228 | ||
229 | size[0] += length; | |
230 | if (size[0] < length) | |
231 | size[1]++; | |
232 | ||
233 | bits[1] = cpu_to_be64(size[0] << 3); | |
234 | bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61); | |
235 | ||
236 | if (ctx->flags & (SHA_FLAGS_SHA384 | SHA_FLAGS_SHA512)) { | |
237 | index = ctx->bufcnt & 0x7f; | |
238 | padlen = (index < 112) ? (112 - index) : ((128+112) - index); | |
239 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
240 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
241 | memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16); | |
242 | ctx->bufcnt += padlen + 16; | |
243 | ctx->flags |= SHA_FLAGS_PAD; | |
244 | } else { | |
245 | index = ctx->bufcnt & 0x3f; | |
246 | padlen = (index < 56) ? (56 - index) : ((64+56) - index); | |
247 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
248 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
249 | memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8); | |
250 | ctx->bufcnt += padlen + 8; | |
251 | ctx->flags |= SHA_FLAGS_PAD; | |
252 | } | |
ebc82efa NR |
253 | } |
254 | ||
255 | static int atmel_sha_init(struct ahash_request *req) | |
256 | { | |
257 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
258 | struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm); | |
259 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
260 | struct atmel_sha_dev *dd = NULL; | |
261 | struct atmel_sha_dev *tmp; | |
262 | ||
263 | spin_lock_bh(&atmel_sha.lock); | |
264 | if (!tctx->dd) { | |
265 | list_for_each_entry(tmp, &atmel_sha.dev_list, list) { | |
266 | dd = tmp; | |
267 | break; | |
268 | } | |
269 | tctx->dd = dd; | |
270 | } else { | |
271 | dd = tctx->dd; | |
272 | } | |
273 | ||
274 | spin_unlock_bh(&atmel_sha.lock); | |
275 | ||
276 | ctx->dd = dd; | |
277 | ||
278 | ctx->flags = 0; | |
279 | ||
280 | dev_dbg(dd->dev, "init: digest size: %d\n", | |
281 | crypto_ahash_digestsize(tfm)); | |
282 | ||
d4905b38 NR |
283 | switch (crypto_ahash_digestsize(tfm)) { |
284 | case SHA1_DIGEST_SIZE: | |
ebc82efa | 285 | ctx->flags |= SHA_FLAGS_SHA1; |
d4905b38 NR |
286 | ctx->block_size = SHA1_BLOCK_SIZE; |
287 | break; | |
288 | case SHA224_DIGEST_SIZE: | |
289 | ctx->flags |= SHA_FLAGS_SHA224; | |
290 | ctx->block_size = SHA224_BLOCK_SIZE; | |
291 | break; | |
292 | case SHA256_DIGEST_SIZE: | |
ebc82efa | 293 | ctx->flags |= SHA_FLAGS_SHA256; |
d4905b38 NR |
294 | ctx->block_size = SHA256_BLOCK_SIZE; |
295 | break; | |
296 | case SHA384_DIGEST_SIZE: | |
297 | ctx->flags |= SHA_FLAGS_SHA384; | |
298 | ctx->block_size = SHA384_BLOCK_SIZE; | |
299 | break; | |
300 | case SHA512_DIGEST_SIZE: | |
301 | ctx->flags |= SHA_FLAGS_SHA512; | |
302 | ctx->block_size = SHA512_BLOCK_SIZE; | |
303 | break; | |
304 | default: | |
305 | return -EINVAL; | |
306 | break; | |
307 | } | |
ebc82efa NR |
308 | |
309 | ctx->bufcnt = 0; | |
d4905b38 NR |
310 | ctx->digcnt[0] = 0; |
311 | ctx->digcnt[1] = 0; | |
ebc82efa NR |
312 | ctx->buflen = SHA_BUFFER_LEN; |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma) | |
318 | { | |
319 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
320 | u32 valcr = 0, valmr = SHA_MR_MODE_AUTO; | |
321 | ||
322 | if (likely(dma)) { | |
d4905b38 NR |
323 | if (!dd->caps.has_dma) |
324 | atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE); | |
ebc82efa | 325 | valmr = SHA_MR_MODE_PDC; |
d4905b38 NR |
326 | if (dd->caps.has_dualbuff) |
327 | valmr |= SHA_MR_DUALBUFF; | |
ebc82efa NR |
328 | } else { |
329 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
330 | } | |
331 | ||
d4905b38 NR |
332 | if (ctx->flags & SHA_FLAGS_SHA1) |
333 | valmr |= SHA_MR_ALGO_SHA1; | |
334 | else if (ctx->flags & SHA_FLAGS_SHA224) | |
335 | valmr |= SHA_MR_ALGO_SHA224; | |
336 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa | 337 | valmr |= SHA_MR_ALGO_SHA256; |
d4905b38 NR |
338 | else if (ctx->flags & SHA_FLAGS_SHA384) |
339 | valmr |= SHA_MR_ALGO_SHA384; | |
340 | else if (ctx->flags & SHA_FLAGS_SHA512) | |
341 | valmr |= SHA_MR_ALGO_SHA512; | |
ebc82efa NR |
342 | |
343 | /* Setting CR_FIRST only for the first iteration */ | |
d4905b38 | 344 | if (!(ctx->digcnt[0] || ctx->digcnt[1])) |
ebc82efa NR |
345 | valcr = SHA_CR_FIRST; |
346 | ||
347 | atmel_sha_write(dd, SHA_CR, valcr); | |
348 | atmel_sha_write(dd, SHA_MR, valmr); | |
349 | } | |
350 | ||
351 | static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf, | |
352 | size_t length, int final) | |
353 | { | |
354 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
355 | int count, len32; | |
356 | const u32 *buffer = (const u32 *)buf; | |
357 | ||
d4905b38 NR |
358 | dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
359 | ctx->digcnt[1], ctx->digcnt[0], length, final); | |
ebc82efa NR |
360 | |
361 | atmel_sha_write_ctrl(dd, 0); | |
362 | ||
363 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
364 | ctx->digcnt[0] += length; |
365 | if (ctx->digcnt[0] < length) | |
366 | ctx->digcnt[1]++; | |
ebc82efa NR |
367 | |
368 | if (final) | |
369 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
370 | ||
371 | len32 = DIV_ROUND_UP(length, sizeof(u32)); | |
372 | ||
373 | dd->flags |= SHA_FLAGS_CPU; | |
374 | ||
375 | for (count = 0; count < len32; count++) | |
376 | atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]); | |
377 | ||
378 | return -EINPROGRESS; | |
379 | } | |
380 | ||
381 | static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
382 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
383 | { | |
384 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
385 | int len32; | |
386 | ||
d4905b38 NR |
387 | dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
388 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
ebc82efa NR |
389 | |
390 | len32 = DIV_ROUND_UP(length1, sizeof(u32)); | |
391 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS); | |
392 | atmel_sha_write(dd, SHA_TPR, dma_addr1); | |
393 | atmel_sha_write(dd, SHA_TCR, len32); | |
394 | ||
395 | len32 = DIV_ROUND_UP(length2, sizeof(u32)); | |
396 | atmel_sha_write(dd, SHA_TNPR, dma_addr2); | |
397 | atmel_sha_write(dd, SHA_TNCR, len32); | |
398 | ||
399 | atmel_sha_write_ctrl(dd, 1); | |
400 | ||
401 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
402 | ctx->digcnt[0] += length1; |
403 | if (ctx->digcnt[0] < length1) | |
404 | ctx->digcnt[1]++; | |
ebc82efa NR |
405 | |
406 | if (final) | |
407 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
408 | ||
409 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
410 | ||
411 | /* Start DMA transfer */ | |
412 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN); | |
413 | ||
414 | return -EINPROGRESS; | |
415 | } | |
416 | ||
d4905b38 NR |
417 | static void atmel_sha_dma_callback(void *data) |
418 | { | |
419 | struct atmel_sha_dev *dd = data; | |
420 | ||
421 | /* dma_lch_in - completed - wait DATRDY */ | |
422 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
423 | } | |
424 | ||
425 | static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
426 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
427 | { | |
428 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
429 | struct dma_async_tx_descriptor *in_desc; | |
430 | struct scatterlist sg[2]; | |
431 | ||
432 | dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", | |
433 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
434 | ||
435 | if (ctx->flags & (SHA_FLAGS_SHA1 | SHA_FLAGS_SHA224 | | |
436 | SHA_FLAGS_SHA256)) { | |
437 | dd->dma_lch_in.dma_conf.src_maxburst = 16; | |
438 | dd->dma_lch_in.dma_conf.dst_maxburst = 16; | |
439 | } else { | |
440 | dd->dma_lch_in.dma_conf.src_maxburst = 32; | |
441 | dd->dma_lch_in.dma_conf.dst_maxburst = 32; | |
442 | } | |
443 | ||
444 | dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); | |
445 | ||
446 | if (length2) { | |
447 | sg_init_table(sg, 2); | |
448 | sg_dma_address(&sg[0]) = dma_addr1; | |
449 | sg_dma_len(&sg[0]) = length1; | |
450 | sg_dma_address(&sg[1]) = dma_addr2; | |
451 | sg_dma_len(&sg[1]) = length2; | |
452 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2, | |
453 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
454 | } else { | |
455 | sg_init_table(sg, 1); | |
456 | sg_dma_address(&sg[0]) = dma_addr1; | |
457 | sg_dma_len(&sg[0]) = length1; | |
458 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1, | |
459 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
460 | } | |
461 | if (!in_desc) | |
462 | return -EINVAL; | |
463 | ||
464 | in_desc->callback = atmel_sha_dma_callback; | |
465 | in_desc->callback_param = dd; | |
466 | ||
467 | atmel_sha_write_ctrl(dd, 1); | |
468 | ||
469 | /* should be non-zero before next lines to disable clocks later */ | |
470 | ctx->digcnt[0] += length1; | |
471 | if (ctx->digcnt[0] < length1) | |
472 | ctx->digcnt[1]++; | |
473 | ||
474 | if (final) | |
475 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
476 | ||
477 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
478 | ||
479 | /* Start DMA transfer */ | |
480 | dmaengine_submit(in_desc); | |
481 | dma_async_issue_pending(dd->dma_lch_in.chan); | |
482 | ||
483 | return -EINPROGRESS; | |
484 | } | |
485 | ||
486 | static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
487 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
488 | { | |
489 | if (dd->caps.has_dma) | |
490 | return atmel_sha_xmit_dma(dd, dma_addr1, length1, | |
491 | dma_addr2, length2, final); | |
492 | else | |
493 | return atmel_sha_xmit_pdc(dd, dma_addr1, length1, | |
494 | dma_addr2, length2, final); | |
495 | } | |
496 | ||
ebc82efa NR |
497 | static int atmel_sha_update_cpu(struct atmel_sha_dev *dd) |
498 | { | |
499 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
500 | int bufcnt; | |
501 | ||
502 | atmel_sha_append_sg(ctx); | |
503 | atmel_sha_fill_padding(ctx, 0); | |
ebc82efa NR |
504 | bufcnt = ctx->bufcnt; |
505 | ctx->bufcnt = 0; | |
506 | ||
507 | return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1); | |
508 | } | |
509 | ||
510 | static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd, | |
511 | struct atmel_sha_reqctx *ctx, | |
512 | size_t length, int final) | |
513 | { | |
514 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 515 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
516 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
517 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen + | |
d4905b38 | 518 | ctx->block_size); |
ebc82efa NR |
519 | return -EINVAL; |
520 | } | |
521 | ||
522 | ctx->flags &= ~SHA_FLAGS_SG; | |
523 | ||
524 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 525 | return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final); |
ebc82efa NR |
526 | } |
527 | ||
528 | static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd) | |
529 | { | |
530 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
531 | unsigned int final; | |
532 | size_t count; | |
533 | ||
534 | atmel_sha_append_sg(ctx); | |
535 | ||
536 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
537 | ||
d4905b38 NR |
538 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n", |
539 | ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final); | |
ebc82efa NR |
540 | |
541 | if (final) | |
542 | atmel_sha_fill_padding(ctx, 0); | |
543 | ||
0099286b | 544 | if (final || (ctx->bufcnt == ctx->buflen)) { |
ebc82efa NR |
545 | count = ctx->bufcnt; |
546 | ctx->bufcnt = 0; | |
547 | return atmel_sha_xmit_dma_map(dd, ctx, count, final); | |
548 | } | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
553 | static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd) | |
554 | { | |
555 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
556 | unsigned int length, final, tail; | |
557 | struct scatterlist *sg; | |
558 | unsigned int count; | |
559 | ||
560 | if (!ctx->total) | |
561 | return 0; | |
562 | ||
563 | if (ctx->bufcnt || ctx->offset) | |
564 | return atmel_sha_update_dma_slow(dd); | |
565 | ||
d4905b38 NR |
566 | dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n", |
567 | ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total); | |
ebc82efa NR |
568 | |
569 | sg = ctx->sg; | |
570 | ||
571 | if (!IS_ALIGNED(sg->offset, sizeof(u32))) | |
572 | return atmel_sha_update_dma_slow(dd); | |
573 | ||
d4905b38 NR |
574 | if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size)) |
575 | /* size is not ctx->block_size aligned */ | |
ebc82efa NR |
576 | return atmel_sha_update_dma_slow(dd); |
577 | ||
578 | length = min(ctx->total, sg->length); | |
579 | ||
580 | if (sg_is_last(sg)) { | |
581 | if (!(ctx->flags & SHA_FLAGS_FINUP)) { | |
d4905b38 NR |
582 | /* not last sg must be ctx->block_size aligned */ |
583 | tail = length & (ctx->block_size - 1); | |
ebc82efa | 584 | length -= tail; |
ebc82efa NR |
585 | } |
586 | } | |
587 | ||
588 | ctx->total -= length; | |
589 | ctx->offset = length; /* offset where to start slow */ | |
590 | ||
591 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
592 | ||
593 | /* Add padding */ | |
594 | if (final) { | |
d4905b38 | 595 | tail = length & (ctx->block_size - 1); |
ebc82efa NR |
596 | length -= tail; |
597 | ctx->total += tail; | |
598 | ctx->offset = length; /* offset where to start slow */ | |
599 | ||
600 | sg = ctx->sg; | |
601 | atmel_sha_append_sg(ctx); | |
602 | ||
603 | atmel_sha_fill_padding(ctx, length); | |
604 | ||
605 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 606 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
607 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
608 | dev_err(dd->dev, "dma %u bytes error\n", | |
d4905b38 | 609 | ctx->buflen + ctx->block_size); |
ebc82efa NR |
610 | return -EINVAL; |
611 | } | |
612 | ||
613 | if (length == 0) { | |
614 | ctx->flags &= ~SHA_FLAGS_SG; | |
615 | count = ctx->bufcnt; | |
616 | ctx->bufcnt = 0; | |
d4905b38 | 617 | return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0, |
ebc82efa NR |
618 | 0, final); |
619 | } else { | |
620 | ctx->sg = sg; | |
621 | if (!dma_map_sg(dd->dev, ctx->sg, 1, | |
622 | DMA_TO_DEVICE)) { | |
623 | dev_err(dd->dev, "dma_map_sg error\n"); | |
624 | return -EINVAL; | |
625 | } | |
626 | ||
627 | ctx->flags |= SHA_FLAGS_SG; | |
628 | ||
629 | count = ctx->bufcnt; | |
630 | ctx->bufcnt = 0; | |
d4905b38 | 631 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), |
ebc82efa NR |
632 | length, ctx->dma_addr, count, final); |
633 | } | |
634 | } | |
635 | ||
636 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
637 | dev_err(dd->dev, "dma_map_sg error\n"); | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
641 | ctx->flags |= SHA_FLAGS_SG; | |
642 | ||
643 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 644 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0, |
ebc82efa NR |
645 | 0, final); |
646 | } | |
647 | ||
648 | static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd) | |
649 | { | |
650 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
651 | ||
652 | if (ctx->flags & SHA_FLAGS_SG) { | |
653 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); | |
654 | if (ctx->sg->length == ctx->offset) { | |
655 | ctx->sg = sg_next(ctx->sg); | |
656 | if (ctx->sg) | |
657 | ctx->offset = 0; | |
658 | } | |
d4905b38 | 659 | if (ctx->flags & SHA_FLAGS_PAD) { |
ebc82efa | 660 | dma_unmap_single(dd->dev, ctx->dma_addr, |
d4905b38 NR |
661 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
662 | } | |
ebc82efa NR |
663 | } else { |
664 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen + | |
d4905b38 | 665 | ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
666 | } |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static int atmel_sha_update_req(struct atmel_sha_dev *dd) | |
672 | { | |
673 | struct ahash_request *req = dd->req; | |
674 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
675 | int err; | |
676 | ||
d4905b38 NR |
677 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n", |
678 | ctx->total, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
679 | |
680 | if (ctx->flags & SHA_FLAGS_CPU) | |
681 | err = atmel_sha_update_cpu(dd); | |
682 | else | |
683 | err = atmel_sha_update_dma_start(dd); | |
684 | ||
685 | /* wait for dma completion before can take more data */ | |
d4905b38 NR |
686 | dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n", |
687 | err, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
688 | |
689 | return err; | |
690 | } | |
691 | ||
692 | static int atmel_sha_final_req(struct atmel_sha_dev *dd) | |
693 | { | |
694 | struct ahash_request *req = dd->req; | |
695 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
696 | int err = 0; | |
697 | int count; | |
698 | ||
699 | if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) { | |
700 | atmel_sha_fill_padding(ctx, 0); | |
701 | count = ctx->bufcnt; | |
702 | ctx->bufcnt = 0; | |
703 | err = atmel_sha_xmit_dma_map(dd, ctx, count, 1); | |
704 | } | |
705 | /* faster to handle last block with cpu */ | |
706 | else { | |
707 | atmel_sha_fill_padding(ctx, 0); | |
708 | count = ctx->bufcnt; | |
709 | ctx->bufcnt = 0; | |
710 | err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1); | |
711 | } | |
712 | ||
713 | dev_dbg(dd->dev, "final_req: err: %d\n", err); | |
714 | ||
715 | return err; | |
716 | } | |
717 | ||
718 | static void atmel_sha_copy_hash(struct ahash_request *req) | |
719 | { | |
720 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
721 | u32 *hash = (u32 *)ctx->digest; | |
722 | int i; | |
723 | ||
d4905b38 | 724 | if (ctx->flags & SHA_FLAGS_SHA1) |
ebc82efa NR |
725 | for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) |
726 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
d4905b38 NR |
727 | else if (ctx->flags & SHA_FLAGS_SHA224) |
728 | for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++) | |
729 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
730 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa NR |
731 | for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++) |
732 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
d4905b38 NR |
733 | else if (ctx->flags & SHA_FLAGS_SHA384) |
734 | for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++) | |
735 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
736 | else | |
737 | for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++) | |
738 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
ebc82efa NR |
739 | } |
740 | ||
741 | static void atmel_sha_copy_ready_hash(struct ahash_request *req) | |
742 | { | |
743 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
744 | ||
745 | if (!req->result) | |
746 | return; | |
747 | ||
d4905b38 | 748 | if (ctx->flags & SHA_FLAGS_SHA1) |
ebc82efa | 749 | memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE); |
d4905b38 NR |
750 | else if (ctx->flags & SHA_FLAGS_SHA224) |
751 | memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE); | |
752 | else if (ctx->flags & SHA_FLAGS_SHA256) | |
ebc82efa | 753 | memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE); |
d4905b38 NR |
754 | else if (ctx->flags & SHA_FLAGS_SHA384) |
755 | memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE); | |
756 | else | |
757 | memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE); | |
ebc82efa NR |
758 | } |
759 | ||
760 | static int atmel_sha_finish(struct ahash_request *req) | |
761 | { | |
762 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
763 | struct atmel_sha_dev *dd = ctx->dd; | |
764 | int err = 0; | |
765 | ||
d4905b38 | 766 | if (ctx->digcnt[0] || ctx->digcnt[1]) |
ebc82efa NR |
767 | atmel_sha_copy_ready_hash(req); |
768 | ||
d4905b38 NR |
769 | dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1], |
770 | ctx->digcnt[0], ctx->bufcnt); | |
ebc82efa NR |
771 | |
772 | return err; | |
773 | } | |
774 | ||
775 | static void atmel_sha_finish_req(struct ahash_request *req, int err) | |
776 | { | |
777 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
778 | struct atmel_sha_dev *dd = ctx->dd; | |
779 | ||
780 | if (!err) { | |
781 | atmel_sha_copy_hash(req); | |
782 | if (SHA_FLAGS_FINAL & dd->flags) | |
783 | err = atmel_sha_finish(req); | |
784 | } else { | |
785 | ctx->flags |= SHA_FLAGS_ERROR; | |
786 | } | |
787 | ||
788 | /* atomic operation is not needed here */ | |
789 | dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU | | |
790 | SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY); | |
791 | ||
792 | clk_disable_unprepare(dd->iclk); | |
793 | ||
794 | if (req->base.complete) | |
795 | req->base.complete(&req->base, err); | |
796 | ||
797 | /* handle new request */ | |
798 | tasklet_schedule(&dd->done_task); | |
799 | } | |
800 | ||
801 | static int atmel_sha_hw_init(struct atmel_sha_dev *dd) | |
802 | { | |
803 | clk_prepare_enable(dd->iclk); | |
804 | ||
d4905b38 | 805 | if (!(SHA_FLAGS_INIT & dd->flags)) { |
ebc82efa | 806 | atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST); |
ebc82efa NR |
807 | dd->flags |= SHA_FLAGS_INIT; |
808 | dd->err = 0; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
d4905b38 NR |
814 | static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd) |
815 | { | |
816 | return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff; | |
817 | } | |
818 | ||
819 | static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd) | |
820 | { | |
821 | atmel_sha_hw_init(dd); | |
822 | ||
823 | dd->hw_version = atmel_sha_get_version(dd); | |
824 | ||
825 | dev_info(dd->dev, | |
826 | "version: 0x%x\n", dd->hw_version); | |
827 | ||
828 | clk_disable_unprepare(dd->iclk); | |
829 | } | |
830 | ||
ebc82efa NR |
831 | static int atmel_sha_handle_queue(struct atmel_sha_dev *dd, |
832 | struct ahash_request *req) | |
833 | { | |
834 | struct crypto_async_request *async_req, *backlog; | |
835 | struct atmel_sha_reqctx *ctx; | |
836 | unsigned long flags; | |
837 | int err = 0, ret = 0; | |
838 | ||
839 | spin_lock_irqsave(&dd->lock, flags); | |
840 | if (req) | |
841 | ret = ahash_enqueue_request(&dd->queue, req); | |
842 | ||
843 | if (SHA_FLAGS_BUSY & dd->flags) { | |
844 | spin_unlock_irqrestore(&dd->lock, flags); | |
845 | return ret; | |
846 | } | |
847 | ||
848 | backlog = crypto_get_backlog(&dd->queue); | |
849 | async_req = crypto_dequeue_request(&dd->queue); | |
850 | if (async_req) | |
851 | dd->flags |= SHA_FLAGS_BUSY; | |
852 | ||
853 | spin_unlock_irqrestore(&dd->lock, flags); | |
854 | ||
855 | if (!async_req) | |
856 | return ret; | |
857 | ||
858 | if (backlog) | |
859 | backlog->complete(backlog, -EINPROGRESS); | |
860 | ||
861 | req = ahash_request_cast(async_req); | |
862 | dd->req = req; | |
863 | ctx = ahash_request_ctx(req); | |
864 | ||
865 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", | |
866 | ctx->op, req->nbytes); | |
867 | ||
868 | err = atmel_sha_hw_init(dd); | |
869 | ||
870 | if (err) | |
871 | goto err1; | |
872 | ||
873 | if (ctx->op == SHA_OP_UPDATE) { | |
874 | err = atmel_sha_update_req(dd); | |
d4905b38 | 875 | if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP)) |
ebc82efa NR |
876 | /* no final() after finup() */ |
877 | err = atmel_sha_final_req(dd); | |
ebc82efa NR |
878 | } else if (ctx->op == SHA_OP_FINAL) { |
879 | err = atmel_sha_final_req(dd); | |
880 | } | |
881 | ||
882 | err1: | |
883 | if (err != -EINPROGRESS) | |
884 | /* done_task will not finish it, so do it here */ | |
885 | atmel_sha_finish_req(req, err); | |
886 | ||
887 | dev_dbg(dd->dev, "exit, err: %d\n", err); | |
888 | ||
889 | return ret; | |
890 | } | |
891 | ||
892 | static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op) | |
893 | { | |
894 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
895 | struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
896 | struct atmel_sha_dev *dd = tctx->dd; | |
897 | ||
898 | ctx->op = op; | |
899 | ||
900 | return atmel_sha_handle_queue(dd, req); | |
901 | } | |
902 | ||
903 | static int atmel_sha_update(struct ahash_request *req) | |
904 | { | |
905 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
906 | ||
907 | if (!req->nbytes) | |
908 | return 0; | |
909 | ||
910 | ctx->total = req->nbytes; | |
911 | ctx->sg = req->src; | |
912 | ctx->offset = 0; | |
913 | ||
914 | if (ctx->flags & SHA_FLAGS_FINUP) { | |
915 | if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD) | |
916 | /* faster to use CPU for short transfers */ | |
917 | ctx->flags |= SHA_FLAGS_CPU; | |
918 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { | |
919 | atmel_sha_append_sg(ctx); | |
920 | return 0; | |
921 | } | |
922 | return atmel_sha_enqueue(req, SHA_OP_UPDATE); | |
923 | } | |
924 | ||
925 | static int atmel_sha_final(struct ahash_request *req) | |
926 | { | |
927 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
928 | struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
929 | struct atmel_sha_dev *dd = tctx->dd; | |
930 | ||
931 | int err = 0; | |
932 | ||
933 | ctx->flags |= SHA_FLAGS_FINUP; | |
934 | ||
935 | if (ctx->flags & SHA_FLAGS_ERROR) | |
936 | return 0; /* uncompleted hash is not needed */ | |
937 | ||
938 | if (ctx->bufcnt) { | |
939 | return atmel_sha_enqueue(req, SHA_OP_FINAL); | |
940 | } else if (!(ctx->flags & SHA_FLAGS_PAD)) { /* add padding */ | |
941 | err = atmel_sha_hw_init(dd); | |
942 | if (err) | |
943 | goto err1; | |
944 | ||
945 | dd->flags |= SHA_FLAGS_BUSY; | |
946 | err = atmel_sha_final_req(dd); | |
947 | } else { | |
948 | /* copy ready hash (+ finalize hmac) */ | |
949 | return atmel_sha_finish(req); | |
950 | } | |
951 | ||
952 | err1: | |
953 | if (err != -EINPROGRESS) | |
954 | /* done_task will not finish it, so do it here */ | |
955 | atmel_sha_finish_req(req, err); | |
956 | ||
957 | return err; | |
958 | } | |
959 | ||
960 | static int atmel_sha_finup(struct ahash_request *req) | |
961 | { | |
962 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
963 | int err1, err2; | |
964 | ||
965 | ctx->flags |= SHA_FLAGS_FINUP; | |
966 | ||
967 | err1 = atmel_sha_update(req); | |
968 | if (err1 == -EINPROGRESS || err1 == -EBUSY) | |
969 | return err1; | |
970 | ||
971 | /* | |
972 | * final() has to be always called to cleanup resources | |
973 | * even if udpate() failed, except EINPROGRESS | |
974 | */ | |
975 | err2 = atmel_sha_final(req); | |
976 | ||
977 | return err1 ?: err2; | |
978 | } | |
979 | ||
980 | static int atmel_sha_digest(struct ahash_request *req) | |
981 | { | |
982 | return atmel_sha_init(req) ?: atmel_sha_finup(req); | |
983 | } | |
984 | ||
be95f0fa | 985 | static int atmel_sha_cra_init(struct crypto_tfm *tfm) |
ebc82efa | 986 | { |
ebc82efa NR |
987 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
988 | sizeof(struct atmel_sha_reqctx) + | |
d4905b38 | 989 | SHA_BUFFER_LEN + SHA512_BLOCK_SIZE); |
ebc82efa NR |
990 | |
991 | return 0; | |
992 | } | |
993 | ||
d4905b38 | 994 | static struct ahash_alg sha_1_256_algs[] = { |
ebc82efa NR |
995 | { |
996 | .init = atmel_sha_init, | |
997 | .update = atmel_sha_update, | |
998 | .final = atmel_sha_final, | |
999 | .finup = atmel_sha_finup, | |
1000 | .digest = atmel_sha_digest, | |
1001 | .halg = { | |
1002 | .digestsize = SHA1_DIGEST_SIZE, | |
1003 | .base = { | |
1004 | .cra_name = "sha1", | |
1005 | .cra_driver_name = "atmel-sha1", | |
1006 | .cra_priority = 100, | |
be95f0fa | 1007 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1008 | .cra_blocksize = SHA1_BLOCK_SIZE, |
1009 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1010 | .cra_alignmask = 0, | |
1011 | .cra_module = THIS_MODULE, | |
1012 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1013 | } |
1014 | } | |
1015 | }, | |
1016 | { | |
1017 | .init = atmel_sha_init, | |
1018 | .update = atmel_sha_update, | |
1019 | .final = atmel_sha_final, | |
1020 | .finup = atmel_sha_finup, | |
1021 | .digest = atmel_sha_digest, | |
1022 | .halg = { | |
1023 | .digestsize = SHA256_DIGEST_SIZE, | |
1024 | .base = { | |
1025 | .cra_name = "sha256", | |
1026 | .cra_driver_name = "atmel-sha256", | |
1027 | .cra_priority = 100, | |
be95f0fa | 1028 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1029 | .cra_blocksize = SHA256_BLOCK_SIZE, |
1030 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1031 | .cra_alignmask = 0, | |
1032 | .cra_module = THIS_MODULE, | |
1033 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1034 | } |
1035 | } | |
1036 | }, | |
1037 | }; | |
1038 | ||
d4905b38 NR |
1039 | static struct ahash_alg sha_224_alg = { |
1040 | .init = atmel_sha_init, | |
1041 | .update = atmel_sha_update, | |
1042 | .final = atmel_sha_final, | |
1043 | .finup = atmel_sha_finup, | |
1044 | .digest = atmel_sha_digest, | |
1045 | .halg = { | |
1046 | .digestsize = SHA224_DIGEST_SIZE, | |
1047 | .base = { | |
1048 | .cra_name = "sha224", | |
1049 | .cra_driver_name = "atmel-sha224", | |
1050 | .cra_priority = 100, | |
be95f0fa | 1051 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1052 | .cra_blocksize = SHA224_BLOCK_SIZE, |
1053 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1054 | .cra_alignmask = 0, | |
1055 | .cra_module = THIS_MODULE, | |
1056 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1057 | } |
1058 | } | |
1059 | }; | |
1060 | ||
1061 | static struct ahash_alg sha_384_512_algs[] = { | |
1062 | { | |
1063 | .init = atmel_sha_init, | |
1064 | .update = atmel_sha_update, | |
1065 | .final = atmel_sha_final, | |
1066 | .finup = atmel_sha_finup, | |
1067 | .digest = atmel_sha_digest, | |
1068 | .halg = { | |
1069 | .digestsize = SHA384_DIGEST_SIZE, | |
1070 | .base = { | |
1071 | .cra_name = "sha384", | |
1072 | .cra_driver_name = "atmel-sha384", | |
1073 | .cra_priority = 100, | |
be95f0fa | 1074 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1075 | .cra_blocksize = SHA384_BLOCK_SIZE, |
1076 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1077 | .cra_alignmask = 0x3, | |
1078 | .cra_module = THIS_MODULE, | |
1079 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1080 | } |
1081 | } | |
1082 | }, | |
1083 | { | |
1084 | .init = atmel_sha_init, | |
1085 | .update = atmel_sha_update, | |
1086 | .final = atmel_sha_final, | |
1087 | .finup = atmel_sha_finup, | |
1088 | .digest = atmel_sha_digest, | |
1089 | .halg = { | |
1090 | .digestsize = SHA512_DIGEST_SIZE, | |
1091 | .base = { | |
1092 | .cra_name = "sha512", | |
1093 | .cra_driver_name = "atmel-sha512", | |
1094 | .cra_priority = 100, | |
be95f0fa | 1095 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1096 | .cra_blocksize = SHA512_BLOCK_SIZE, |
1097 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1098 | .cra_alignmask = 0x3, | |
1099 | .cra_module = THIS_MODULE, | |
1100 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1101 | } |
1102 | } | |
1103 | }, | |
1104 | }; | |
1105 | ||
ebc82efa NR |
1106 | static void atmel_sha_done_task(unsigned long data) |
1107 | { | |
1108 | struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; | |
1109 | int err = 0; | |
1110 | ||
1111 | if (!(SHA_FLAGS_BUSY & dd->flags)) { | |
1112 | atmel_sha_handle_queue(dd, NULL); | |
1113 | return; | |
1114 | } | |
1115 | ||
1116 | if (SHA_FLAGS_CPU & dd->flags) { | |
1117 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1118 | dd->flags &= ~SHA_FLAGS_OUTPUT_READY; | |
1119 | goto finish; | |
1120 | } | |
1121 | } else if (SHA_FLAGS_DMA_READY & dd->flags) { | |
1122 | if (SHA_FLAGS_DMA_ACTIVE & dd->flags) { | |
1123 | dd->flags &= ~SHA_FLAGS_DMA_ACTIVE; | |
1124 | atmel_sha_update_dma_stop(dd); | |
1125 | if (dd->err) { | |
1126 | err = dd->err; | |
1127 | goto finish; | |
1128 | } | |
1129 | } | |
1130 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1131 | /* hash or semi-hash ready */ | |
1132 | dd->flags &= ~(SHA_FLAGS_DMA_READY | | |
1133 | SHA_FLAGS_OUTPUT_READY); | |
1134 | err = atmel_sha_update_dma_start(dd); | |
1135 | if (err != -EINPROGRESS) | |
1136 | goto finish; | |
1137 | } | |
1138 | } | |
1139 | return; | |
1140 | ||
1141 | finish: | |
1142 | /* finish curent request */ | |
1143 | atmel_sha_finish_req(dd->req, err); | |
1144 | } | |
1145 | ||
1146 | static irqreturn_t atmel_sha_irq(int irq, void *dev_id) | |
1147 | { | |
1148 | struct atmel_sha_dev *sha_dd = dev_id; | |
1149 | u32 reg; | |
1150 | ||
1151 | reg = atmel_sha_read(sha_dd, SHA_ISR); | |
1152 | if (reg & atmel_sha_read(sha_dd, SHA_IMR)) { | |
1153 | atmel_sha_write(sha_dd, SHA_IDR, reg); | |
1154 | if (SHA_FLAGS_BUSY & sha_dd->flags) { | |
1155 | sha_dd->flags |= SHA_FLAGS_OUTPUT_READY; | |
1156 | if (!(SHA_FLAGS_CPU & sha_dd->flags)) | |
1157 | sha_dd->flags |= SHA_FLAGS_DMA_READY; | |
1158 | tasklet_schedule(&sha_dd->done_task); | |
1159 | } else { | |
1160 | dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n"); | |
1161 | } | |
1162 | return IRQ_HANDLED; | |
1163 | } | |
1164 | ||
1165 | return IRQ_NONE; | |
1166 | } | |
1167 | ||
1168 | static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd) | |
1169 | { | |
1170 | int i; | |
1171 | ||
d4905b38 NR |
1172 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) |
1173 | crypto_unregister_ahash(&sha_1_256_algs[i]); | |
1174 | ||
1175 | if (dd->caps.has_sha224) | |
1176 | crypto_unregister_ahash(&sha_224_alg); | |
1177 | ||
1178 | if (dd->caps.has_sha_384_512) { | |
1179 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) | |
1180 | crypto_unregister_ahash(&sha_384_512_algs[i]); | |
1181 | } | |
ebc82efa NR |
1182 | } |
1183 | ||
1184 | static int atmel_sha_register_algs(struct atmel_sha_dev *dd) | |
1185 | { | |
1186 | int err, i, j; | |
1187 | ||
d4905b38 NR |
1188 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) { |
1189 | err = crypto_register_ahash(&sha_1_256_algs[i]); | |
ebc82efa | 1190 | if (err) |
d4905b38 NR |
1191 | goto err_sha_1_256_algs; |
1192 | } | |
1193 | ||
1194 | if (dd->caps.has_sha224) { | |
1195 | err = crypto_register_ahash(&sha_224_alg); | |
1196 | if (err) | |
1197 | goto err_sha_224_algs; | |
1198 | } | |
1199 | ||
1200 | if (dd->caps.has_sha_384_512) { | |
1201 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) { | |
1202 | err = crypto_register_ahash(&sha_384_512_algs[i]); | |
1203 | if (err) | |
1204 | goto err_sha_384_512_algs; | |
1205 | } | |
ebc82efa NR |
1206 | } |
1207 | ||
1208 | return 0; | |
1209 | ||
d4905b38 NR |
1210 | err_sha_384_512_algs: |
1211 | for (j = 0; j < i; j++) | |
1212 | crypto_unregister_ahash(&sha_384_512_algs[j]); | |
1213 | crypto_unregister_ahash(&sha_224_alg); | |
1214 | err_sha_224_algs: | |
1215 | i = ARRAY_SIZE(sha_1_256_algs); | |
1216 | err_sha_1_256_algs: | |
ebc82efa | 1217 | for (j = 0; j < i; j++) |
d4905b38 | 1218 | crypto_unregister_ahash(&sha_1_256_algs[j]); |
ebc82efa NR |
1219 | |
1220 | return err; | |
1221 | } | |
1222 | ||
d4905b38 NR |
1223 | static bool atmel_sha_filter(struct dma_chan *chan, void *slave) |
1224 | { | |
1225 | struct at_dma_slave *sl = slave; | |
1226 | ||
1227 | if (sl && sl->dma_dev == chan->device->dev) { | |
1228 | chan->private = sl; | |
1229 | return true; | |
1230 | } else { | |
1231 | return false; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | static int atmel_sha_dma_init(struct atmel_sha_dev *dd, | |
1236 | struct crypto_platform_data *pdata) | |
1237 | { | |
1238 | int err = -ENOMEM; | |
1239 | dma_cap_mask_t mask_in; | |
1240 | ||
abfe7ae4 NF |
1241 | /* Try to grab DMA channel */ |
1242 | dma_cap_zero(mask_in); | |
1243 | dma_cap_set(DMA_SLAVE, mask_in); | |
d4905b38 | 1244 | |
abfe7ae4 NF |
1245 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in, |
1246 | atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); | |
1247 | if (!dd->dma_lch_in.chan) { | |
1248 | dev_warn(dd->dev, "no DMA channel available\n"); | |
1249 | return err; | |
d4905b38 NR |
1250 | } |
1251 | ||
abfe7ae4 NF |
1252 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; |
1253 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | |
1254 | SHA_REG_DIN(0); | |
1255 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | |
1256 | dd->dma_lch_in.dma_conf.src_addr_width = | |
1257 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1258 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | |
1259 | dd->dma_lch_in.dma_conf.dst_addr_width = | |
1260 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1261 | dd->dma_lch_in.dma_conf.device_fc = false; | |
1262 | ||
1263 | return 0; | |
d4905b38 NR |
1264 | } |
1265 | ||
1266 | static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) | |
1267 | { | |
1268 | dma_release_channel(dd->dma_lch_in.chan); | |
1269 | } | |
1270 | ||
1271 | static void atmel_sha_get_cap(struct atmel_sha_dev *dd) | |
1272 | { | |
1273 | ||
1274 | dd->caps.has_dma = 0; | |
1275 | dd->caps.has_dualbuff = 0; | |
1276 | dd->caps.has_sha224 = 0; | |
1277 | dd->caps.has_sha_384_512 = 0; | |
1278 | ||
1279 | /* keep only major version number */ | |
1280 | switch (dd->hw_version & 0xff0) { | |
141824d0 LZ |
1281 | case 0x420: |
1282 | dd->caps.has_dma = 1; | |
1283 | dd->caps.has_dualbuff = 1; | |
1284 | dd->caps.has_sha224 = 1; | |
1285 | dd->caps.has_sha_384_512 = 1; | |
1286 | break; | |
d4905b38 NR |
1287 | case 0x410: |
1288 | dd->caps.has_dma = 1; | |
1289 | dd->caps.has_dualbuff = 1; | |
1290 | dd->caps.has_sha224 = 1; | |
1291 | dd->caps.has_sha_384_512 = 1; | |
1292 | break; | |
1293 | case 0x400: | |
1294 | dd->caps.has_dma = 1; | |
1295 | dd->caps.has_dualbuff = 1; | |
1296 | dd->caps.has_sha224 = 1; | |
1297 | break; | |
1298 | case 0x320: | |
1299 | break; | |
1300 | default: | |
1301 | dev_warn(dd->dev, | |
1302 | "Unmanaged sha version, set minimum capabilities\n"); | |
1303 | break; | |
1304 | } | |
1305 | } | |
1306 | ||
abfe7ae4 NF |
1307 | #if defined(CONFIG_OF) |
1308 | static const struct of_device_id atmel_sha_dt_ids[] = { | |
1309 | { .compatible = "atmel,at91sam9g46-sha" }, | |
1310 | { /* sentinel */ } | |
1311 | }; | |
1312 | ||
1313 | MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids); | |
1314 | ||
1315 | static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev) | |
1316 | { | |
1317 | struct device_node *np = pdev->dev.of_node; | |
1318 | struct crypto_platform_data *pdata; | |
1319 | ||
1320 | if (!np) { | |
1321 | dev_err(&pdev->dev, "device node not found\n"); | |
1322 | return ERR_PTR(-EINVAL); | |
1323 | } | |
1324 | ||
1325 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1326 | if (!pdata) { | |
1327 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
1328 | return ERR_PTR(-ENOMEM); | |
1329 | } | |
1330 | ||
1331 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | |
1332 | sizeof(*(pdata->dma_slave)), | |
1333 | GFP_KERNEL); | |
1334 | if (!pdata->dma_slave) { | |
1335 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | |
abfe7ae4 NF |
1336 | return ERR_PTR(-ENOMEM); |
1337 | } | |
1338 | ||
1339 | return pdata; | |
1340 | } | |
1341 | #else /* CONFIG_OF */ | |
1342 | static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev) | |
1343 | { | |
1344 | return ERR_PTR(-EINVAL); | |
1345 | } | |
1346 | #endif | |
1347 | ||
49cfe4db | 1348 | static int atmel_sha_probe(struct platform_device *pdev) |
ebc82efa NR |
1349 | { |
1350 | struct atmel_sha_dev *sha_dd; | |
d4905b38 | 1351 | struct crypto_platform_data *pdata; |
ebc82efa NR |
1352 | struct device *dev = &pdev->dev; |
1353 | struct resource *sha_res; | |
1354 | unsigned long sha_phys_size; | |
1355 | int err; | |
1356 | ||
593901aa PG |
1357 | sha_dd = devm_kzalloc(&pdev->dev, sizeof(struct atmel_sha_dev), |
1358 | GFP_KERNEL); | |
ebc82efa NR |
1359 | if (sha_dd == NULL) { |
1360 | dev_err(dev, "unable to alloc data struct.\n"); | |
1361 | err = -ENOMEM; | |
1362 | goto sha_dd_err; | |
1363 | } | |
1364 | ||
1365 | sha_dd->dev = dev; | |
1366 | ||
1367 | platform_set_drvdata(pdev, sha_dd); | |
1368 | ||
1369 | INIT_LIST_HEAD(&sha_dd->list); | |
1370 | ||
1371 | tasklet_init(&sha_dd->done_task, atmel_sha_done_task, | |
1372 | (unsigned long)sha_dd); | |
1373 | ||
1374 | crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH); | |
1375 | ||
1376 | sha_dd->irq = -1; | |
1377 | ||
1378 | /* Get the base address */ | |
1379 | sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1380 | if (!sha_res) { | |
1381 | dev_err(dev, "no MEM resource info\n"); | |
1382 | err = -ENODEV; | |
1383 | goto res_err; | |
1384 | } | |
1385 | sha_dd->phys_base = sha_res->start; | |
1386 | sha_phys_size = resource_size(sha_res); | |
1387 | ||
1388 | /* Get the IRQ */ | |
1389 | sha_dd->irq = platform_get_irq(pdev, 0); | |
1390 | if (sha_dd->irq < 0) { | |
1391 | dev_err(dev, "no IRQ resource info\n"); | |
1392 | err = sha_dd->irq; | |
1393 | goto res_err; | |
1394 | } | |
1395 | ||
1396 | err = request_irq(sha_dd->irq, atmel_sha_irq, IRQF_SHARED, "atmel-sha", | |
1397 | sha_dd); | |
1398 | if (err) { | |
1399 | dev_err(dev, "unable to request sha irq.\n"); | |
1400 | goto res_err; | |
1401 | } | |
1402 | ||
1403 | /* Initializing the clock */ | |
d4905b38 | 1404 | sha_dd->iclk = clk_get(&pdev->dev, "sha_clk"); |
ebc82efa | 1405 | if (IS_ERR(sha_dd->iclk)) { |
be208356 | 1406 | dev_err(dev, "clock initialization failed.\n"); |
ebc82efa NR |
1407 | err = PTR_ERR(sha_dd->iclk); |
1408 | goto clk_err; | |
1409 | } | |
1410 | ||
1411 | sha_dd->io_base = ioremap(sha_dd->phys_base, sha_phys_size); | |
1412 | if (!sha_dd->io_base) { | |
1413 | dev_err(dev, "can't ioremap\n"); | |
1414 | err = -ENOMEM; | |
1415 | goto sha_io_err; | |
1416 | } | |
1417 | ||
d4905b38 NR |
1418 | atmel_sha_hw_version_init(sha_dd); |
1419 | ||
1420 | atmel_sha_get_cap(sha_dd); | |
1421 | ||
1422 | if (sha_dd->caps.has_dma) { | |
1423 | pdata = pdev->dev.platform_data; | |
1424 | if (!pdata) { | |
abfe7ae4 NF |
1425 | pdata = atmel_sha_of_init(pdev); |
1426 | if (IS_ERR(pdata)) { | |
1427 | dev_err(&pdev->dev, "platform data not available\n"); | |
1428 | err = PTR_ERR(pdata); | |
1429 | goto err_pdata; | |
1430 | } | |
1431 | } | |
1432 | if (!pdata->dma_slave) { | |
d4905b38 NR |
1433 | err = -ENXIO; |
1434 | goto err_pdata; | |
1435 | } | |
1436 | err = atmel_sha_dma_init(sha_dd, pdata); | |
1437 | if (err) | |
1438 | goto err_sha_dma; | |
abfe7ae4 NF |
1439 | |
1440 | dev_info(dev, "using %s for DMA transfers\n", | |
1441 | dma_chan_name(sha_dd->dma_lch_in.chan)); | |
d4905b38 NR |
1442 | } |
1443 | ||
ebc82efa NR |
1444 | spin_lock(&atmel_sha.lock); |
1445 | list_add_tail(&sha_dd->list, &atmel_sha.dev_list); | |
1446 | spin_unlock(&atmel_sha.lock); | |
1447 | ||
1448 | err = atmel_sha_register_algs(sha_dd); | |
1449 | if (err) | |
1450 | goto err_algs; | |
1451 | ||
1ca5b7d9 NF |
1452 | dev_info(dev, "Atmel SHA1/SHA256%s%s\n", |
1453 | sha_dd->caps.has_sha224 ? "/SHA224" : "", | |
1454 | sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : ""); | |
ebc82efa NR |
1455 | |
1456 | return 0; | |
1457 | ||
1458 | err_algs: | |
1459 | spin_lock(&atmel_sha.lock); | |
1460 | list_del(&sha_dd->list); | |
1461 | spin_unlock(&atmel_sha.lock); | |
d4905b38 NR |
1462 | if (sha_dd->caps.has_dma) |
1463 | atmel_sha_dma_cleanup(sha_dd); | |
1464 | err_sha_dma: | |
1465 | err_pdata: | |
ebc82efa NR |
1466 | iounmap(sha_dd->io_base); |
1467 | sha_io_err: | |
1468 | clk_put(sha_dd->iclk); | |
1469 | clk_err: | |
1470 | free_irq(sha_dd->irq, sha_dd); | |
1471 | res_err: | |
1472 | tasklet_kill(&sha_dd->done_task); | |
ebc82efa NR |
1473 | sha_dd_err: |
1474 | dev_err(dev, "initialization failed.\n"); | |
1475 | ||
1476 | return err; | |
1477 | } | |
1478 | ||
49cfe4db | 1479 | static int atmel_sha_remove(struct platform_device *pdev) |
ebc82efa NR |
1480 | { |
1481 | static struct atmel_sha_dev *sha_dd; | |
1482 | ||
1483 | sha_dd = platform_get_drvdata(pdev); | |
1484 | if (!sha_dd) | |
1485 | return -ENODEV; | |
1486 | spin_lock(&atmel_sha.lock); | |
1487 | list_del(&sha_dd->list); | |
1488 | spin_unlock(&atmel_sha.lock); | |
1489 | ||
1490 | atmel_sha_unregister_algs(sha_dd); | |
1491 | ||
1492 | tasklet_kill(&sha_dd->done_task); | |
1493 | ||
d4905b38 NR |
1494 | if (sha_dd->caps.has_dma) |
1495 | atmel_sha_dma_cleanup(sha_dd); | |
1496 | ||
ebc82efa NR |
1497 | iounmap(sha_dd->io_base); |
1498 | ||
1499 | clk_put(sha_dd->iclk); | |
1500 | ||
1501 | if (sha_dd->irq >= 0) | |
1502 | free_irq(sha_dd->irq, sha_dd); | |
1503 | ||
ebc82efa NR |
1504 | return 0; |
1505 | } | |
1506 | ||
1507 | static struct platform_driver atmel_sha_driver = { | |
1508 | .probe = atmel_sha_probe, | |
49cfe4db | 1509 | .remove = atmel_sha_remove, |
ebc82efa NR |
1510 | .driver = { |
1511 | .name = "atmel_sha", | |
abfe7ae4 | 1512 | .of_match_table = of_match_ptr(atmel_sha_dt_ids), |
ebc82efa NR |
1513 | }, |
1514 | }; | |
1515 | ||
1516 | module_platform_driver(atmel_sha_driver); | |
1517 | ||
d4905b38 | 1518 | MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support."); |
ebc82efa NR |
1519 | MODULE_LICENSE("GPL v2"); |
1520 | MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); |