Commit | Line | Data |
---|---|---|
820684cc | 1 | // SPDX-License-Identifier: GPL-2.0 |
bd3c7b5c NR |
2 | /* |
3 | * Cryptographic API. | |
4 | * | |
5 | * Support for ATMEL AES HW acceleration. | |
6 | * | |
7 | * Copyright (c) 2012 Eukréa Electromatique - ATMEL | |
8 | * Author: Nicolas Royer <nicolas@eukrea.com> | |
9 | * | |
bd3c7b5c NR |
10 | * Some ideas are from omap-aes.c driver. |
11 | */ | |
12 | ||
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/hw_random.h> | |
21 | #include <linux/platform_device.h> | |
22 | ||
23 | #include <linux/device.h> | |
bd3c7b5c NR |
24 | #include <linux/init.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/interrupt.h> | |
bd3c7b5c | 27 | #include <linux/irq.h> |
bd3c7b5c NR |
28 | #include <linux/scatterlist.h> |
29 | #include <linux/dma-mapping.h> | |
be943c7d | 30 | #include <linux/of_device.h> |
bd3c7b5c NR |
31 | #include <linux/delay.h> |
32 | #include <linux/crypto.h> | |
bd3c7b5c NR |
33 | #include <crypto/scatterwalk.h> |
34 | #include <crypto/algapi.h> | |
35 | #include <crypto/aes.h> | |
219d51c7 | 36 | #include <crypto/gcm.h> |
d52db518 | 37 | #include <crypto/xts.h> |
d4419548 | 38 | #include <crypto/internal/aead.h> |
cadc4ab8 | 39 | #include <linux/platform_data/crypto-atmel.h> |
be943c7d | 40 | #include <dt-bindings/dma/at91.h> |
bd3c7b5c | 41 | #include "atmel-aes-regs.h" |
89a82ef8 | 42 | #include "atmel-authenc.h" |
bd3c7b5c | 43 | |
88efd9a9 CP |
44 | #define ATMEL_AES_PRIORITY 300 |
45 | ||
bbe628ed CP |
46 | #define ATMEL_AES_BUFFER_ORDER 2 |
47 | #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER) | |
48 | ||
bd3c7b5c NR |
49 | #define CFB8_BLOCK_SIZE 1 |
50 | #define CFB16_BLOCK_SIZE 2 | |
51 | #define CFB32_BLOCK_SIZE 4 | |
52 | #define CFB64_BLOCK_SIZE 8 | |
53 | ||
bbe628ed CP |
54 | #define SIZE_IN_WORDS(x) ((x) >> 2) |
55 | ||
bd3c7b5c | 56 | /* AES flags */ |
d4419548 | 57 | /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */ |
77dacf5f | 58 | #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC |
d4419548 | 59 | #define AES_FLAGS_GTAGEN AES_MR_GTAGEN |
77dacf5f CP |
60 | #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK) |
61 | #define AES_FLAGS_ECB AES_MR_OPMOD_ECB | |
62 | #define AES_FLAGS_CBC AES_MR_OPMOD_CBC | |
63 | #define AES_FLAGS_OFB AES_MR_OPMOD_OFB | |
64 | #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b) | |
65 | #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b) | |
66 | #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b) | |
67 | #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b) | |
68 | #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b) | |
69 | #define AES_FLAGS_CTR AES_MR_OPMOD_CTR | |
d4419548 | 70 | #define AES_FLAGS_GCM AES_MR_OPMOD_GCM |
d52db518 | 71 | #define AES_FLAGS_XTS AES_MR_OPMOD_XTS |
77dacf5f CP |
72 | |
73 | #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \ | |
d4419548 CP |
74 | AES_FLAGS_ENCRYPT | \ |
75 | AES_FLAGS_GTAGEN) | |
77dacf5f | 76 | |
77dacf5f | 77 | #define AES_FLAGS_BUSY BIT(3) |
4537992b | 78 | #define AES_FLAGS_DUMP_REG BIT(4) |
89a82ef8 | 79 | #define AES_FLAGS_OWN_SHA BIT(5) |
77dacf5f | 80 | |
7a373fd7 | 81 | #define AES_FLAGS_PERSISTENT AES_FLAGS_BUSY |
bd3c7b5c | 82 | |
cadc4ab8 | 83 | #define ATMEL_AES_QUEUE_LENGTH 50 |
bd3c7b5c | 84 | |
129f8bb6 | 85 | #define ATMEL_AES_DMA_THRESHOLD 256 |
bd3c7b5c NR |
86 | |
87 | ||
cadc4ab8 | 88 | struct atmel_aes_caps { |
afbac17e CP |
89 | bool has_dualbuff; |
90 | bool has_cfb64; | |
fcac8365 | 91 | bool has_ctr32; |
d4419548 | 92 | bool has_gcm; |
d52db518 | 93 | bool has_xts; |
89a82ef8 | 94 | bool has_authenc; |
afbac17e | 95 | u32 max_burst_size; |
cadc4ab8 NR |
96 | }; |
97 | ||
bd3c7b5c NR |
98 | struct atmel_aes_dev; |
99 | ||
ccbf7298 CP |
100 | |
101 | typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *); | |
102 | ||
103 | ||
104 | struct atmel_aes_base_ctx { | |
afbac17e CP |
105 | struct atmel_aes_dev *dd; |
106 | atmel_aes_fn_t start; | |
107 | int keylen; | |
108 | u32 key[AES_KEYSIZE_256 / sizeof(u32)]; | |
109 | u16 block_size; | |
91308019 | 110 | bool is_aead; |
bd3c7b5c NR |
111 | }; |
112 | ||
ccbf7298 CP |
113 | struct atmel_aes_ctx { |
114 | struct atmel_aes_base_ctx base; | |
115 | }; | |
116 | ||
fcac8365 CP |
117 | struct atmel_aes_ctr_ctx { |
118 | struct atmel_aes_base_ctx base; | |
119 | ||
120 | u32 iv[AES_BLOCK_SIZE / sizeof(u32)]; | |
121 | size_t offset; | |
122 | struct scatterlist src[2]; | |
123 | struct scatterlist dst[2]; | |
124 | }; | |
125 | ||
d4419548 CP |
126 | struct atmel_aes_gcm_ctx { |
127 | struct atmel_aes_base_ctx base; | |
128 | ||
129 | struct scatterlist src[2]; | |
130 | struct scatterlist dst[2]; | |
131 | ||
132 | u32 j0[AES_BLOCK_SIZE / sizeof(u32)]; | |
133 | u32 tag[AES_BLOCK_SIZE / sizeof(u32)]; | |
134 | u32 ghash[AES_BLOCK_SIZE / sizeof(u32)]; | |
135 | size_t textlen; | |
136 | ||
137 | const u32 *ghash_in; | |
138 | u32 *ghash_out; | |
139 | atmel_aes_fn_t ghash_resume; | |
140 | }; | |
141 | ||
d52db518 CP |
142 | struct atmel_aes_xts_ctx { |
143 | struct atmel_aes_base_ctx base; | |
144 | ||
145 | u32 key2[AES_KEYSIZE_256 / sizeof(u32)]; | |
146 | }; | |
147 | ||
89a82ef8 CP |
148 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
149 | struct atmel_aes_authenc_ctx { | |
150 | struct atmel_aes_base_ctx base; | |
151 | struct atmel_sha_authenc_ctx *auth; | |
152 | }; | |
153 | #endif | |
154 | ||
bd3c7b5c | 155 | struct atmel_aes_reqctx { |
afbac17e | 156 | unsigned long mode; |
91308019 | 157 | u32 lastc[AES_BLOCK_SIZE / sizeof(u32)]; |
bd3c7b5c NR |
158 | }; |
159 | ||
89a82ef8 CP |
160 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
161 | struct atmel_aes_authenc_reqctx { | |
162 | struct atmel_aes_reqctx base; | |
163 | ||
164 | struct scatterlist src[2]; | |
165 | struct scatterlist dst[2]; | |
166 | size_t textlen; | |
167 | u32 digest[SHA512_DIGEST_SIZE / sizeof(u32)]; | |
168 | ||
169 | /* auth_req MUST be place last. */ | |
170 | struct ahash_request auth_req; | |
171 | }; | |
172 | #endif | |
173 | ||
bd3c7b5c | 174 | struct atmel_aes_dma { |
bbe628ed CP |
175 | struct dma_chan *chan; |
176 | struct scatterlist *sg; | |
177 | int nents; | |
178 | unsigned int remainder; | |
179 | unsigned int sg_len; | |
bd3c7b5c NR |
180 | }; |
181 | ||
182 | struct atmel_aes_dev { | |
183 | struct list_head list; | |
184 | unsigned long phys_base; | |
185 | void __iomem *io_base; | |
186 | ||
ccbf7298 CP |
187 | struct crypto_async_request *areq; |
188 | struct atmel_aes_base_ctx *ctx; | |
189 | ||
10f12c1b CP |
190 | bool is_async; |
191 | atmel_aes_fn_t resume; | |
bbe628ed | 192 | atmel_aes_fn_t cpu_transfer_complete; |
10f12c1b | 193 | |
bd3c7b5c NR |
194 | struct device *dev; |
195 | struct clk *iclk; | |
afbac17e | 196 | int irq; |
bd3c7b5c NR |
197 | |
198 | unsigned long flags; | |
bd3c7b5c NR |
199 | |
200 | spinlock_t lock; | |
201 | struct crypto_queue queue; | |
202 | ||
203 | struct tasklet_struct done_task; | |
204 | struct tasklet_struct queue_task; | |
205 | ||
bbe628ed CP |
206 | size_t total; |
207 | size_t datalen; | |
208 | u32 *data; | |
bd3c7b5c | 209 | |
bbe628ed CP |
210 | struct atmel_aes_dma src; |
211 | struct atmel_aes_dma dst; | |
bd3c7b5c | 212 | |
bbe628ed CP |
213 | size_t buflen; |
214 | void *buf; | |
215 | struct scatterlist aligned_sg; | |
216 | struct scatterlist *real_dst; | |
bd3c7b5c | 217 | |
cadc4ab8 NR |
218 | struct atmel_aes_caps caps; |
219 | ||
afbac17e | 220 | u32 hw_version; |
bd3c7b5c NR |
221 | }; |
222 | ||
223 | struct atmel_aes_drv { | |
224 | struct list_head dev_list; | |
225 | spinlock_t lock; | |
226 | }; | |
227 | ||
228 | static struct atmel_aes_drv atmel_aes = { | |
229 | .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list), | |
230 | .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock), | |
231 | }; | |
232 | ||
4537992b CP |
233 | #ifdef VERBOSE_DEBUG |
234 | static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz) | |
235 | { | |
236 | switch (offset) { | |
237 | case AES_CR: | |
238 | return "CR"; | |
239 | ||
240 | case AES_MR: | |
241 | return "MR"; | |
242 | ||
243 | case AES_ISR: | |
244 | return "ISR"; | |
245 | ||
246 | case AES_IMR: | |
247 | return "IMR"; | |
248 | ||
249 | case AES_IER: | |
250 | return "IER"; | |
251 | ||
252 | case AES_IDR: | |
253 | return "IDR"; | |
254 | ||
255 | case AES_KEYWR(0): | |
256 | case AES_KEYWR(1): | |
257 | case AES_KEYWR(2): | |
258 | case AES_KEYWR(3): | |
259 | case AES_KEYWR(4): | |
260 | case AES_KEYWR(5): | |
261 | case AES_KEYWR(6): | |
262 | case AES_KEYWR(7): | |
263 | snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2); | |
264 | break; | |
265 | ||
266 | case AES_IDATAR(0): | |
267 | case AES_IDATAR(1): | |
268 | case AES_IDATAR(2): | |
269 | case AES_IDATAR(3): | |
270 | snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2); | |
271 | break; | |
272 | ||
273 | case AES_ODATAR(0): | |
274 | case AES_ODATAR(1): | |
275 | case AES_ODATAR(2): | |
276 | case AES_ODATAR(3): | |
277 | snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2); | |
278 | break; | |
279 | ||
280 | case AES_IVR(0): | |
281 | case AES_IVR(1): | |
282 | case AES_IVR(2): | |
283 | case AES_IVR(3): | |
284 | snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2); | |
285 | break; | |
286 | ||
287 | case AES_AADLENR: | |
288 | return "AADLENR"; | |
289 | ||
290 | case AES_CLENR: | |
291 | return "CLENR"; | |
292 | ||
293 | case AES_GHASHR(0): | |
294 | case AES_GHASHR(1): | |
295 | case AES_GHASHR(2): | |
296 | case AES_GHASHR(3): | |
297 | snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2); | |
298 | break; | |
299 | ||
300 | case AES_TAGR(0): | |
301 | case AES_TAGR(1): | |
302 | case AES_TAGR(2): | |
303 | case AES_TAGR(3): | |
304 | snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2); | |
305 | break; | |
306 | ||
307 | case AES_CTRR: | |
308 | return "CTRR"; | |
309 | ||
310 | case AES_GCMHR(0): | |
311 | case AES_GCMHR(1): | |
312 | case AES_GCMHR(2): | |
313 | case AES_GCMHR(3): | |
314 | snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2); | |
e31835ad | 315 | break; |
4537992b | 316 | |
89a82ef8 CP |
317 | case AES_EMR: |
318 | return "EMR"; | |
319 | ||
d52db518 CP |
320 | case AES_TWR(0): |
321 | case AES_TWR(1): | |
322 | case AES_TWR(2): | |
323 | case AES_TWR(3): | |
324 | snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2); | |
325 | break; | |
326 | ||
327 | case AES_ALPHAR(0): | |
328 | case AES_ALPHAR(1): | |
329 | case AES_ALPHAR(2): | |
330 | case AES_ALPHAR(3): | |
331 | snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2); | |
332 | break; | |
333 | ||
4537992b CP |
334 | default: |
335 | snprintf(tmp, sz, "0x%02x", offset); | |
336 | break; | |
337 | } | |
338 | ||
339 | return tmp; | |
340 | } | |
341 | #endif /* VERBOSE_DEBUG */ | |
342 | ||
e37a7e55 | 343 | /* Shared functions */ |
cadc4ab8 | 344 | |
bd3c7b5c NR |
345 | static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset) |
346 | { | |
4537992b CP |
347 | u32 value = readl_relaxed(dd->io_base + offset); |
348 | ||
349 | #ifdef VERBOSE_DEBUG | |
350 | if (dd->flags & AES_FLAGS_DUMP_REG) { | |
351 | char tmp[16]; | |
352 | ||
353 | dev_vdbg(dd->dev, "read 0x%08x from %s\n", value, | |
354 | atmel_aes_reg_name(offset, tmp, sizeof(tmp))); | |
355 | } | |
356 | #endif /* VERBOSE_DEBUG */ | |
357 | ||
358 | return value; | |
bd3c7b5c NR |
359 | } |
360 | ||
361 | static inline void atmel_aes_write(struct atmel_aes_dev *dd, | |
362 | u32 offset, u32 value) | |
363 | { | |
4537992b CP |
364 | #ifdef VERBOSE_DEBUG |
365 | if (dd->flags & AES_FLAGS_DUMP_REG) { | |
366 | char tmp[16]; | |
367 | ||
368 | dev_vdbg(dd->dev, "write 0x%08x into %s\n", value, | |
f709dc86 | 369 | atmel_aes_reg_name(offset, tmp, sizeof(tmp))); |
4537992b CP |
370 | } |
371 | #endif /* VERBOSE_DEBUG */ | |
372 | ||
bd3c7b5c NR |
373 | writel_relaxed(value, dd->io_base + offset); |
374 | } | |
375 | ||
376 | static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset, | |
377 | u32 *value, int count) | |
378 | { | |
379 | for (; count--; value++, offset += 4) | |
380 | *value = atmel_aes_read(dd, offset); | |
381 | } | |
382 | ||
383 | static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset, | |
c0b28d8c | 384 | const u32 *value, int count) |
bd3c7b5c NR |
385 | { |
386 | for (; count--; value++, offset += 4) | |
387 | atmel_aes_write(dd, offset, *value); | |
388 | } | |
389 | ||
bbe628ed CP |
390 | static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset, |
391 | u32 *value) | |
392 | { | |
393 | atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE)); | |
394 | } | |
395 | ||
396 | static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset, | |
397 | const u32 *value) | |
398 | { | |
399 | atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE)); | |
400 | } | |
401 | ||
402 | static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd, | |
403 | atmel_aes_fn_t resume) | |
404 | { | |
405 | u32 isr = atmel_aes_read(dd, AES_ISR); | |
406 | ||
407 | if (unlikely(isr & AES_INT_DATARDY)) | |
408 | return resume(dd); | |
409 | ||
410 | dd->resume = resume; | |
411 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
412 | return -EINPROGRESS; | |
413 | } | |
414 | ||
415 | static inline size_t atmel_aes_padlen(size_t len, size_t block_size) | |
416 | { | |
417 | len &= block_size - 1; | |
418 | return len ? block_size - len : 0; | |
419 | } | |
420 | ||
ccbf7298 | 421 | static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx) |
bd3c7b5c NR |
422 | { |
423 | struct atmel_aes_dev *aes_dd = NULL; | |
424 | struct atmel_aes_dev *tmp; | |
425 | ||
426 | spin_lock_bh(&atmel_aes.lock); | |
427 | if (!ctx->dd) { | |
428 | list_for_each_entry(tmp, &atmel_aes.dev_list, list) { | |
429 | aes_dd = tmp; | |
430 | break; | |
431 | } | |
432 | ctx->dd = aes_dd; | |
433 | } else { | |
434 | aes_dd = ctx->dd; | |
435 | } | |
436 | ||
437 | spin_unlock_bh(&atmel_aes.lock); | |
438 | ||
439 | return aes_dd; | |
440 | } | |
441 | ||
442 | static int atmel_aes_hw_init(struct atmel_aes_dev *dd) | |
443 | { | |
9d83d299 LC |
444 | int err; |
445 | ||
49a20454 | 446 | err = clk_enable(dd->iclk); |
9d83d299 LC |
447 | if (err) |
448 | return err; | |
bd3c7b5c | 449 | |
7a373fd7 RI |
450 | atmel_aes_write(dd, AES_CR, AES_CR_SWRST); |
451 | atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET); | |
bd3c7b5c NR |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
cadc4ab8 NR |
456 | static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd) |
457 | { | |
458 | return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff; | |
459 | } | |
460 | ||
aab0a39b | 461 | static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd) |
bd3c7b5c | 462 | { |
aab0a39b CP |
463 | int err; |
464 | ||
465 | err = atmel_aes_hw_init(dd); | |
466 | if (err) | |
467 | return err; | |
bd3c7b5c | 468 | |
cadc4ab8 NR |
469 | dd->hw_version = atmel_aes_get_version(dd); |
470 | ||
aab0a39b | 471 | dev_info(dd->dev, "version: 0x%x\n", dd->hw_version); |
bd3c7b5c | 472 | |
49a20454 | 473 | clk_disable(dd->iclk); |
aab0a39b | 474 | return 0; |
bd3c7b5c NR |
475 | } |
476 | ||
77dacf5f CP |
477 | static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd, |
478 | const struct atmel_aes_reqctx *rctx) | |
479 | { | |
480 | /* Clear all but persistent flags and set request flags. */ | |
481 | dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode; | |
482 | } | |
483 | ||
d4419548 CP |
484 | static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd) |
485 | { | |
486 | return (dd->flags & AES_FLAGS_ENCRYPT); | |
487 | } | |
488 | ||
89a82ef8 CP |
489 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
490 | static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err); | |
491 | #endif | |
492 | ||
10f12c1b | 493 | static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err) |
bd3c7b5c | 494 | { |
89a82ef8 | 495 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
91308019 RI |
496 | if (dd->ctx->is_aead) |
497 | atmel_aes_authenc_complete(dd, err); | |
89a82ef8 CP |
498 | #endif |
499 | ||
49a20454 | 500 | clk_disable(dd->iclk); |
bd3c7b5c NR |
501 | dd->flags &= ~AES_FLAGS_BUSY; |
502 | ||
91308019 RI |
503 | if (!dd->ctx->is_aead) { |
504 | struct ablkcipher_request *req = | |
505 | ablkcipher_request_cast(dd->areq); | |
506 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
507 | struct crypto_ablkcipher *ablkcipher = | |
508 | crypto_ablkcipher_reqtfm(req); | |
509 | int ivsize = crypto_ablkcipher_ivsize(ablkcipher); | |
510 | ||
511 | if (rctx->mode & AES_FLAGS_ENCRYPT) { | |
512 | scatterwalk_map_and_copy(req->info, req->dst, | |
513 | req->nbytes - ivsize, ivsize, 0); | |
514 | } else { | |
515 | if (req->src == req->dst) { | |
516 | memcpy(req->info, rctx->lastc, ivsize); | |
517 | } else { | |
518 | scatterwalk_map_and_copy(req->info, req->src, | |
519 | req->nbytes - ivsize, ivsize, 0); | |
520 | } | |
521 | } | |
522 | } | |
523 | ||
10f12c1b CP |
524 | if (dd->is_async) |
525 | dd->areq->complete(dd->areq, err); | |
526 | ||
527 | tasklet_schedule(&dd->queue_task); | |
528 | ||
529 | return err; | |
bd3c7b5c NR |
530 | } |
531 | ||
d52db518 CP |
532 | static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma, |
533 | const u32 *iv, const u32 *key, int keylen) | |
e37a7e55 CP |
534 | { |
535 | u32 valmr = 0; | |
536 | ||
537 | /* MR register must be set before IV registers */ | |
d52db518 | 538 | if (keylen == AES_KEYSIZE_128) |
e37a7e55 | 539 | valmr |= AES_MR_KEYSIZE_128; |
d52db518 | 540 | else if (keylen == AES_KEYSIZE_192) |
e37a7e55 CP |
541 | valmr |= AES_MR_KEYSIZE_192; |
542 | else | |
543 | valmr |= AES_MR_KEYSIZE_256; | |
544 | ||
545 | valmr |= dd->flags & AES_FLAGS_MODE_MASK; | |
546 | ||
547 | if (use_dma) { | |
548 | valmr |= AES_MR_SMOD_IDATAR0; | |
549 | if (dd->caps.has_dualbuff) | |
550 | valmr |= AES_MR_DUALBUFF; | |
551 | } else { | |
552 | valmr |= AES_MR_SMOD_AUTO; | |
553 | } | |
554 | ||
555 | atmel_aes_write(dd, AES_MR, valmr); | |
556 | ||
d52db518 | 557 | atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen)); |
e37a7e55 CP |
558 | |
559 | if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB) | |
560 | atmel_aes_write_block(dd, AES_IVR(0), iv); | |
561 | } | |
562 | ||
d52db518 CP |
563 | static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma, |
564 | const u32 *iv) | |
565 | ||
566 | { | |
567 | atmel_aes_write_ctrl_key(dd, use_dma, iv, | |
568 | dd->ctx->key, dd->ctx->keylen); | |
569 | } | |
bbe628ed CP |
570 | |
571 | /* CPU transfer */ | |
572 | ||
573 | static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd) | |
bd3c7b5c | 574 | { |
bbe628ed CP |
575 | int err = 0; |
576 | u32 isr; | |
bd3c7b5c | 577 | |
bbe628ed CP |
578 | for (;;) { |
579 | atmel_aes_read_block(dd, AES_ODATAR(0), dd->data); | |
580 | dd->data += 4; | |
581 | dd->datalen -= AES_BLOCK_SIZE; | |
582 | ||
583 | if (dd->datalen < AES_BLOCK_SIZE) | |
584 | break; | |
585 | ||
586 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
587 | ||
588 | isr = atmel_aes_read(dd, AES_ISR); | |
589 | if (!(isr & AES_INT_DATARDY)) { | |
590 | dd->resume = atmel_aes_cpu_transfer; | |
591 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
592 | return -EINPROGRESS; | |
593 | } | |
594 | } | |
595 | ||
596 | if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), | |
597 | dd->buf, dd->total)) | |
598 | err = -EINVAL; | |
599 | ||
600 | if (err) | |
601 | return atmel_aes_complete(dd, err); | |
602 | ||
603 | return dd->cpu_transfer_complete(dd); | |
bd3c7b5c NR |
604 | } |
605 | ||
bbe628ed CP |
606 | static int atmel_aes_cpu_start(struct atmel_aes_dev *dd, |
607 | struct scatterlist *src, | |
608 | struct scatterlist *dst, | |
609 | size_t len, | |
610 | atmel_aes_fn_t resume) | |
bd3c7b5c | 611 | { |
bbe628ed | 612 | size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE); |
77dacf5f | 613 | |
bbe628ed CP |
614 | if (unlikely(len == 0)) |
615 | return -EINVAL; | |
77dacf5f | 616 | |
bbe628ed | 617 | sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); |
77dacf5f | 618 | |
bbe628ed CP |
619 | dd->total = len; |
620 | dd->real_dst = dst; | |
621 | dd->cpu_transfer_complete = resume; | |
622 | dd->datalen = len + padlen; | |
623 | dd->data = (u32 *)dd->buf; | |
624 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
625 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer); | |
626 | } | |
77dacf5f | 627 | |
77dacf5f | 628 | |
bbe628ed CP |
629 | /* DMA transfer */ |
630 | ||
631 | static void atmel_aes_dma_callback(void *data); | |
632 | ||
633 | static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd, | |
634 | struct scatterlist *sg, | |
635 | size_t len, | |
636 | struct atmel_aes_dma *dma) | |
637 | { | |
638 | int nents; | |
639 | ||
640 | if (!IS_ALIGNED(len, dd->ctx->block_size)) | |
641 | return false; | |
642 | ||
643 | for (nents = 0; sg; sg = sg_next(sg), ++nents) { | |
644 | if (!IS_ALIGNED(sg->offset, sizeof(u32))) | |
645 | return false; | |
646 | ||
647 | if (len <= sg->length) { | |
648 | if (!IS_ALIGNED(len, dd->ctx->block_size)) | |
649 | return false; | |
650 | ||
651 | dma->nents = nents+1; | |
652 | dma->remainder = sg->length - len; | |
653 | sg->length = len; | |
654 | return true; | |
655 | } | |
656 | ||
657 | if (!IS_ALIGNED(sg->length, dd->ctx->block_size)) | |
658 | return false; | |
659 | ||
660 | len -= sg->length; | |
77dacf5f | 661 | } |
bd3c7b5c | 662 | |
bbe628ed CP |
663 | return false; |
664 | } | |
bd3c7b5c | 665 | |
bbe628ed CP |
666 | static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma) |
667 | { | |
668 | struct scatterlist *sg = dma->sg; | |
669 | int nents = dma->nents; | |
bd3c7b5c | 670 | |
bbe628ed CP |
671 | if (!dma->remainder) |
672 | return; | |
bd3c7b5c | 673 | |
bbe628ed CP |
674 | while (--nents > 0 && sg) |
675 | sg = sg_next(sg); | |
bd3c7b5c | 676 | |
bbe628ed CP |
677 | if (!sg) |
678 | return; | |
bd3c7b5c | 679 | |
bbe628ed CP |
680 | sg->length += dma->remainder; |
681 | } | |
bd3c7b5c | 682 | |
bbe628ed CP |
683 | static int atmel_aes_map(struct atmel_aes_dev *dd, |
684 | struct scatterlist *src, | |
685 | struct scatterlist *dst, | |
686 | size_t len) | |
687 | { | |
688 | bool src_aligned, dst_aligned; | |
689 | size_t padlen; | |
cadc4ab8 | 690 | |
bbe628ed CP |
691 | dd->total = len; |
692 | dd->src.sg = src; | |
693 | dd->dst.sg = dst; | |
694 | dd->real_dst = dst; | |
bd3c7b5c | 695 | |
bbe628ed CP |
696 | src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src); |
697 | if (src == dst) | |
698 | dst_aligned = src_aligned; | |
699 | else | |
700 | dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst); | |
701 | if (!src_aligned || !dst_aligned) { | |
702 | padlen = atmel_aes_padlen(len, dd->ctx->block_size); | |
703 | ||
704 | if (dd->buflen < len + padlen) | |
705 | return -ENOMEM; | |
706 | ||
707 | if (!src_aligned) { | |
708 | sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); | |
709 | dd->src.sg = &dd->aligned_sg; | |
710 | dd->src.nents = 1; | |
711 | dd->src.remainder = 0; | |
712 | } | |
bd3c7b5c | 713 | |
bbe628ed CP |
714 | if (!dst_aligned) { |
715 | dd->dst.sg = &dd->aligned_sg; | |
716 | dd->dst.nents = 1; | |
717 | dd->dst.remainder = 0; | |
718 | } | |
bd3c7b5c | 719 | |
bbe628ed CP |
720 | sg_init_table(&dd->aligned_sg, 1); |
721 | sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen); | |
722 | } | |
bd3c7b5c | 723 | |
bbe628ed CP |
724 | if (dd->src.sg == dd->dst.sg) { |
725 | dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, | |
726 | DMA_BIDIRECTIONAL); | |
727 | dd->dst.sg_len = dd->src.sg_len; | |
728 | if (!dd->src.sg_len) | |
729 | return -EFAULT; | |
730 | } else { | |
731 | dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, | |
732 | DMA_TO_DEVICE); | |
733 | if (!dd->src.sg_len) | |
734 | return -EFAULT; | |
735 | ||
736 | dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents, | |
737 | DMA_FROM_DEVICE); | |
738 | if (!dd->dst.sg_len) { | |
739 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, | |
740 | DMA_TO_DEVICE); | |
741 | return -EFAULT; | |
742 | } | |
743 | } | |
bd3c7b5c NR |
744 | |
745 | return 0; | |
bd3c7b5c NR |
746 | } |
747 | ||
bbe628ed | 748 | static void atmel_aes_unmap(struct atmel_aes_dev *dd) |
bd3c7b5c | 749 | { |
bbe628ed CP |
750 | if (dd->src.sg == dd->dst.sg) { |
751 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, | |
752 | DMA_BIDIRECTIONAL); | |
ccbf7298 | 753 | |
bbe628ed CP |
754 | if (dd->src.sg != &dd->aligned_sg) |
755 | atmel_aes_restore_sg(&dd->src); | |
756 | } else { | |
757 | dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents, | |
758 | DMA_FROM_DEVICE); | |
289b2623 | 759 | |
bbe628ed CP |
760 | if (dd->dst.sg != &dd->aligned_sg) |
761 | atmel_aes_restore_sg(&dd->dst); | |
bd3c7b5c | 762 | |
bbe628ed CP |
763 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, |
764 | DMA_TO_DEVICE); | |
765 | ||
766 | if (dd->src.sg != &dd->aligned_sg) | |
767 | atmel_aes_restore_sg(&dd->src); | |
768 | } | |
769 | ||
770 | if (dd->dst.sg == &dd->aligned_sg) | |
771 | sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), | |
772 | dd->buf, dd->total); | |
773 | } | |
bd3c7b5c | 774 | |
bbe628ed CP |
775 | static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd, |
776 | enum dma_slave_buswidth addr_width, | |
777 | enum dma_transfer_direction dir, | |
778 | u32 maxburst) | |
779 | { | |
780 | struct dma_async_tx_descriptor *desc; | |
781 | struct dma_slave_config config; | |
782 | dma_async_tx_callback callback; | |
783 | struct atmel_aes_dma *dma; | |
784 | int err; | |
785 | ||
786 | memset(&config, 0, sizeof(config)); | |
787 | config.direction = dir; | |
788 | config.src_addr_width = addr_width; | |
789 | config.dst_addr_width = addr_width; | |
790 | config.src_maxburst = maxburst; | |
791 | config.dst_maxburst = maxburst; | |
792 | ||
793 | switch (dir) { | |
794 | case DMA_MEM_TO_DEV: | |
795 | dma = &dd->src; | |
796 | callback = NULL; | |
797 | config.dst_addr = dd->phys_base + AES_IDATAR(0); | |
798 | break; | |
bd3c7b5c | 799 | |
bbe628ed CP |
800 | case DMA_DEV_TO_MEM: |
801 | dma = &dd->dst; | |
802 | callback = atmel_aes_dma_callback; | |
803 | config.src_addr = dd->phys_base + AES_ODATAR(0); | |
804 | break; | |
805 | ||
806 | default: | |
bd3c7b5c | 807 | return -EINVAL; |
bbe628ed | 808 | } |
bd3c7b5c | 809 | |
bbe628ed CP |
810 | err = dmaengine_slave_config(dma->chan, &config); |
811 | if (err) | |
812 | return err; | |
bd3c7b5c | 813 | |
bbe628ed CP |
814 | desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir, |
815 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
816 | if (!desc) | |
817 | return -ENOMEM; | |
bd3c7b5c | 818 | |
bbe628ed CP |
819 | desc->callback = callback; |
820 | desc->callback_param = dd; | |
821 | dmaengine_submit(desc); | |
822 | dma_async_issue_pending(dma->chan); | |
bd3c7b5c | 823 | |
bbe628ed CP |
824 | return 0; |
825 | } | |
10f12c1b | 826 | |
bbe628ed CP |
827 | static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd, |
828 | enum dma_transfer_direction dir) | |
bd3c7b5c | 829 | { |
bbe628ed | 830 | struct atmel_aes_dma *dma; |
cadc4ab8 | 831 | |
bbe628ed CP |
832 | switch (dir) { |
833 | case DMA_MEM_TO_DEV: | |
834 | dma = &dd->src; | |
835 | break; | |
836 | ||
837 | case DMA_DEV_TO_MEM: | |
838 | dma = &dd->dst; | |
839 | break; | |
cadc4ab8 | 840 | |
bbe628ed CP |
841 | default: |
842 | return; | |
cadc4ab8 NR |
843 | } |
844 | ||
bbe628ed CP |
845 | dmaengine_terminate_all(dma->chan); |
846 | } | |
cadc4ab8 | 847 | |
bbe628ed CP |
848 | static int atmel_aes_dma_start(struct atmel_aes_dev *dd, |
849 | struct scatterlist *src, | |
850 | struct scatterlist *dst, | |
851 | size_t len, | |
852 | atmel_aes_fn_t resume) | |
853 | { | |
854 | enum dma_slave_buswidth addr_width; | |
855 | u32 maxburst; | |
856 | int err; | |
cadc4ab8 | 857 | |
bbe628ed CP |
858 | switch (dd->ctx->block_size) { |
859 | case CFB8_BLOCK_SIZE: | |
860 | addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
861 | maxburst = 1; | |
862 | break; | |
cadc4ab8 | 863 | |
bbe628ed CP |
864 | case CFB16_BLOCK_SIZE: |
865 | addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
866 | maxburst = 1; | |
867 | break; | |
cadc4ab8 | 868 | |
bbe628ed CP |
869 | case CFB32_BLOCK_SIZE: |
870 | case CFB64_BLOCK_SIZE: | |
871 | addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
872 | maxburst = 1; | |
873 | break; | |
cadc4ab8 | 874 | |
bbe628ed CP |
875 | case AES_BLOCK_SIZE: |
876 | addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
877 | maxburst = dd->caps.max_burst_size; | |
878 | break; | |
bd3c7b5c | 879 | |
bbe628ed CP |
880 | default: |
881 | err = -EINVAL; | |
882 | goto exit; | |
883 | } | |
289b2623 | 884 | |
bbe628ed CP |
885 | err = atmel_aes_map(dd, src, dst, len); |
886 | if (err) | |
887 | goto exit; | |
cadc4ab8 | 888 | |
bbe628ed | 889 | dd->resume = resume; |
cadc4ab8 | 890 | |
bbe628ed CP |
891 | /* Set output DMA transfer first */ |
892 | err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM, | |
893 | maxburst); | |
894 | if (err) | |
895 | goto unmap; | |
bd3c7b5c | 896 | |
bbe628ed CP |
897 | /* Then set input DMA transfer */ |
898 | err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV, | |
899 | maxburst); | |
900 | if (err) | |
901 | goto output_transfer_stop; | |
bd3c7b5c | 902 | |
bbe628ed | 903 | return -EINPROGRESS; |
cadc4ab8 | 904 | |
bbe628ed CP |
905 | output_transfer_stop: |
906 | atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM); | |
907 | unmap: | |
908 | atmel_aes_unmap(dd); | |
909 | exit: | |
910 | return atmel_aes_complete(dd, err); | |
911 | } | |
bd3c7b5c | 912 | |
bbe628ed CP |
913 | static void atmel_aes_dma_stop(struct atmel_aes_dev *dd) |
914 | { | |
915 | atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV); | |
916 | atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM); | |
917 | atmel_aes_unmap(dd); | |
918 | } | |
919 | ||
920 | static void atmel_aes_dma_callback(void *data) | |
921 | { | |
922 | struct atmel_aes_dev *dd = data; | |
923 | ||
924 | atmel_aes_dma_stop(dd); | |
925 | dd->is_async = true; | |
926 | (void)dd->resume(dd); | |
bd3c7b5c NR |
927 | } |
928 | ||
bd3c7b5c | 929 | static int atmel_aes_handle_queue(struct atmel_aes_dev *dd, |
ccbf7298 | 930 | struct crypto_async_request *new_areq) |
bd3c7b5c | 931 | { |
ccbf7298 CP |
932 | struct crypto_async_request *areq, *backlog; |
933 | struct atmel_aes_base_ctx *ctx; | |
bd3c7b5c | 934 | unsigned long flags; |
a1f613f1 | 935 | bool start_async; |
bd3c7b5c NR |
936 | int err, ret = 0; |
937 | ||
938 | spin_lock_irqsave(&dd->lock, flags); | |
ccbf7298 CP |
939 | if (new_areq) |
940 | ret = crypto_enqueue_request(&dd->queue, new_areq); | |
bd3c7b5c NR |
941 | if (dd->flags & AES_FLAGS_BUSY) { |
942 | spin_unlock_irqrestore(&dd->lock, flags); | |
943 | return ret; | |
944 | } | |
945 | backlog = crypto_get_backlog(&dd->queue); | |
ccbf7298 CP |
946 | areq = crypto_dequeue_request(&dd->queue); |
947 | if (areq) | |
bd3c7b5c NR |
948 | dd->flags |= AES_FLAGS_BUSY; |
949 | spin_unlock_irqrestore(&dd->lock, flags); | |
950 | ||
ccbf7298 | 951 | if (!areq) |
bd3c7b5c NR |
952 | return ret; |
953 | ||
954 | if (backlog) | |
955 | backlog->complete(backlog, -EINPROGRESS); | |
956 | ||
ccbf7298 CP |
957 | ctx = crypto_tfm_ctx(areq->tfm); |
958 | ||
959 | dd->areq = areq; | |
960 | dd->ctx = ctx; | |
a1f613f1 CP |
961 | start_async = (areq != new_areq); |
962 | dd->is_async = start_async; | |
ccbf7298 | 963 | |
a1f613f1 | 964 | /* WARNING: ctx->start() MAY change dd->is_async. */ |
ccbf7298 | 965 | err = ctx->start(dd); |
a1f613f1 | 966 | return (start_async) ? ret : err; |
ccbf7298 CP |
967 | } |
968 | ||
e37a7e55 CP |
969 | |
970 | /* AES async block ciphers */ | |
971 | ||
bbe628ed CP |
972 | static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd) |
973 | { | |
974 | return atmel_aes_complete(dd, 0); | |
975 | } | |
976 | ||
ccbf7298 CP |
977 | static int atmel_aes_start(struct atmel_aes_dev *dd) |
978 | { | |
979 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
bbe628ed CP |
980 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
981 | bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD || | |
982 | dd->ctx->block_size != AES_BLOCK_SIZE); | |
ccbf7298 | 983 | int err; |
bd3c7b5c | 984 | |
77dacf5f | 985 | atmel_aes_set_mode(dd, rctx); |
bd3c7b5c | 986 | |
cdfab4a7 | 987 | err = atmel_aes_hw_init(dd); |
bbe628ed | 988 | if (err) |
10f12c1b | 989 | return atmel_aes_complete(dd, err); |
bd3c7b5c | 990 | |
bbe628ed CP |
991 | atmel_aes_write_ctrl(dd, use_dma, req->info); |
992 | if (use_dma) | |
993 | return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes, | |
994 | atmel_aes_transfer_complete); | |
bd3c7b5c | 995 | |
bbe628ed CP |
996 | return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes, |
997 | atmel_aes_transfer_complete); | |
bd3c7b5c NR |
998 | } |
999 | ||
fcac8365 CP |
1000 | static inline struct atmel_aes_ctr_ctx * |
1001 | atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx) | |
1002 | { | |
1003 | return container_of(ctx, struct atmel_aes_ctr_ctx, base); | |
1004 | } | |
1005 | ||
1006 | static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) | |
1007 | { | |
1008 | struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); | |
1009 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
1010 | struct scatterlist *src, *dst; | |
1011 | u32 ctr, blocks; | |
1012 | size_t datalen; | |
1013 | bool use_dma, fragmented = false; | |
1014 | ||
1015 | /* Check for transfer completion. */ | |
1016 | ctx->offset += dd->total; | |
1017 | if (ctx->offset >= req->nbytes) | |
1018 | return atmel_aes_transfer_complete(dd); | |
1019 | ||
1020 | /* Compute data length. */ | |
1021 | datalen = req->nbytes - ctx->offset; | |
1022 | blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); | |
1023 | ctr = be32_to_cpu(ctx->iv[3]); | |
1024 | if (dd->caps.has_ctr32) { | |
1025 | /* Check 32bit counter overflow. */ | |
1026 | u32 start = ctr; | |
1027 | u32 end = start + blocks - 1; | |
1028 | ||
1029 | if (end < start) { | |
1030 | ctr |= 0xffffffff; | |
1031 | datalen = AES_BLOCK_SIZE * -start; | |
1032 | fragmented = true; | |
1033 | } | |
1034 | } else { | |
1035 | /* Check 16bit counter overflow. */ | |
1036 | u16 start = ctr & 0xffff; | |
1037 | u16 end = start + (u16)blocks - 1; | |
1038 | ||
1039 | if (blocks >> 16 || end < start) { | |
1040 | ctr |= 0xffff; | |
1041 | datalen = AES_BLOCK_SIZE * (0x10000-start); | |
1042 | fragmented = true; | |
1043 | } | |
1044 | } | |
1045 | use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); | |
1046 | ||
1047 | /* Jump to offset. */ | |
1048 | src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset); | |
1049 | dst = ((req->src == req->dst) ? src : | |
1050 | scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset)); | |
1051 | ||
1052 | /* Configure hardware. */ | |
1053 | atmel_aes_write_ctrl(dd, use_dma, ctx->iv); | |
1054 | if (unlikely(fragmented)) { | |
1055 | /* | |
1056 | * Increment the counter manually to cope with the hardware | |
1057 | * counter overflow. | |
1058 | */ | |
1059 | ctx->iv[3] = cpu_to_be32(ctr); | |
1060 | crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE); | |
1061 | } | |
1062 | ||
1063 | if (use_dma) | |
1064 | return atmel_aes_dma_start(dd, src, dst, datalen, | |
1065 | atmel_aes_ctr_transfer); | |
1066 | ||
1067 | return atmel_aes_cpu_start(dd, src, dst, datalen, | |
1068 | atmel_aes_ctr_transfer); | |
1069 | } | |
1070 | ||
1071 | static int atmel_aes_ctr_start(struct atmel_aes_dev *dd) | |
1072 | { | |
1073 | struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); | |
1074 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
1075 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
1076 | int err; | |
1077 | ||
1078 | atmel_aes_set_mode(dd, rctx); | |
1079 | ||
1080 | err = atmel_aes_hw_init(dd); | |
1081 | if (err) | |
1082 | return atmel_aes_complete(dd, err); | |
1083 | ||
1084 | memcpy(ctx->iv, req->info, AES_BLOCK_SIZE); | |
1085 | ctx->offset = 0; | |
1086 | dd->total = 0; | |
1087 | return atmel_aes_ctr_transfer(dd); | |
1088 | } | |
1089 | ||
bd3c7b5c NR |
1090 | static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode) |
1091 | { | |
91308019 RI |
1092 | struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); |
1093 | struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); | |
afbac17e | 1094 | struct atmel_aes_reqctx *rctx; |
bd3c7b5c NR |
1095 | struct atmel_aes_dev *dd; |
1096 | ||
77dacf5f CP |
1097 | switch (mode & AES_FLAGS_OPMODE_MASK) { |
1098 | case AES_FLAGS_CFB8: | |
cadc4ab8 | 1099 | ctx->block_size = CFB8_BLOCK_SIZE; |
77dacf5f CP |
1100 | break; |
1101 | ||
1102 | case AES_FLAGS_CFB16: | |
cadc4ab8 | 1103 | ctx->block_size = CFB16_BLOCK_SIZE; |
77dacf5f CP |
1104 | break; |
1105 | ||
1106 | case AES_FLAGS_CFB32: | |
cadc4ab8 | 1107 | ctx->block_size = CFB32_BLOCK_SIZE; |
77dacf5f CP |
1108 | break; |
1109 | ||
1110 | case AES_FLAGS_CFB64: | |
9f84951f | 1111 | ctx->block_size = CFB64_BLOCK_SIZE; |
77dacf5f CP |
1112 | break; |
1113 | ||
1114 | default: | |
cadc4ab8 | 1115 | ctx->block_size = AES_BLOCK_SIZE; |
77dacf5f | 1116 | break; |
bd3c7b5c | 1117 | } |
91308019 | 1118 | ctx->is_aead = false; |
bd3c7b5c NR |
1119 | |
1120 | dd = atmel_aes_find_dev(ctx); | |
1121 | if (!dd) | |
1122 | return -ENODEV; | |
1123 | ||
afbac17e | 1124 | rctx = ablkcipher_request_ctx(req); |
bd3c7b5c NR |
1125 | rctx->mode = mode; |
1126 | ||
91308019 RI |
1127 | if (!(mode & AES_FLAGS_ENCRYPT) && (req->src == req->dst)) { |
1128 | int ivsize = crypto_ablkcipher_ivsize(ablkcipher); | |
1129 | ||
1130 | scatterwalk_map_and_copy(rctx->lastc, req->src, | |
1131 | (req->nbytes - ivsize), ivsize, 0); | |
1132 | } | |
1133 | ||
ccbf7298 | 1134 | return atmel_aes_handle_queue(dd, &req->base); |
bd3c7b5c NR |
1135 | } |
1136 | ||
bd3c7b5c NR |
1137 | static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, |
1138 | unsigned int keylen) | |
1139 | { | |
ccbf7298 | 1140 | struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm); |
bd3c7b5c | 1141 | |
afbac17e CP |
1142 | if (keylen != AES_KEYSIZE_128 && |
1143 | keylen != AES_KEYSIZE_192 && | |
1144 | keylen != AES_KEYSIZE_256) { | |
bd3c7b5c NR |
1145 | crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
1149 | memcpy(ctx->key, key, keylen); | |
1150 | ctx->keylen = keylen; | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req) | |
1156 | { | |
77dacf5f | 1157 | return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1158 | } |
1159 | ||
1160 | static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req) | |
1161 | { | |
77dacf5f | 1162 | return atmel_aes_crypt(req, AES_FLAGS_ECB); |
bd3c7b5c NR |
1163 | } |
1164 | ||
1165 | static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req) | |
1166 | { | |
afbac17e | 1167 | return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1168 | } |
1169 | ||
1170 | static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req) | |
1171 | { | |
afbac17e | 1172 | return atmel_aes_crypt(req, AES_FLAGS_CBC); |
bd3c7b5c NR |
1173 | } |
1174 | ||
1175 | static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req) | |
1176 | { | |
afbac17e | 1177 | return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1178 | } |
1179 | ||
1180 | static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req) | |
1181 | { | |
afbac17e | 1182 | return atmel_aes_crypt(req, AES_FLAGS_OFB); |
bd3c7b5c NR |
1183 | } |
1184 | ||
1185 | static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req) | |
1186 | { | |
77dacf5f | 1187 | return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1188 | } |
1189 | ||
1190 | static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req) | |
1191 | { | |
77dacf5f | 1192 | return atmel_aes_crypt(req, AES_FLAGS_CFB128); |
bd3c7b5c NR |
1193 | } |
1194 | ||
1195 | static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req) | |
1196 | { | |
77dacf5f | 1197 | return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1198 | } |
1199 | ||
1200 | static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req) | |
1201 | { | |
77dacf5f | 1202 | return atmel_aes_crypt(req, AES_FLAGS_CFB64); |
bd3c7b5c NR |
1203 | } |
1204 | ||
1205 | static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req) | |
1206 | { | |
77dacf5f | 1207 | return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1208 | } |
1209 | ||
1210 | static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req) | |
1211 | { | |
77dacf5f | 1212 | return atmel_aes_crypt(req, AES_FLAGS_CFB32); |
bd3c7b5c NR |
1213 | } |
1214 | ||
1215 | static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req) | |
1216 | { | |
77dacf5f | 1217 | return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1218 | } |
1219 | ||
1220 | static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req) | |
1221 | { | |
77dacf5f | 1222 | return atmel_aes_crypt(req, AES_FLAGS_CFB16); |
bd3c7b5c NR |
1223 | } |
1224 | ||
1225 | static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req) | |
1226 | { | |
77dacf5f | 1227 | return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1228 | } |
1229 | ||
1230 | static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req) | |
1231 | { | |
77dacf5f | 1232 | return atmel_aes_crypt(req, AES_FLAGS_CFB8); |
bd3c7b5c NR |
1233 | } |
1234 | ||
1235 | static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req) | |
1236 | { | |
afbac17e | 1237 | return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1238 | } |
1239 | ||
1240 | static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req) | |
1241 | { | |
afbac17e | 1242 | return atmel_aes_crypt(req, AES_FLAGS_CTR); |
bd3c7b5c NR |
1243 | } |
1244 | ||
1245 | static int atmel_aes_cra_init(struct crypto_tfm *tfm) | |
1246 | { | |
ccbf7298 CP |
1247 | struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
1248 | ||
bd3c7b5c | 1249 | tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx); |
ccbf7298 | 1250 | ctx->base.start = atmel_aes_start; |
bd3c7b5c NR |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
fcac8365 CP |
1255 | static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm) |
1256 | { | |
1257 | struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
1258 | ||
1259 | tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx); | |
1260 | ctx->base.start = atmel_aes_ctr_start; | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
bd3c7b5c NR |
1265 | static struct crypto_alg aes_algs[] = { |
1266 | { | |
1267 | .cra_name = "ecb(aes)", | |
1268 | .cra_driver_name = "atmel-ecb-aes", | |
88efd9a9 | 1269 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1270 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1271 | .cra_blocksize = AES_BLOCK_SIZE, | |
1272 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1273 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1274 | .cra_type = &crypto_ablkcipher_type, |
1275 | .cra_module = THIS_MODULE, | |
1276 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1277 | .cra_u.ablkcipher = { |
1278 | .min_keysize = AES_MIN_KEY_SIZE, | |
1279 | .max_keysize = AES_MAX_KEY_SIZE, | |
1280 | .setkey = atmel_aes_setkey, | |
1281 | .encrypt = atmel_aes_ecb_encrypt, | |
1282 | .decrypt = atmel_aes_ecb_decrypt, | |
1283 | } | |
1284 | }, | |
1285 | { | |
1286 | .cra_name = "cbc(aes)", | |
1287 | .cra_driver_name = "atmel-cbc-aes", | |
88efd9a9 | 1288 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1289 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1290 | .cra_blocksize = AES_BLOCK_SIZE, | |
1291 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1292 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1293 | .cra_type = &crypto_ablkcipher_type, |
1294 | .cra_module = THIS_MODULE, | |
1295 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1296 | .cra_u.ablkcipher = { |
1297 | .min_keysize = AES_MIN_KEY_SIZE, | |
1298 | .max_keysize = AES_MAX_KEY_SIZE, | |
1299 | .ivsize = AES_BLOCK_SIZE, | |
1300 | .setkey = atmel_aes_setkey, | |
1301 | .encrypt = atmel_aes_cbc_encrypt, | |
1302 | .decrypt = atmel_aes_cbc_decrypt, | |
1303 | } | |
1304 | }, | |
1305 | { | |
1306 | .cra_name = "ofb(aes)", | |
1307 | .cra_driver_name = "atmel-ofb-aes", | |
88efd9a9 | 1308 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1309 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1310 | .cra_blocksize = AES_BLOCK_SIZE, | |
1311 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1312 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1313 | .cra_type = &crypto_ablkcipher_type, |
1314 | .cra_module = THIS_MODULE, | |
1315 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1316 | .cra_u.ablkcipher = { |
1317 | .min_keysize = AES_MIN_KEY_SIZE, | |
1318 | .max_keysize = AES_MAX_KEY_SIZE, | |
1319 | .ivsize = AES_BLOCK_SIZE, | |
1320 | .setkey = atmel_aes_setkey, | |
1321 | .encrypt = atmel_aes_ofb_encrypt, | |
1322 | .decrypt = atmel_aes_ofb_decrypt, | |
1323 | } | |
1324 | }, | |
1325 | { | |
1326 | .cra_name = "cfb(aes)", | |
1327 | .cra_driver_name = "atmel-cfb-aes", | |
88efd9a9 | 1328 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1329 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1330 | .cra_blocksize = AES_BLOCK_SIZE, | |
1331 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1332 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1333 | .cra_type = &crypto_ablkcipher_type, |
1334 | .cra_module = THIS_MODULE, | |
1335 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1336 | .cra_u.ablkcipher = { |
1337 | .min_keysize = AES_MIN_KEY_SIZE, | |
1338 | .max_keysize = AES_MAX_KEY_SIZE, | |
1339 | .ivsize = AES_BLOCK_SIZE, | |
1340 | .setkey = atmel_aes_setkey, | |
1341 | .encrypt = atmel_aes_cfb_encrypt, | |
1342 | .decrypt = atmel_aes_cfb_decrypt, | |
1343 | } | |
1344 | }, | |
1345 | { | |
1346 | .cra_name = "cfb32(aes)", | |
1347 | .cra_driver_name = "atmel-cfb32-aes", | |
88efd9a9 | 1348 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1349 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1350 | .cra_blocksize = CFB32_BLOCK_SIZE, | |
1351 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1352 | .cra_alignmask = 0x3, |
bd3c7b5c NR |
1353 | .cra_type = &crypto_ablkcipher_type, |
1354 | .cra_module = THIS_MODULE, | |
1355 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1356 | .cra_u.ablkcipher = { |
1357 | .min_keysize = AES_MIN_KEY_SIZE, | |
1358 | .max_keysize = AES_MAX_KEY_SIZE, | |
1359 | .ivsize = AES_BLOCK_SIZE, | |
1360 | .setkey = atmel_aes_setkey, | |
1361 | .encrypt = atmel_aes_cfb32_encrypt, | |
1362 | .decrypt = atmel_aes_cfb32_decrypt, | |
1363 | } | |
1364 | }, | |
1365 | { | |
1366 | .cra_name = "cfb16(aes)", | |
1367 | .cra_driver_name = "atmel-cfb16-aes", | |
88efd9a9 | 1368 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1369 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1370 | .cra_blocksize = CFB16_BLOCK_SIZE, | |
1371 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1372 | .cra_alignmask = 0x1, |
bd3c7b5c NR |
1373 | .cra_type = &crypto_ablkcipher_type, |
1374 | .cra_module = THIS_MODULE, | |
1375 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1376 | .cra_u.ablkcipher = { |
1377 | .min_keysize = AES_MIN_KEY_SIZE, | |
1378 | .max_keysize = AES_MAX_KEY_SIZE, | |
1379 | .ivsize = AES_BLOCK_SIZE, | |
1380 | .setkey = atmel_aes_setkey, | |
1381 | .encrypt = atmel_aes_cfb16_encrypt, | |
1382 | .decrypt = atmel_aes_cfb16_decrypt, | |
1383 | } | |
1384 | }, | |
1385 | { | |
1386 | .cra_name = "cfb8(aes)", | |
1387 | .cra_driver_name = "atmel-cfb8-aes", | |
88efd9a9 | 1388 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c | 1389 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
e5d8c961 | 1390 | .cra_blocksize = CFB8_BLOCK_SIZE, |
bd3c7b5c NR |
1391 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), |
1392 | .cra_alignmask = 0x0, | |
1393 | .cra_type = &crypto_ablkcipher_type, | |
1394 | .cra_module = THIS_MODULE, | |
1395 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1396 | .cra_u.ablkcipher = { |
1397 | .min_keysize = AES_MIN_KEY_SIZE, | |
1398 | .max_keysize = AES_MAX_KEY_SIZE, | |
1399 | .ivsize = AES_BLOCK_SIZE, | |
1400 | .setkey = atmel_aes_setkey, | |
1401 | .encrypt = atmel_aes_cfb8_encrypt, | |
1402 | .decrypt = atmel_aes_cfb8_decrypt, | |
1403 | } | |
1404 | }, | |
1405 | { | |
1406 | .cra_name = "ctr(aes)", | |
1407 | .cra_driver_name = "atmel-ctr-aes", | |
88efd9a9 | 1408 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c | 1409 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
da7b850e | 1410 | .cra_blocksize = 1, |
fcac8365 | 1411 | .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx), |
cadc4ab8 | 1412 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1413 | .cra_type = &crypto_ablkcipher_type, |
1414 | .cra_module = THIS_MODULE, | |
fcac8365 | 1415 | .cra_init = atmel_aes_ctr_cra_init, |
bd3c7b5c NR |
1416 | .cra_u.ablkcipher = { |
1417 | .min_keysize = AES_MIN_KEY_SIZE, | |
1418 | .max_keysize = AES_MAX_KEY_SIZE, | |
1419 | .ivsize = AES_BLOCK_SIZE, | |
1420 | .setkey = atmel_aes_setkey, | |
1421 | .encrypt = atmel_aes_ctr_encrypt, | |
1422 | .decrypt = atmel_aes_ctr_decrypt, | |
1423 | } | |
1424 | }, | |
1425 | }; | |
1426 | ||
cadc4ab8 | 1427 | static struct crypto_alg aes_cfb64_alg = { |
bd3c7b5c NR |
1428 | .cra_name = "cfb64(aes)", |
1429 | .cra_driver_name = "atmel-cfb64-aes", | |
88efd9a9 | 1430 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1431 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1432 | .cra_blocksize = CFB64_BLOCK_SIZE, | |
1433 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1434 | .cra_alignmask = 0x7, |
bd3c7b5c NR |
1435 | .cra_type = &crypto_ablkcipher_type, |
1436 | .cra_module = THIS_MODULE, | |
1437 | .cra_init = atmel_aes_cra_init, | |
bd3c7b5c NR |
1438 | .cra_u.ablkcipher = { |
1439 | .min_keysize = AES_MIN_KEY_SIZE, | |
1440 | .max_keysize = AES_MAX_KEY_SIZE, | |
1441 | .ivsize = AES_BLOCK_SIZE, | |
1442 | .setkey = atmel_aes_setkey, | |
1443 | .encrypt = atmel_aes_cfb64_encrypt, | |
1444 | .decrypt = atmel_aes_cfb64_decrypt, | |
1445 | } | |
bd3c7b5c NR |
1446 | }; |
1447 | ||
e37a7e55 | 1448 | |
d4419548 CP |
1449 | /* gcm aead functions */ |
1450 | ||
1451 | static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd, | |
1452 | const u32 *data, size_t datalen, | |
1453 | const u32 *ghash_in, u32 *ghash_out, | |
1454 | atmel_aes_fn_t resume); | |
1455 | static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd); | |
1456 | static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd); | |
1457 | ||
1458 | static int atmel_aes_gcm_start(struct atmel_aes_dev *dd); | |
1459 | static int atmel_aes_gcm_process(struct atmel_aes_dev *dd); | |
1460 | static int atmel_aes_gcm_length(struct atmel_aes_dev *dd); | |
1461 | static int atmel_aes_gcm_data(struct atmel_aes_dev *dd); | |
1462 | static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd); | |
1463 | static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd); | |
1464 | static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd); | |
1465 | ||
1466 | static inline struct atmel_aes_gcm_ctx * | |
1467 | atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx) | |
1468 | { | |
1469 | return container_of(ctx, struct atmel_aes_gcm_ctx, base); | |
1470 | } | |
1471 | ||
1472 | static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd, | |
1473 | const u32 *data, size_t datalen, | |
1474 | const u32 *ghash_in, u32 *ghash_out, | |
1475 | atmel_aes_fn_t resume) | |
1476 | { | |
1477 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1478 | ||
1479 | dd->data = (u32 *)data; | |
1480 | dd->datalen = datalen; | |
1481 | ctx->ghash_in = ghash_in; | |
1482 | ctx->ghash_out = ghash_out; | |
1483 | ctx->ghash_resume = resume; | |
1484 | ||
1485 | atmel_aes_write_ctrl(dd, false, NULL); | |
1486 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init); | |
1487 | } | |
1488 | ||
1489 | static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd) | |
1490 | { | |
1491 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1492 | ||
1493 | /* Set the data length. */ | |
1494 | atmel_aes_write(dd, AES_AADLENR, dd->total); | |
1495 | atmel_aes_write(dd, AES_CLENR, 0); | |
1496 | ||
1497 | /* If needed, overwrite the GCM Intermediate Hash Word Registers */ | |
1498 | if (ctx->ghash_in) | |
1499 | atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in); | |
1500 | ||
1501 | return atmel_aes_gcm_ghash_finalize(dd); | |
1502 | } | |
1503 | ||
1504 | static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd) | |
1505 | { | |
1506 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1507 | u32 isr; | |
1508 | ||
1509 | /* Write data into the Input Data Registers. */ | |
1510 | while (dd->datalen > 0) { | |
1511 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
1512 | dd->data += 4; | |
1513 | dd->datalen -= AES_BLOCK_SIZE; | |
1514 | ||
1515 | isr = atmel_aes_read(dd, AES_ISR); | |
1516 | if (!(isr & AES_INT_DATARDY)) { | |
1517 | dd->resume = atmel_aes_gcm_ghash_finalize; | |
1518 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
1519 | return -EINPROGRESS; | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /* Read the computed hash from GHASHRx. */ | |
1524 | atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out); | |
1525 | ||
1526 | return ctx->ghash_resume(dd); | |
1527 | } | |
1528 | ||
1529 | ||
1530 | static int atmel_aes_gcm_start(struct atmel_aes_dev *dd) | |
1531 | { | |
1532 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1533 | struct aead_request *req = aead_request_cast(dd->areq); | |
1534 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1535 | struct atmel_aes_reqctx *rctx = aead_request_ctx(req); | |
1536 | size_t ivsize = crypto_aead_ivsize(tfm); | |
1537 | size_t datalen, padlen; | |
1538 | const void *iv = req->iv; | |
1539 | u8 *data = dd->buf; | |
1540 | int err; | |
1541 | ||
1542 | atmel_aes_set_mode(dd, rctx); | |
1543 | ||
1544 | err = atmel_aes_hw_init(dd); | |
1545 | if (err) | |
1546 | return atmel_aes_complete(dd, err); | |
1547 | ||
219d51c7 | 1548 | if (likely(ivsize == GCM_AES_IV_SIZE)) { |
d4419548 CP |
1549 | memcpy(ctx->j0, iv, ivsize); |
1550 | ctx->j0[3] = cpu_to_be32(1); | |
1551 | return atmel_aes_gcm_process(dd); | |
1552 | } | |
1553 | ||
1554 | padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE); | |
1555 | datalen = ivsize + padlen + AES_BLOCK_SIZE; | |
1556 | if (datalen > dd->buflen) | |
1557 | return atmel_aes_complete(dd, -EINVAL); | |
1558 | ||
1559 | memcpy(data, iv, ivsize); | |
1560 | memset(data + ivsize, 0, padlen + sizeof(u64)); | |
1561 | ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8); | |
1562 | ||
1563 | return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen, | |
1564 | NULL, ctx->j0, atmel_aes_gcm_process); | |
1565 | } | |
1566 | ||
1567 | static int atmel_aes_gcm_process(struct atmel_aes_dev *dd) | |
1568 | { | |
1569 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1570 | struct aead_request *req = aead_request_cast(dd->areq); | |
1571 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1572 | bool enc = atmel_aes_is_encrypt(dd); | |
1573 | u32 authsize; | |
1574 | ||
1575 | /* Compute text length. */ | |
1576 | authsize = crypto_aead_authsize(tfm); | |
1577 | ctx->textlen = req->cryptlen - (enc ? 0 : authsize); | |
1578 | ||
1579 | /* | |
1580 | * According to tcrypt test suite, the GCM Automatic Tag Generation | |
1581 | * fails when both the message and its associated data are empty. | |
1582 | */ | |
1583 | if (likely(req->assoclen != 0 || ctx->textlen != 0)) | |
1584 | dd->flags |= AES_FLAGS_GTAGEN; | |
1585 | ||
1586 | atmel_aes_write_ctrl(dd, false, NULL); | |
1587 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length); | |
1588 | } | |
1589 | ||
1590 | static int atmel_aes_gcm_length(struct atmel_aes_dev *dd) | |
1591 | { | |
1592 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1593 | struct aead_request *req = aead_request_cast(dd->areq); | |
1594 | u32 j0_lsw, *j0 = ctx->j0; | |
1595 | size_t padlen; | |
1596 | ||
1597 | /* Write incr32(J0) into IV. */ | |
1598 | j0_lsw = j0[3]; | |
1599 | j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1); | |
1600 | atmel_aes_write_block(dd, AES_IVR(0), j0); | |
1601 | j0[3] = j0_lsw; | |
1602 | ||
1603 | /* Set aad and text lengths. */ | |
1604 | atmel_aes_write(dd, AES_AADLENR, req->assoclen); | |
1605 | atmel_aes_write(dd, AES_CLENR, ctx->textlen); | |
1606 | ||
1607 | /* Check whether AAD are present. */ | |
1608 | if (unlikely(req->assoclen == 0)) { | |
1609 | dd->datalen = 0; | |
1610 | return atmel_aes_gcm_data(dd); | |
1611 | } | |
1612 | ||
1613 | /* Copy assoc data and add padding. */ | |
1614 | padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE); | |
1615 | if (unlikely(req->assoclen + padlen > dd->buflen)) | |
1616 | return atmel_aes_complete(dd, -EINVAL); | |
1617 | sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen); | |
1618 | ||
1619 | /* Write assoc data into the Input Data register. */ | |
1620 | dd->data = (u32 *)dd->buf; | |
1621 | dd->datalen = req->assoclen + padlen; | |
1622 | return atmel_aes_gcm_data(dd); | |
1623 | } | |
1624 | ||
1625 | static int atmel_aes_gcm_data(struct atmel_aes_dev *dd) | |
1626 | { | |
1627 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1628 | struct aead_request *req = aead_request_cast(dd->areq); | |
1629 | bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD); | |
1630 | struct scatterlist *src, *dst; | |
1631 | u32 isr, mr; | |
1632 | ||
1633 | /* Write AAD first. */ | |
1634 | while (dd->datalen > 0) { | |
1635 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
1636 | dd->data += 4; | |
1637 | dd->datalen -= AES_BLOCK_SIZE; | |
1638 | ||
1639 | isr = atmel_aes_read(dd, AES_ISR); | |
1640 | if (!(isr & AES_INT_DATARDY)) { | |
1641 | dd->resume = atmel_aes_gcm_data; | |
1642 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
1643 | return -EINPROGRESS; | |
1644 | } | |
1645 | } | |
1646 | ||
1647 | /* GMAC only. */ | |
1648 | if (unlikely(ctx->textlen == 0)) | |
1649 | return atmel_aes_gcm_tag_init(dd); | |
1650 | ||
1651 | /* Prepare src and dst scatter lists to transfer cipher/plain texts */ | |
1652 | src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen); | |
1653 | dst = ((req->src == req->dst) ? src : | |
1654 | scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen)); | |
1655 | ||
1656 | if (use_dma) { | |
1657 | /* Update the Mode Register for DMA transfers. */ | |
1658 | mr = atmel_aes_read(dd, AES_MR); | |
1659 | mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF); | |
1660 | mr |= AES_MR_SMOD_IDATAR0; | |
1661 | if (dd->caps.has_dualbuff) | |
1662 | mr |= AES_MR_DUALBUFF; | |
1663 | atmel_aes_write(dd, AES_MR, mr); | |
1664 | ||
1665 | return atmel_aes_dma_start(dd, src, dst, ctx->textlen, | |
1666 | atmel_aes_gcm_tag_init); | |
1667 | } | |
1668 | ||
1669 | return atmel_aes_cpu_start(dd, src, dst, ctx->textlen, | |
1670 | atmel_aes_gcm_tag_init); | |
1671 | } | |
1672 | ||
1673 | static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd) | |
1674 | { | |
1675 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1676 | struct aead_request *req = aead_request_cast(dd->areq); | |
1677 | u64 *data = dd->buf; | |
1678 | ||
1679 | if (likely(dd->flags & AES_FLAGS_GTAGEN)) { | |
1680 | if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) { | |
1681 | dd->resume = atmel_aes_gcm_tag_init; | |
1682 | atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY); | |
1683 | return -EINPROGRESS; | |
1684 | } | |
1685 | ||
1686 | return atmel_aes_gcm_finalize(dd); | |
1687 | } | |
1688 | ||
1689 | /* Read the GCM Intermediate Hash Word Registers. */ | |
1690 | atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash); | |
1691 | ||
1692 | data[0] = cpu_to_be64(req->assoclen * 8); | |
1693 | data[1] = cpu_to_be64(ctx->textlen * 8); | |
1694 | ||
1695 | return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE, | |
1696 | ctx->ghash, ctx->ghash, atmel_aes_gcm_tag); | |
1697 | } | |
1698 | ||
1699 | static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd) | |
1700 | { | |
1701 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1702 | unsigned long flags; | |
1703 | ||
1704 | /* | |
1705 | * Change mode to CTR to complete the tag generation. | |
1706 | * Use J0 as Initialization Vector. | |
1707 | */ | |
1708 | flags = dd->flags; | |
1709 | dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN); | |
1710 | dd->flags |= AES_FLAGS_CTR; | |
1711 | atmel_aes_write_ctrl(dd, false, ctx->j0); | |
1712 | dd->flags = flags; | |
1713 | ||
1714 | atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash); | |
1715 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize); | |
1716 | } | |
1717 | ||
1718 | static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd) | |
1719 | { | |
1720 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1721 | struct aead_request *req = aead_request_cast(dd->areq); | |
1722 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1723 | bool enc = atmel_aes_is_encrypt(dd); | |
1724 | u32 offset, authsize, itag[4], *otag = ctx->tag; | |
1725 | int err; | |
1726 | ||
1727 | /* Read the computed tag. */ | |
1728 | if (likely(dd->flags & AES_FLAGS_GTAGEN)) | |
1729 | atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag); | |
1730 | else | |
1731 | atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag); | |
1732 | ||
1733 | offset = req->assoclen + ctx->textlen; | |
1734 | authsize = crypto_aead_authsize(tfm); | |
1735 | if (enc) { | |
1736 | scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1); | |
1737 | err = 0; | |
1738 | } else { | |
1739 | scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0); | |
1740 | err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0; | |
1741 | } | |
1742 | ||
1743 | return atmel_aes_complete(dd, err); | |
1744 | } | |
1745 | ||
1746 | static int atmel_aes_gcm_crypt(struct aead_request *req, | |
1747 | unsigned long mode) | |
1748 | { | |
1749 | struct atmel_aes_base_ctx *ctx; | |
1750 | struct atmel_aes_reqctx *rctx; | |
1751 | struct atmel_aes_dev *dd; | |
1752 | ||
1753 | ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); | |
1754 | ctx->block_size = AES_BLOCK_SIZE; | |
91308019 | 1755 | ctx->is_aead = true; |
d4419548 CP |
1756 | |
1757 | dd = atmel_aes_find_dev(ctx); | |
1758 | if (!dd) | |
1759 | return -ENODEV; | |
1760 | ||
1761 | rctx = aead_request_ctx(req); | |
1762 | rctx->mode = AES_FLAGS_GCM | mode; | |
1763 | ||
1764 | return atmel_aes_handle_queue(dd, &req->base); | |
1765 | } | |
1766 | ||
1767 | static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, | |
1768 | unsigned int keylen) | |
1769 | { | |
1770 | struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm); | |
1771 | ||
1772 | if (keylen != AES_KEYSIZE_256 && | |
1773 | keylen != AES_KEYSIZE_192 && | |
1774 | keylen != AES_KEYSIZE_128) { | |
1775 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
1776 | return -EINVAL; | |
1777 | } | |
1778 | ||
1779 | memcpy(ctx->key, key, keylen); | |
1780 | ctx->keylen = keylen; | |
1781 | ||
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm, | |
1786 | unsigned int authsize) | |
1787 | { | |
1788 | /* Same as crypto_gcm_authsize() from crypto/gcm.c */ | |
1789 | switch (authsize) { | |
1790 | case 4: | |
1791 | case 8: | |
1792 | case 12: | |
1793 | case 13: | |
1794 | case 14: | |
1795 | case 15: | |
1796 | case 16: | |
1797 | break; | |
1798 | default: | |
1799 | return -EINVAL; | |
1800 | } | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | static int atmel_aes_gcm_encrypt(struct aead_request *req) | |
1806 | { | |
1807 | return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT); | |
1808 | } | |
1809 | ||
1810 | static int atmel_aes_gcm_decrypt(struct aead_request *req) | |
1811 | { | |
1812 | return atmel_aes_gcm_crypt(req, 0); | |
1813 | } | |
1814 | ||
1815 | static int atmel_aes_gcm_init(struct crypto_aead *tfm) | |
1816 | { | |
1817 | struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm); | |
1818 | ||
1819 | crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx)); | |
1820 | ctx->base.start = atmel_aes_gcm_start; | |
1821 | ||
1822 | return 0; | |
1823 | } | |
1824 | ||
d4419548 CP |
1825 | static struct aead_alg aes_gcm_alg = { |
1826 | .setkey = atmel_aes_gcm_setkey, | |
1827 | .setauthsize = atmel_aes_gcm_setauthsize, | |
1828 | .encrypt = atmel_aes_gcm_encrypt, | |
1829 | .decrypt = atmel_aes_gcm_decrypt, | |
1830 | .init = atmel_aes_gcm_init, | |
219d51c7 | 1831 | .ivsize = GCM_AES_IV_SIZE, |
d4419548 CP |
1832 | .maxauthsize = AES_BLOCK_SIZE, |
1833 | ||
1834 | .base = { | |
1835 | .cra_name = "gcm(aes)", | |
1836 | .cra_driver_name = "atmel-gcm-aes", | |
1837 | .cra_priority = ATMEL_AES_PRIORITY, | |
1838 | .cra_flags = CRYPTO_ALG_ASYNC, | |
1839 | .cra_blocksize = 1, | |
1840 | .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx), | |
1841 | .cra_alignmask = 0xf, | |
1842 | .cra_module = THIS_MODULE, | |
1843 | }, | |
1844 | }; | |
1845 | ||
1846 | ||
d52db518 CP |
1847 | /* xts functions */ |
1848 | ||
1849 | static inline struct atmel_aes_xts_ctx * | |
1850 | atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx) | |
1851 | { | |
1852 | return container_of(ctx, struct atmel_aes_xts_ctx, base); | |
1853 | } | |
1854 | ||
1855 | static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd); | |
1856 | ||
1857 | static int atmel_aes_xts_start(struct atmel_aes_dev *dd) | |
1858 | { | |
1859 | struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx); | |
1860 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
1861 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
1862 | unsigned long flags; | |
1863 | int err; | |
1864 | ||
1865 | atmel_aes_set_mode(dd, rctx); | |
1866 | ||
1867 | err = atmel_aes_hw_init(dd); | |
1868 | if (err) | |
1869 | return atmel_aes_complete(dd, err); | |
1870 | ||
1871 | /* Compute the tweak value from req->info with ecb(aes). */ | |
1872 | flags = dd->flags; | |
1873 | dd->flags &= ~AES_FLAGS_MODE_MASK; | |
1874 | dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT); | |
1875 | atmel_aes_write_ctrl_key(dd, false, NULL, | |
1876 | ctx->key2, ctx->base.keylen); | |
1877 | dd->flags = flags; | |
1878 | ||
1879 | atmel_aes_write_block(dd, AES_IDATAR(0), req->info); | |
1880 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data); | |
1881 | } | |
1882 | ||
1883 | static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd) | |
1884 | { | |
1885 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
1886 | bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD); | |
1887 | u32 tweak[AES_BLOCK_SIZE / sizeof(u32)]; | |
1888 | static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), }; | |
1889 | u8 *tweak_bytes = (u8 *)tweak; | |
1890 | int i; | |
1891 | ||
1892 | /* Read the computed ciphered tweak value. */ | |
1893 | atmel_aes_read_block(dd, AES_ODATAR(0), tweak); | |
1894 | /* | |
1895 | * Hardware quirk: | |
1896 | * the order of the ciphered tweak bytes need to be reversed before | |
1897 | * writing them into the ODATARx registers. | |
1898 | */ | |
1899 | for (i = 0; i < AES_BLOCK_SIZE/2; ++i) { | |
1900 | u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i]; | |
1901 | ||
1902 | tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i]; | |
1903 | tweak_bytes[i] = tmp; | |
1904 | } | |
1905 | ||
1906 | /* Process the data. */ | |
1907 | atmel_aes_write_ctrl(dd, use_dma, NULL); | |
1908 | atmel_aes_write_block(dd, AES_TWR(0), tweak); | |
1909 | atmel_aes_write_block(dd, AES_ALPHAR(0), one); | |
1910 | if (use_dma) | |
1911 | return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes, | |
1912 | atmel_aes_transfer_complete); | |
1913 | ||
1914 | return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes, | |
1915 | atmel_aes_transfer_complete); | |
1916 | } | |
1917 | ||
1918 | static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
1919 | unsigned int keylen) | |
1920 | { | |
1921 | struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
1922 | int err; | |
1923 | ||
1924 | err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen); | |
1925 | if (err) | |
1926 | return err; | |
1927 | ||
1928 | memcpy(ctx->base.key, key, keylen/2); | |
1929 | memcpy(ctx->key2, key + keylen/2, keylen/2); | |
1930 | ctx->base.keylen = keylen/2; | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | static int atmel_aes_xts_encrypt(struct ablkcipher_request *req) | |
1936 | { | |
1937 | return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT); | |
1938 | } | |
1939 | ||
1940 | static int atmel_aes_xts_decrypt(struct ablkcipher_request *req) | |
1941 | { | |
1942 | return atmel_aes_crypt(req, AES_FLAGS_XTS); | |
1943 | } | |
1944 | ||
1945 | static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm) | |
1946 | { | |
1947 | struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm); | |
1948 | ||
1949 | tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx); | |
1950 | ctx->base.start = atmel_aes_xts_start; | |
1951 | ||
1952 | return 0; | |
1953 | } | |
1954 | ||
1955 | static struct crypto_alg aes_xts_alg = { | |
1956 | .cra_name = "xts(aes)", | |
1957 | .cra_driver_name = "atmel-xts-aes", | |
1958 | .cra_priority = ATMEL_AES_PRIORITY, | |
1959 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, | |
1960 | .cra_blocksize = AES_BLOCK_SIZE, | |
1961 | .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx), | |
1962 | .cra_alignmask = 0xf, | |
1963 | .cra_type = &crypto_ablkcipher_type, | |
1964 | .cra_module = THIS_MODULE, | |
1965 | .cra_init = atmel_aes_xts_cra_init, | |
d52db518 CP |
1966 | .cra_u.ablkcipher = { |
1967 | .min_keysize = 2 * AES_MIN_KEY_SIZE, | |
1968 | .max_keysize = 2 * AES_MAX_KEY_SIZE, | |
1969 | .ivsize = AES_BLOCK_SIZE, | |
1970 | .setkey = atmel_aes_xts_setkey, | |
1971 | .encrypt = atmel_aes_xts_encrypt, | |
1972 | .decrypt = atmel_aes_xts_decrypt, | |
1973 | } | |
1974 | }; | |
1975 | ||
89a82ef8 CP |
1976 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
1977 | /* authenc aead functions */ | |
1978 | ||
1979 | static int atmel_aes_authenc_start(struct atmel_aes_dev *dd); | |
1980 | static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err, | |
1981 | bool is_async); | |
1982 | static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err, | |
1983 | bool is_async); | |
1984 | static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd); | |
1985 | static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err, | |
1986 | bool is_async); | |
1987 | ||
1988 | static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err) | |
1989 | { | |
1990 | struct aead_request *req = aead_request_cast(dd->areq); | |
1991 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
1992 | ||
1993 | if (err && (dd->flags & AES_FLAGS_OWN_SHA)) | |
1994 | atmel_sha_authenc_abort(&rctx->auth_req); | |
1995 | dd->flags &= ~AES_FLAGS_OWN_SHA; | |
1996 | } | |
1997 | ||
1998 | static int atmel_aes_authenc_start(struct atmel_aes_dev *dd) | |
1999 | { | |
2000 | struct aead_request *req = aead_request_cast(dd->areq); | |
2001 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2002 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
2003 | struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm); | |
2004 | int err; | |
2005 | ||
2006 | atmel_aes_set_mode(dd, &rctx->base); | |
2007 | ||
2008 | err = atmel_aes_hw_init(dd); | |
2009 | if (err) | |
2010 | return atmel_aes_complete(dd, err); | |
2011 | ||
2012 | return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth, | |
2013 | atmel_aes_authenc_init, dd); | |
2014 | } | |
2015 | ||
2016 | static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err, | |
2017 | bool is_async) | |
2018 | { | |
2019 | struct aead_request *req = aead_request_cast(dd->areq); | |
2020 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2021 | ||
2022 | if (is_async) | |
2023 | dd->is_async = true; | |
2024 | if (err) | |
2025 | return atmel_aes_complete(dd, err); | |
2026 | ||
2027 | /* If here, we've got the ownership of the SHA device. */ | |
2028 | dd->flags |= AES_FLAGS_OWN_SHA; | |
2029 | ||
2030 | /* Configure the SHA device. */ | |
2031 | return atmel_sha_authenc_init(&rctx->auth_req, | |
2032 | req->src, req->assoclen, | |
2033 | rctx->textlen, | |
2034 | atmel_aes_authenc_transfer, dd); | |
2035 | } | |
2036 | ||
2037 | static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err, | |
2038 | bool is_async) | |
2039 | { | |
2040 | struct aead_request *req = aead_request_cast(dd->areq); | |
2041 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2042 | bool enc = atmel_aes_is_encrypt(dd); | |
2043 | struct scatterlist *src, *dst; | |
2044 | u32 iv[AES_BLOCK_SIZE / sizeof(u32)]; | |
2045 | u32 emr; | |
2046 | ||
2047 | if (is_async) | |
2048 | dd->is_async = true; | |
2049 | if (err) | |
2050 | return atmel_aes_complete(dd, err); | |
2051 | ||
2052 | /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */ | |
2053 | src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen); | |
2054 | dst = src; | |
2055 | ||
2056 | if (req->src != req->dst) | |
2057 | dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen); | |
2058 | ||
2059 | /* Configure the AES device. */ | |
2060 | memcpy(iv, req->iv, sizeof(iv)); | |
2061 | ||
2062 | /* | |
2063 | * Here we always set the 2nd parameter of atmel_aes_write_ctrl() to | |
2064 | * 'true' even if the data transfer is actually performed by the CPU (so | |
2065 | * not by the DMA) because we must force the AES_MR_SMOD bitfield to the | |
2066 | * value AES_MR_SMOD_IDATAR0. Indeed, both AES_MR_SMOD and SHA_MR_SMOD | |
2067 | * must be set to *_MR_SMOD_IDATAR0. | |
2068 | */ | |
2069 | atmel_aes_write_ctrl(dd, true, iv); | |
2070 | emr = AES_EMR_PLIPEN; | |
2071 | if (!enc) | |
2072 | emr |= AES_EMR_PLIPD; | |
2073 | atmel_aes_write(dd, AES_EMR, emr); | |
2074 | ||
2075 | /* Transfer data. */ | |
2076 | return atmel_aes_dma_start(dd, src, dst, rctx->textlen, | |
2077 | atmel_aes_authenc_digest); | |
2078 | } | |
2079 | ||
2080 | static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd) | |
2081 | { | |
2082 | struct aead_request *req = aead_request_cast(dd->areq); | |
2083 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2084 | ||
2085 | /* atmel_sha_authenc_final() releases the SHA device. */ | |
2086 | dd->flags &= ~AES_FLAGS_OWN_SHA; | |
2087 | return atmel_sha_authenc_final(&rctx->auth_req, | |
2088 | rctx->digest, sizeof(rctx->digest), | |
2089 | atmel_aes_authenc_final, dd); | |
2090 | } | |
2091 | ||
2092 | static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err, | |
2093 | bool is_async) | |
2094 | { | |
2095 | struct aead_request *req = aead_request_cast(dd->areq); | |
2096 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2097 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
2098 | bool enc = atmel_aes_is_encrypt(dd); | |
2099 | u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest; | |
2100 | u32 offs, authsize; | |
2101 | ||
2102 | if (is_async) | |
2103 | dd->is_async = true; | |
2104 | if (err) | |
2105 | goto complete; | |
2106 | ||
2107 | offs = req->assoclen + rctx->textlen; | |
2108 | authsize = crypto_aead_authsize(tfm); | |
2109 | if (enc) { | |
2110 | scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1); | |
2111 | } else { | |
2112 | scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0); | |
2113 | if (crypto_memneq(idigest, odigest, authsize)) | |
2114 | err = -EBADMSG; | |
2115 | } | |
2116 | ||
2117 | complete: | |
2118 | return atmel_aes_complete(dd, err); | |
2119 | } | |
2120 | ||
2121 | static int atmel_aes_authenc_setkey(struct crypto_aead *tfm, const u8 *key, | |
2122 | unsigned int keylen) | |
2123 | { | |
2124 | struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm); | |
2125 | struct crypto_authenc_keys keys; | |
2126 | u32 flags; | |
2127 | int err; | |
2128 | ||
2129 | if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) | |
2130 | goto badkey; | |
2131 | ||
2132 | if (keys.enckeylen > sizeof(ctx->base.key)) | |
2133 | goto badkey; | |
2134 | ||
2135 | /* Save auth key. */ | |
2136 | flags = crypto_aead_get_flags(tfm); | |
2137 | err = atmel_sha_authenc_setkey(ctx->auth, | |
2138 | keys.authkey, keys.authkeylen, | |
2139 | &flags); | |
2140 | crypto_aead_set_flags(tfm, flags & CRYPTO_TFM_RES_MASK); | |
2141 | if (err) { | |
2142 | memzero_explicit(&keys, sizeof(keys)); | |
2143 | return err; | |
2144 | } | |
2145 | ||
2146 | /* Save enc key. */ | |
2147 | ctx->base.keylen = keys.enckeylen; | |
2148 | memcpy(ctx->base.key, keys.enckey, keys.enckeylen); | |
2149 | ||
2150 | memzero_explicit(&keys, sizeof(keys)); | |
2151 | return 0; | |
2152 | ||
2153 | badkey: | |
2154 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
5d804a51 | 2155 | memzero_explicit(&keys, sizeof(keys)); |
89a82ef8 CP |
2156 | return -EINVAL; |
2157 | } | |
2158 | ||
2159 | static int atmel_aes_authenc_init_tfm(struct crypto_aead *tfm, | |
2160 | unsigned long auth_mode) | |
2161 | { | |
2162 | struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm); | |
2163 | unsigned int auth_reqsize = atmel_sha_authenc_get_reqsize(); | |
2164 | ||
2165 | ctx->auth = atmel_sha_authenc_spawn(auth_mode); | |
2166 | if (IS_ERR(ctx->auth)) | |
2167 | return PTR_ERR(ctx->auth); | |
2168 | ||
2169 | crypto_aead_set_reqsize(tfm, (sizeof(struct atmel_aes_authenc_reqctx) + | |
2170 | auth_reqsize)); | |
2171 | ctx->base.start = atmel_aes_authenc_start; | |
2172 | ||
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | static int atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead *tfm) | |
2177 | { | |
2178 | return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA1); | |
2179 | } | |
2180 | ||
2181 | static int atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead *tfm) | |
2182 | { | |
2183 | return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA224); | |
2184 | } | |
2185 | ||
2186 | static int atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead *tfm) | |
2187 | { | |
2188 | return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA256); | |
2189 | } | |
2190 | ||
2191 | static int atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead *tfm) | |
2192 | { | |
2193 | return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA384); | |
2194 | } | |
2195 | ||
2196 | static int atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead *tfm) | |
2197 | { | |
2198 | return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA512); | |
2199 | } | |
2200 | ||
2201 | static void atmel_aes_authenc_exit_tfm(struct crypto_aead *tfm) | |
2202 | { | |
2203 | struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm); | |
2204 | ||
2205 | atmel_sha_authenc_free(ctx->auth); | |
2206 | } | |
2207 | ||
2208 | static int atmel_aes_authenc_crypt(struct aead_request *req, | |
2209 | unsigned long mode) | |
2210 | { | |
2211 | struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req); | |
2212 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
2213 | struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm); | |
2214 | u32 authsize = crypto_aead_authsize(tfm); | |
2215 | bool enc = (mode & AES_FLAGS_ENCRYPT); | |
2216 | struct atmel_aes_dev *dd; | |
2217 | ||
2218 | /* Compute text length. */ | |
2219 | if (!enc && req->cryptlen < authsize) | |
2220 | return -EINVAL; | |
2221 | rctx->textlen = req->cryptlen - (enc ? 0 : authsize); | |
2222 | ||
2223 | /* | |
2224 | * Currently, empty messages are not supported yet: | |
2225 | * the SHA auto-padding can be used only on non-empty messages. | |
2226 | * Hence a special case needs to be implemented for empty message. | |
2227 | */ | |
2228 | if (!rctx->textlen && !req->assoclen) | |
2229 | return -EINVAL; | |
2230 | ||
2231 | rctx->base.mode = mode; | |
2232 | ctx->block_size = AES_BLOCK_SIZE; | |
91308019 | 2233 | ctx->is_aead = true; |
89a82ef8 CP |
2234 | |
2235 | dd = atmel_aes_find_dev(ctx); | |
2236 | if (!dd) | |
2237 | return -ENODEV; | |
2238 | ||
2239 | return atmel_aes_handle_queue(dd, &req->base); | |
2240 | } | |
2241 | ||
2242 | static int atmel_aes_authenc_cbc_aes_encrypt(struct aead_request *req) | |
2243 | { | |
2244 | return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT); | |
2245 | } | |
2246 | ||
2247 | static int atmel_aes_authenc_cbc_aes_decrypt(struct aead_request *req) | |
2248 | { | |
2249 | return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC); | |
2250 | } | |
2251 | ||
2252 | static struct aead_alg aes_authenc_algs[] = { | |
2253 | { | |
2254 | .setkey = atmel_aes_authenc_setkey, | |
2255 | .encrypt = atmel_aes_authenc_cbc_aes_encrypt, | |
2256 | .decrypt = atmel_aes_authenc_cbc_aes_decrypt, | |
2257 | .init = atmel_aes_authenc_hmac_sha1_init_tfm, | |
2258 | .exit = atmel_aes_authenc_exit_tfm, | |
2259 | .ivsize = AES_BLOCK_SIZE, | |
2260 | .maxauthsize = SHA1_DIGEST_SIZE, | |
2261 | ||
2262 | .base = { | |
2263 | .cra_name = "authenc(hmac(sha1),cbc(aes))", | |
2264 | .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes", | |
2265 | .cra_priority = ATMEL_AES_PRIORITY, | |
2266 | .cra_flags = CRYPTO_ALG_ASYNC, | |
2267 | .cra_blocksize = AES_BLOCK_SIZE, | |
2268 | .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), | |
2269 | .cra_alignmask = 0xf, | |
2270 | .cra_module = THIS_MODULE, | |
2271 | }, | |
2272 | }, | |
2273 | { | |
2274 | .setkey = atmel_aes_authenc_setkey, | |
2275 | .encrypt = atmel_aes_authenc_cbc_aes_encrypt, | |
2276 | .decrypt = atmel_aes_authenc_cbc_aes_decrypt, | |
2277 | .init = atmel_aes_authenc_hmac_sha224_init_tfm, | |
2278 | .exit = atmel_aes_authenc_exit_tfm, | |
2279 | .ivsize = AES_BLOCK_SIZE, | |
2280 | .maxauthsize = SHA224_DIGEST_SIZE, | |
2281 | ||
2282 | .base = { | |
2283 | .cra_name = "authenc(hmac(sha224),cbc(aes))", | |
2284 | .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes", | |
2285 | .cra_priority = ATMEL_AES_PRIORITY, | |
2286 | .cra_flags = CRYPTO_ALG_ASYNC, | |
2287 | .cra_blocksize = AES_BLOCK_SIZE, | |
2288 | .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), | |
2289 | .cra_alignmask = 0xf, | |
2290 | .cra_module = THIS_MODULE, | |
2291 | }, | |
2292 | }, | |
2293 | { | |
2294 | .setkey = atmel_aes_authenc_setkey, | |
2295 | .encrypt = atmel_aes_authenc_cbc_aes_encrypt, | |
2296 | .decrypt = atmel_aes_authenc_cbc_aes_decrypt, | |
2297 | .init = atmel_aes_authenc_hmac_sha256_init_tfm, | |
2298 | .exit = atmel_aes_authenc_exit_tfm, | |
2299 | .ivsize = AES_BLOCK_SIZE, | |
2300 | .maxauthsize = SHA256_DIGEST_SIZE, | |
2301 | ||
2302 | .base = { | |
2303 | .cra_name = "authenc(hmac(sha256),cbc(aes))", | |
2304 | .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes", | |
2305 | .cra_priority = ATMEL_AES_PRIORITY, | |
2306 | .cra_flags = CRYPTO_ALG_ASYNC, | |
2307 | .cra_blocksize = AES_BLOCK_SIZE, | |
2308 | .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), | |
2309 | .cra_alignmask = 0xf, | |
2310 | .cra_module = THIS_MODULE, | |
2311 | }, | |
2312 | }, | |
2313 | { | |
2314 | .setkey = atmel_aes_authenc_setkey, | |
2315 | .encrypt = atmel_aes_authenc_cbc_aes_encrypt, | |
2316 | .decrypt = atmel_aes_authenc_cbc_aes_decrypt, | |
2317 | .init = atmel_aes_authenc_hmac_sha384_init_tfm, | |
2318 | .exit = atmel_aes_authenc_exit_tfm, | |
2319 | .ivsize = AES_BLOCK_SIZE, | |
2320 | .maxauthsize = SHA384_DIGEST_SIZE, | |
2321 | ||
2322 | .base = { | |
2323 | .cra_name = "authenc(hmac(sha384),cbc(aes))", | |
2324 | .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes", | |
2325 | .cra_priority = ATMEL_AES_PRIORITY, | |
2326 | .cra_flags = CRYPTO_ALG_ASYNC, | |
2327 | .cra_blocksize = AES_BLOCK_SIZE, | |
2328 | .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), | |
2329 | .cra_alignmask = 0xf, | |
2330 | .cra_module = THIS_MODULE, | |
2331 | }, | |
2332 | }, | |
2333 | { | |
2334 | .setkey = atmel_aes_authenc_setkey, | |
2335 | .encrypt = atmel_aes_authenc_cbc_aes_encrypt, | |
2336 | .decrypt = atmel_aes_authenc_cbc_aes_decrypt, | |
2337 | .init = atmel_aes_authenc_hmac_sha512_init_tfm, | |
2338 | .exit = atmel_aes_authenc_exit_tfm, | |
2339 | .ivsize = AES_BLOCK_SIZE, | |
2340 | .maxauthsize = SHA512_DIGEST_SIZE, | |
2341 | ||
2342 | .base = { | |
2343 | .cra_name = "authenc(hmac(sha512),cbc(aes))", | |
2344 | .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes", | |
2345 | .cra_priority = ATMEL_AES_PRIORITY, | |
2346 | .cra_flags = CRYPTO_ALG_ASYNC, | |
2347 | .cra_blocksize = AES_BLOCK_SIZE, | |
2348 | .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), | |
2349 | .cra_alignmask = 0xf, | |
2350 | .cra_module = THIS_MODULE, | |
2351 | }, | |
2352 | }, | |
2353 | }; | |
2354 | #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */ | |
d52db518 | 2355 | |
e37a7e55 CP |
2356 | /* Probe functions */ |
2357 | ||
2358 | static int atmel_aes_buff_init(struct atmel_aes_dev *dd) | |
2359 | { | |
2360 | dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER); | |
2361 | dd->buflen = ATMEL_AES_BUFFER_SIZE; | |
2362 | dd->buflen &= ~(AES_BLOCK_SIZE - 1); | |
2363 | ||
2364 | if (!dd->buf) { | |
2365 | dev_err(dd->dev, "unable to alloc pages.\n"); | |
2366 | return -ENOMEM; | |
2367 | } | |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd) | |
2373 | { | |
2374 | free_page((unsigned long)dd->buf); | |
2375 | } | |
2376 | ||
2377 | static bool atmel_aes_filter(struct dma_chan *chan, void *slave) | |
2378 | { | |
2379 | struct at_dma_slave *sl = slave; | |
2380 | ||
2381 | if (sl && sl->dma_dev == chan->device->dev) { | |
2382 | chan->private = sl; | |
2383 | return true; | |
2384 | } else { | |
2385 | return false; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | static int atmel_aes_dma_init(struct atmel_aes_dev *dd, | |
2390 | struct crypto_platform_data *pdata) | |
2391 | { | |
2392 | struct at_dma_slave *slave; | |
e37a7e55 CP |
2393 | dma_cap_mask_t mask; |
2394 | ||
2395 | dma_cap_zero(mask); | |
2396 | dma_cap_set(DMA_SLAVE, mask); | |
2397 | ||
2398 | /* Try to grab 2 DMA channels */ | |
2399 | slave = &pdata->dma_slave->rxdata; | |
2400 | dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, | |
2401 | slave, dd->dev, "tx"); | |
2402 | if (!dd->src.chan) | |
2403 | goto err_dma_in; | |
2404 | ||
2405 | slave = &pdata->dma_slave->txdata; | |
2406 | dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, | |
2407 | slave, dd->dev, "rx"); | |
2408 | if (!dd->dst.chan) | |
2409 | goto err_dma_out; | |
2410 | ||
2411 | return 0; | |
2412 | ||
2413 | err_dma_out: | |
2414 | dma_release_channel(dd->src.chan); | |
2415 | err_dma_in: | |
2416 | dev_warn(dd->dev, "no DMA channel available\n"); | |
3c88761e | 2417 | return -ENODEV; |
e37a7e55 CP |
2418 | } |
2419 | ||
2420 | static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd) | |
2421 | { | |
2422 | dma_release_channel(dd->dst.chan); | |
2423 | dma_release_channel(dd->src.chan); | |
2424 | } | |
2425 | ||
bd3c7b5c NR |
2426 | static void atmel_aes_queue_task(unsigned long data) |
2427 | { | |
2428 | struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data; | |
2429 | ||
2430 | atmel_aes_handle_queue(dd, NULL); | |
2431 | } | |
2432 | ||
2433 | static void atmel_aes_done_task(unsigned long data) | |
2434 | { | |
afbac17e | 2435 | struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data; |
bd3c7b5c | 2436 | |
10f12c1b CP |
2437 | dd->is_async = true; |
2438 | (void)dd->resume(dd); | |
2439 | } | |
bd3c7b5c | 2440 | |
bd3c7b5c NR |
2441 | static irqreturn_t atmel_aes_irq(int irq, void *dev_id) |
2442 | { | |
2443 | struct atmel_aes_dev *aes_dd = dev_id; | |
2444 | u32 reg; | |
2445 | ||
2446 | reg = atmel_aes_read(aes_dd, AES_ISR); | |
2447 | if (reg & atmel_aes_read(aes_dd, AES_IMR)) { | |
2448 | atmel_aes_write(aes_dd, AES_IDR, reg); | |
2449 | if (AES_FLAGS_BUSY & aes_dd->flags) | |
2450 | tasklet_schedule(&aes_dd->done_task); | |
2451 | else | |
2452 | dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n"); | |
2453 | return IRQ_HANDLED; | |
2454 | } | |
2455 | ||
2456 | return IRQ_NONE; | |
2457 | } | |
2458 | ||
2459 | static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd) | |
2460 | { | |
2461 | int i; | |
2462 | ||
89a82ef8 CP |
2463 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
2464 | if (dd->caps.has_authenc) | |
2465 | for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) | |
2466 | crypto_unregister_aead(&aes_authenc_algs[i]); | |
2467 | #endif | |
2468 | ||
d52db518 CP |
2469 | if (dd->caps.has_xts) |
2470 | crypto_unregister_alg(&aes_xts_alg); | |
2471 | ||
d4419548 CP |
2472 | if (dd->caps.has_gcm) |
2473 | crypto_unregister_aead(&aes_gcm_alg); | |
2474 | ||
cadc4ab8 NR |
2475 | if (dd->caps.has_cfb64) |
2476 | crypto_unregister_alg(&aes_cfb64_alg); | |
924a8bc7 CP |
2477 | |
2478 | for (i = 0; i < ARRAY_SIZE(aes_algs); i++) | |
2479 | crypto_unregister_alg(&aes_algs[i]); | |
bd3c7b5c NR |
2480 | } |
2481 | ||
2482 | static int atmel_aes_register_algs(struct atmel_aes_dev *dd) | |
2483 | { | |
2484 | int err, i, j; | |
2485 | ||
2486 | for (i = 0; i < ARRAY_SIZE(aes_algs); i++) { | |
bd3c7b5c NR |
2487 | err = crypto_register_alg(&aes_algs[i]); |
2488 | if (err) | |
2489 | goto err_aes_algs; | |
2490 | } | |
2491 | ||
cadc4ab8 NR |
2492 | if (dd->caps.has_cfb64) { |
2493 | err = crypto_register_alg(&aes_cfb64_alg); | |
bd3c7b5c NR |
2494 | if (err) |
2495 | goto err_aes_cfb64_alg; | |
2496 | } | |
2497 | ||
d4419548 CP |
2498 | if (dd->caps.has_gcm) { |
2499 | err = crypto_register_aead(&aes_gcm_alg); | |
2500 | if (err) | |
2501 | goto err_aes_gcm_alg; | |
2502 | } | |
2503 | ||
d52db518 CP |
2504 | if (dd->caps.has_xts) { |
2505 | err = crypto_register_alg(&aes_xts_alg); | |
2506 | if (err) | |
2507 | goto err_aes_xts_alg; | |
2508 | } | |
2509 | ||
89a82ef8 CP |
2510 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
2511 | if (dd->caps.has_authenc) { | |
2512 | for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) { | |
2513 | err = crypto_register_aead(&aes_authenc_algs[i]); | |
2514 | if (err) | |
2515 | goto err_aes_authenc_alg; | |
2516 | } | |
2517 | } | |
2518 | #endif | |
2519 | ||
bd3c7b5c NR |
2520 | return 0; |
2521 | ||
89a82ef8 CP |
2522 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
2523 | /* i = ARRAY_SIZE(aes_authenc_algs); */ | |
2524 | err_aes_authenc_alg: | |
2525 | for (j = 0; j < i; j++) | |
2526 | crypto_unregister_aead(&aes_authenc_algs[j]); | |
2527 | crypto_unregister_alg(&aes_xts_alg); | |
2528 | #endif | |
d52db518 CP |
2529 | err_aes_xts_alg: |
2530 | crypto_unregister_aead(&aes_gcm_alg); | |
d4419548 CP |
2531 | err_aes_gcm_alg: |
2532 | crypto_unregister_alg(&aes_cfb64_alg); | |
bd3c7b5c NR |
2533 | err_aes_cfb64_alg: |
2534 | i = ARRAY_SIZE(aes_algs); | |
2535 | err_aes_algs: | |
2536 | for (j = 0; j < i; j++) | |
2537 | crypto_unregister_alg(&aes_algs[j]); | |
2538 | ||
2539 | return err; | |
2540 | } | |
2541 | ||
cadc4ab8 NR |
2542 | static void atmel_aes_get_cap(struct atmel_aes_dev *dd) |
2543 | { | |
2544 | dd->caps.has_dualbuff = 0; | |
2545 | dd->caps.has_cfb64 = 0; | |
fcac8365 | 2546 | dd->caps.has_ctr32 = 0; |
d4419548 | 2547 | dd->caps.has_gcm = 0; |
d52db518 | 2548 | dd->caps.has_xts = 0; |
89a82ef8 | 2549 | dd->caps.has_authenc = 0; |
cadc4ab8 NR |
2550 | dd->caps.max_burst_size = 1; |
2551 | ||
2552 | /* keep only major version number */ | |
2553 | switch (dd->hw_version & 0xff0) { | |
973e209d LZ |
2554 | case 0x500: |
2555 | dd->caps.has_dualbuff = 1; | |
2556 | dd->caps.has_cfb64 = 1; | |
fcac8365 | 2557 | dd->caps.has_ctr32 = 1; |
d4419548 | 2558 | dd->caps.has_gcm = 1; |
d52db518 | 2559 | dd->caps.has_xts = 1; |
89a82ef8 | 2560 | dd->caps.has_authenc = 1; |
973e209d LZ |
2561 | dd->caps.max_burst_size = 4; |
2562 | break; | |
cf1f0d12 LZ |
2563 | case 0x200: |
2564 | dd->caps.has_dualbuff = 1; | |
2565 | dd->caps.has_cfb64 = 1; | |
fcac8365 | 2566 | dd->caps.has_ctr32 = 1; |
d4419548 | 2567 | dd->caps.has_gcm = 1; |
cf1f0d12 LZ |
2568 | dd->caps.max_burst_size = 4; |
2569 | break; | |
cadc4ab8 NR |
2570 | case 0x130: |
2571 | dd->caps.has_dualbuff = 1; | |
2572 | dd->caps.has_cfb64 = 1; | |
2573 | dd->caps.max_burst_size = 4; | |
2574 | break; | |
2575 | case 0x120: | |
2576 | break; | |
2577 | default: | |
2578 | dev_warn(dd->dev, | |
2579 | "Unmanaged aes version, set minimum capabilities\n"); | |
2580 | break; | |
2581 | } | |
2582 | } | |
2583 | ||
be943c7d NF |
2584 | #if defined(CONFIG_OF) |
2585 | static const struct of_device_id atmel_aes_dt_ids[] = { | |
2586 | { .compatible = "atmel,at91sam9g46-aes" }, | |
2587 | { /* sentinel */ } | |
2588 | }; | |
2589 | MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids); | |
2590 | ||
2591 | static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | |
2592 | { | |
2593 | struct device_node *np = pdev->dev.of_node; | |
2594 | struct crypto_platform_data *pdata; | |
2595 | ||
2596 | if (!np) { | |
2597 | dev_err(&pdev->dev, "device node not found\n"); | |
2598 | return ERR_PTR(-EINVAL); | |
2599 | } | |
2600 | ||
2601 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
02684839 | 2602 | if (!pdata) |
be943c7d | 2603 | return ERR_PTR(-ENOMEM); |
be943c7d NF |
2604 | |
2605 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | |
2606 | sizeof(*(pdata->dma_slave)), | |
2607 | GFP_KERNEL); | |
2608 | if (!pdata->dma_slave) { | |
be943c7d NF |
2609 | devm_kfree(&pdev->dev, pdata); |
2610 | return ERR_PTR(-ENOMEM); | |
2611 | } | |
2612 | ||
2613 | return pdata; | |
2614 | } | |
2615 | #else | |
2616 | static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | |
2617 | { | |
2618 | return ERR_PTR(-EINVAL); | |
2619 | } | |
2620 | #endif | |
2621 | ||
49cfe4db | 2622 | static int atmel_aes_probe(struct platform_device *pdev) |
bd3c7b5c NR |
2623 | { |
2624 | struct atmel_aes_dev *aes_dd; | |
cadc4ab8 | 2625 | struct crypto_platform_data *pdata; |
bd3c7b5c NR |
2626 | struct device *dev = &pdev->dev; |
2627 | struct resource *aes_res; | |
bd3c7b5c NR |
2628 | int err; |
2629 | ||
2630 | pdata = pdev->dev.platform_data; | |
2631 | if (!pdata) { | |
be943c7d NF |
2632 | pdata = atmel_aes_of_init(pdev); |
2633 | if (IS_ERR(pdata)) { | |
2634 | err = PTR_ERR(pdata); | |
2635 | goto aes_dd_err; | |
2636 | } | |
2637 | } | |
2638 | ||
2639 | if (!pdata->dma_slave) { | |
bd3c7b5c NR |
2640 | err = -ENXIO; |
2641 | goto aes_dd_err; | |
2642 | } | |
2643 | ||
b0e8b341 | 2644 | aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL); |
bd3c7b5c | 2645 | if (aes_dd == NULL) { |
bd3c7b5c NR |
2646 | err = -ENOMEM; |
2647 | goto aes_dd_err; | |
2648 | } | |
2649 | ||
2650 | aes_dd->dev = dev; | |
2651 | ||
2652 | platform_set_drvdata(pdev, aes_dd); | |
2653 | ||
2654 | INIT_LIST_HEAD(&aes_dd->list); | |
8a10eb8d | 2655 | spin_lock_init(&aes_dd->lock); |
bd3c7b5c NR |
2656 | |
2657 | tasklet_init(&aes_dd->done_task, atmel_aes_done_task, | |
2658 | (unsigned long)aes_dd); | |
2659 | tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task, | |
2660 | (unsigned long)aes_dd); | |
2661 | ||
2662 | crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH); | |
2663 | ||
bd3c7b5c NR |
2664 | /* Get the base address */ |
2665 | aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2666 | if (!aes_res) { | |
2667 | dev_err(dev, "no MEM resource info\n"); | |
2668 | err = -ENODEV; | |
2669 | goto res_err; | |
2670 | } | |
2671 | aes_dd->phys_base = aes_res->start; | |
bd3c7b5c NR |
2672 | |
2673 | /* Get the IRQ */ | |
2674 | aes_dd->irq = platform_get_irq(pdev, 0); | |
2675 | if (aes_dd->irq < 0) { | |
2676 | dev_err(dev, "no IRQ resource info\n"); | |
2677 | err = aes_dd->irq; | |
b0e8b341 | 2678 | goto res_err; |
bd3c7b5c NR |
2679 | } |
2680 | ||
b0e8b341 LC |
2681 | err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq, |
2682 | IRQF_SHARED, "atmel-aes", aes_dd); | |
bd3c7b5c NR |
2683 | if (err) { |
2684 | dev_err(dev, "unable to request aes irq.\n"); | |
b0e8b341 | 2685 | goto res_err; |
bd3c7b5c NR |
2686 | } |
2687 | ||
2688 | /* Initializing the clock */ | |
b0e8b341 | 2689 | aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk"); |
bd3c7b5c | 2690 | if (IS_ERR(aes_dd->iclk)) { |
be208356 | 2691 | dev_err(dev, "clock initialization failed.\n"); |
bd3c7b5c | 2692 | err = PTR_ERR(aes_dd->iclk); |
b0e8b341 | 2693 | goto res_err; |
bd3c7b5c NR |
2694 | } |
2695 | ||
b0e8b341 | 2696 | aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res); |
9b52d55f | 2697 | if (IS_ERR(aes_dd->io_base)) { |
bd3c7b5c | 2698 | dev_err(dev, "can't ioremap\n"); |
9b52d55f | 2699 | err = PTR_ERR(aes_dd->io_base); |
b0e8b341 | 2700 | goto res_err; |
bd3c7b5c NR |
2701 | } |
2702 | ||
49a20454 | 2703 | err = clk_prepare(aes_dd->iclk); |
aab0a39b CP |
2704 | if (err) |
2705 | goto res_err; | |
cadc4ab8 | 2706 | |
49a20454 CP |
2707 | err = atmel_aes_hw_version_init(aes_dd); |
2708 | if (err) | |
2709 | goto iclk_unprepare; | |
2710 | ||
cadc4ab8 NR |
2711 | atmel_aes_get_cap(aes_dd); |
2712 | ||
89a82ef8 CP |
2713 | #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC |
2714 | if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) { | |
2715 | err = -EPROBE_DEFER; | |
2716 | goto iclk_unprepare; | |
2717 | } | |
2718 | #endif | |
2719 | ||
cadc4ab8 NR |
2720 | err = atmel_aes_buff_init(aes_dd); |
2721 | if (err) | |
2722 | goto err_aes_buff; | |
2723 | ||
2724 | err = atmel_aes_dma_init(aes_dd, pdata); | |
bd3c7b5c NR |
2725 | if (err) |
2726 | goto err_aes_dma; | |
2727 | ||
2728 | spin_lock(&atmel_aes.lock); | |
2729 | list_add_tail(&aes_dd->list, &atmel_aes.dev_list); | |
2730 | spin_unlock(&atmel_aes.lock); | |
2731 | ||
2732 | err = atmel_aes_register_algs(aes_dd); | |
2733 | if (err) | |
2734 | goto err_algs; | |
2735 | ||
be943c7d | 2736 | dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n", |
bbe628ed CP |
2737 | dma_chan_name(aes_dd->src.chan), |
2738 | dma_chan_name(aes_dd->dst.chan)); | |
bd3c7b5c NR |
2739 | |
2740 | return 0; | |
2741 | ||
2742 | err_algs: | |
2743 | spin_lock(&atmel_aes.lock); | |
2744 | list_del(&aes_dd->list); | |
2745 | spin_unlock(&atmel_aes.lock); | |
2746 | atmel_aes_dma_cleanup(aes_dd); | |
2747 | err_aes_dma: | |
cadc4ab8 NR |
2748 | atmel_aes_buff_cleanup(aes_dd); |
2749 | err_aes_buff: | |
49a20454 CP |
2750 | iclk_unprepare: |
2751 | clk_unprepare(aes_dd->iclk); | |
bd3c7b5c NR |
2752 | res_err: |
2753 | tasklet_kill(&aes_dd->done_task); | |
2754 | tasklet_kill(&aes_dd->queue_task); | |
bd3c7b5c | 2755 | aes_dd_err: |
89a82ef8 CP |
2756 | if (err != -EPROBE_DEFER) |
2757 | dev_err(dev, "initialization failed.\n"); | |
bd3c7b5c NR |
2758 | |
2759 | return err; | |
2760 | } | |
2761 | ||
49cfe4db | 2762 | static int atmel_aes_remove(struct platform_device *pdev) |
bd3c7b5c | 2763 | { |
fc783341 | 2764 | struct atmel_aes_dev *aes_dd; |
bd3c7b5c NR |
2765 | |
2766 | aes_dd = platform_get_drvdata(pdev); | |
2767 | if (!aes_dd) | |
2768 | return -ENODEV; | |
2769 | spin_lock(&atmel_aes.lock); | |
2770 | list_del(&aes_dd->list); | |
2771 | spin_unlock(&atmel_aes.lock); | |
2772 | ||
2773 | atmel_aes_unregister_algs(aes_dd); | |
2774 | ||
2775 | tasklet_kill(&aes_dd->done_task); | |
2776 | tasklet_kill(&aes_dd->queue_task); | |
2777 | ||
2778 | atmel_aes_dma_cleanup(aes_dd); | |
2a377828 | 2779 | atmel_aes_buff_cleanup(aes_dd); |
bd3c7b5c | 2780 | |
49a20454 CP |
2781 | clk_unprepare(aes_dd->iclk); |
2782 | ||
bd3c7b5c NR |
2783 | return 0; |
2784 | } | |
2785 | ||
2786 | static struct platform_driver atmel_aes_driver = { | |
2787 | .probe = atmel_aes_probe, | |
49cfe4db | 2788 | .remove = atmel_aes_remove, |
bd3c7b5c NR |
2789 | .driver = { |
2790 | .name = "atmel_aes", | |
be943c7d | 2791 | .of_match_table = of_match_ptr(atmel_aes_dt_ids), |
bd3c7b5c NR |
2792 | }, |
2793 | }; | |
2794 | ||
2795 | module_platform_driver(atmel_aes_driver); | |
2796 | ||
2797 | MODULE_DESCRIPTION("Atmel AES hw acceleration support."); | |
2798 | MODULE_LICENSE("GPL v2"); | |
2799 | MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); |