Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
b511431d JE |
2 | |
3 | menuconfig CRYPTO_HW | |
4 | bool "Hardware crypto devices" | |
5 | default y | |
a7f7f624 | 6 | help |
06bfb7eb JE |
7 | Say Y here to get to see options for hardware crypto devices and |
8 | processors. This option alone does not add any kernel code. | |
9 | ||
10 | If you say N, all options in this submenu will be skipped and disabled. | |
b511431d JE |
11 | |
12 | if CRYPTO_HW | |
1da177e4 | 13 | |
3914b931 CL |
14 | source "drivers/crypto/allwinner/Kconfig" |
15 | ||
1da177e4 | 16 | config CRYPTO_DEV_PADLOCK |
d158325e | 17 | tristate "Support for VIA PadLock ACE" |
2f817418 | 18 | depends on X86 && !UML |
1da177e4 LT |
19 | help |
20 | Some VIA processors come with an integrated crypto engine | |
21 | (so called VIA PadLock ACE, Advanced Cryptography Engine) | |
1191f0a4 ML |
22 | that provides instructions for very fast cryptographic |
23 | operations with supported algorithms. | |
1da177e4 LT |
24 | |
25 | The instructions are used only when the CPU supports them. | |
5644bda5 ML |
26 | Otherwise software encryption is used. |
27 | ||
1da177e4 | 28 | config CRYPTO_DEV_PADLOCK_AES |
1191f0a4 | 29 | tristate "PadLock driver for AES algorithm" |
1da177e4 | 30 | depends on CRYPTO_DEV_PADLOCK |
b95bba5d | 31 | select CRYPTO_SKCIPHER |
8131878d | 32 | select CRYPTO_LIB_AES |
1da177e4 LT |
33 | help |
34 | Use VIA PadLock for AES algorithm. | |
35 | ||
1191f0a4 ML |
36 | Available in VIA C3 and newer CPUs. |
37 | ||
38 | If unsure say M. The compiled module will be | |
4737f097 | 39 | called padlock-aes. |
1191f0a4 | 40 | |
6c833275 ML |
41 | config CRYPTO_DEV_PADLOCK_SHA |
42 | tristate "PadLock driver for SHA1 and SHA256 algorithms" | |
43 | depends on CRYPTO_DEV_PADLOCK | |
bbbee467 | 44 | select CRYPTO_HASH |
6c833275 ML |
45 | select CRYPTO_SHA1 |
46 | select CRYPTO_SHA256 | |
6c833275 ML |
47 | help |
48 | Use VIA PadLock for SHA1/SHA256 algorithms. | |
49 | ||
50 | Available in VIA C7 and newer processors. | |
51 | ||
52 | If unsure say M. The compiled module will be | |
4737f097 | 53 | called padlock-sha. |
6c833275 | 54 | |
9fe757b0 JC |
55 | config CRYPTO_DEV_GEODE |
56 | tristate "Support for the Geode LX AES engine" | |
f6259dea | 57 | depends on X86_32 && PCI |
9fe757b0 | 58 | select CRYPTO_ALGAPI |
b95bba5d | 59 | select CRYPTO_SKCIPHER |
9fe757b0 JC |
60 | help |
61 | Say 'Y' here to use the AMD Geode LX processor on-board AES | |
3dde6ad8 | 62 | engine for the CryptoAPI AES algorithm. |
9fe757b0 JC |
63 | |
64 | To compile this driver as a module, choose M here: the module | |
65 | will be called geode-aes. | |
66 | ||
61d48c2c | 67 | config ZCRYPT |
a3358e3d | 68 | tristate "Support for s390 cryptographic adapters" |
61d48c2c | 69 | depends on S390 |
2f7c8bd6 | 70 | select HW_RANDOM |
61d48c2c | 71 | help |
a3358e3d HF |
72 | Select this option if you want to enable support for |
73 | s390 cryptographic adapters like: | |
0ae88ccf HF |
74 | + Crypto Express 2 up to 7 Coprocessor (CEXxC) |
75 | + Crypto Express 2 up to 7 Accelerator (CEXxA) | |
76 | + Crypto Express 4 up to 7 EP11 Coprocessor (CEXxP) | |
77 | ||
78 | config ZCRYPT_DEBUG | |
79 | bool "Enable debug features for s390 cryptographic adapters" | |
80 | default n | |
81 | depends on DEBUG_KERNEL | |
82 | depends on ZCRYPT | |
83 | help | |
84 | Say 'Y' here to enable some additional debug features on the | |
85 | s390 cryptographic adapters driver. | |
86 | ||
87 | There will be some more sysfs attributes displayed for ap cards | |
88 | and queues and some flags on crypto requests are interpreted as | |
89 | debugging messages to force error injection. | |
90 | ||
91 | Do not enable on production level kernel build. | |
92 | ||
93 | If unsure, say N. | |
61d48c2c | 94 | |
00fab235 HF |
95 | config ZCRYPT_MULTIDEVNODES |
96 | bool "Support for multiple zcrypt device nodes" | |
97 | default y | |
98 | depends on S390 | |
99 | depends on ZCRYPT | |
100 | help | |
101 | With this option enabled the zcrypt device driver can | |
102 | provide multiple devices nodes in /dev. Each device | |
103 | node can get customized to limit access and narrow | |
104 | down the use of the available crypto hardware. | |
105 | ||
e80d4af0 HF |
106 | config PKEY |
107 | tristate "Kernel API for protected key handling" | |
108 | depends on S390 | |
109 | depends on ZCRYPT | |
110 | help | |
111 | With this option enabled the pkey kernel module provides an API | |
112 | for creation and handling of protected keys. Other parts of the | |
113 | kernel or userspace applications may use these functions. | |
114 | ||
115 | Select this option if you want to enable the kernel and userspace | |
116 | API for proteced key handling. | |
117 | ||
118 | Please note that creation of protected keys from secure keys | |
119 | requires to have at least one CEX card in coprocessor mode | |
120 | available at runtime. | |
61d48c2c | 121 | |
c4684f98 HF |
122 | config CRYPTO_PAES_S390 |
123 | tristate "PAES cipher algorithms" | |
124 | depends on S390 | |
125 | depends on ZCRYPT | |
126 | depends on PKEY | |
127 | select CRYPTO_ALGAPI | |
b95bba5d | 128 | select CRYPTO_SKCIPHER |
c4684f98 HF |
129 | help |
130 | This is the s390 hardware accelerated implementation of the | |
131 | AES cipher algorithms for use with protected key. | |
132 | ||
133 | Select this option if you want to use the paes cipher | |
134 | for example to use protected key encrypted devices. | |
135 | ||
3f5615e0 JG |
136 | config CRYPTO_SHA1_S390 |
137 | tristate "SHA1 digest algorithm" | |
138 | depends on S390 | |
563f346d | 139 | select CRYPTO_HASH |
3f5615e0 JG |
140 | help |
141 | This is the s390 hardware accelerated implementation of the | |
142 | SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). | |
143 | ||
d393d9b8 JG |
144 | It is available as of z990. |
145 | ||
3f5615e0 JG |
146 | config CRYPTO_SHA256_S390 |
147 | tristate "SHA256 digest algorithm" | |
148 | depends on S390 | |
563f346d | 149 | select CRYPTO_HASH |
3f5615e0 JG |
150 | help |
151 | This is the s390 hardware accelerated implementation of the | |
152 | SHA256 secure hash standard (DFIPS 180-2). | |
153 | ||
d393d9b8 | 154 | It is available as of z9. |
3f5615e0 | 155 | |
291dc7c0 | 156 | config CRYPTO_SHA512_S390 |
4e2c6d7f | 157 | tristate "SHA384 and SHA512 digest algorithm" |
291dc7c0 | 158 | depends on S390 |
563f346d | 159 | select CRYPTO_HASH |
291dc7c0 JG |
160 | help |
161 | This is the s390 hardware accelerated implementation of the | |
162 | SHA512 secure hash standard. | |
163 | ||
d393d9b8 | 164 | It is available as of z10. |
291dc7c0 | 165 | |
3c2eb6b7 JS |
166 | config CRYPTO_SHA3_256_S390 |
167 | tristate "SHA3_224 and SHA3_256 digest algorithm" | |
168 | depends on S390 | |
169 | select CRYPTO_HASH | |
170 | help | |
171 | This is the s390 hardware accelerated implementation of the | |
172 | SHA3_256 secure hash standard. | |
173 | ||
174 | It is available as of z14. | |
175 | ||
176 | config CRYPTO_SHA3_512_S390 | |
177 | tristate "SHA3_384 and SHA3_512 digest algorithm" | |
178 | depends on S390 | |
179 | select CRYPTO_HASH | |
180 | help | |
181 | This is the s390 hardware accelerated implementation of the | |
182 | SHA3_512 secure hash standard. | |
183 | ||
184 | It is available as of z14. | |
185 | ||
3f5615e0 JG |
186 | config CRYPTO_DES_S390 |
187 | tristate "DES and Triple DES cipher algorithms" | |
188 | depends on S390 | |
189 | select CRYPTO_ALGAPI | |
b95bba5d | 190 | select CRYPTO_SKCIPHER |
04007b0e | 191 | select CRYPTO_LIB_DES |
3f5615e0 | 192 | help |
0200f3ec | 193 | This is the s390 hardware accelerated implementation of the |
3f5615e0 JG |
194 | DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). |
195 | ||
0200f3ec GS |
196 | As of z990 the ECB and CBC mode are hardware accelerated. |
197 | As of z196 the CTR mode is hardware accelerated. | |
198 | ||
3f5615e0 JG |
199 | config CRYPTO_AES_S390 |
200 | tristate "AES cipher algorithms" | |
201 | depends on S390 | |
202 | select CRYPTO_ALGAPI | |
b95bba5d | 203 | select CRYPTO_SKCIPHER |
3f5615e0 JG |
204 | help |
205 | This is the s390 hardware accelerated implementation of the | |
99d97222 GS |
206 | AES cipher algorithms (FIPS-197). |
207 | ||
208 | As of z9 the ECB and CBC modes are hardware accelerated | |
209 | for 128 bit keys. | |
210 | As of z10 the ECB and CBC modes are hardware accelerated | |
211 | for all AES key sizes. | |
0200f3ec GS |
212 | As of z196 the CTR mode is hardware accelerated for all AES |
213 | key sizes and XTS mode is hardware accelerated for 256 and | |
99d97222 | 214 | 512 bit keys. |
3f5615e0 JG |
215 | |
216 | config S390_PRNG | |
217 | tristate "Pseudo random number generator device driver" | |
218 | depends on S390 | |
219 | default "m" | |
220 | help | |
221 | Select this option if you want to use the s390 pseudo random number | |
222 | generator. The PRNG is part of the cryptographic processor functions | |
223 | and uses triple-DES to generate secure random numbers like the | |
d393d9b8 JG |
224 | ANSI X9.17 standard. User-space programs access the |
225 | pseudo-random-number device through the char device /dev/prandom. | |
226 | ||
227 | It is available as of z9. | |
3f5615e0 | 228 | |
df1309ce | 229 | config CRYPTO_GHASH_S390 |
8dfa20fc | 230 | tristate "GHASH hash function" |
df1309ce GS |
231 | depends on S390 |
232 | select CRYPTO_HASH | |
233 | help | |
8dfa20fc EB |
234 | This is the s390 hardware accelerated implementation of GHASH, |
235 | the hash function used in GCM (Galois/Counter mode). | |
df1309ce GS |
236 | |
237 | It is available as of z196. | |
238 | ||
f848dbd3 HB |
239 | config CRYPTO_CRC32_S390 |
240 | tristate "CRC-32 algorithms" | |
241 | depends on S390 | |
242 | select CRYPTO_HASH | |
243 | select CRC32 | |
244 | help | |
245 | Select this option if you want to use hardware accelerated | |
246 | implementations of CRC algorithms. With this option, you | |
247 | can optimize the computation of CRC-32 (IEEE 802.3 Ethernet) | |
248 | and CRC-32C (Castagnoli). | |
249 | ||
250 | It is available with IBM z13 or later. | |
251 | ||
0a625fd2 | 252 | config CRYPTO_DEV_NIAGARA2 |
2452cfdf KK |
253 | tristate "Niagara2 Stream Processing Unit driver" |
254 | select CRYPTO_LIB_DES | |
255 | select CRYPTO_SKCIPHER | |
256 | select CRYPTO_HASH | |
257 | select CRYPTO_MD5 | |
258 | select CRYPTO_SHA1 | |
259 | select CRYPTO_SHA256 | |
260 | depends on SPARC64 | |
261 | help | |
0a625fd2 DM |
262 | Each core of a Niagara2 processor contains a Stream |
263 | Processing Unit, which itself contains several cryptographic | |
264 | sub-units. One set provides the Modular Arithmetic Unit, | |
265 | used for SSL offload. The other set provides the Cipher | |
266 | Group, which can perform encryption, decryption, hashing, | |
267 | checksumming, and raw copies. | |
268 | ||
f7d0561e EP |
269 | config CRYPTO_DEV_HIFN_795X |
270 | tristate "Driver HIFN 795x crypto accelerator chips" | |
04007b0e | 271 | select CRYPTO_LIB_DES |
b95bba5d | 272 | select CRYPTO_SKCIPHER |
946fef4e | 273 | select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG |
2707b937 | 274 | depends on PCI |
75b76625 | 275 | depends on !ARCH_DMA_ADDR_T_64BIT |
f7d0561e EP |
276 | help |
277 | This option allows you to have support for HIFN 795x crypto adapters. | |
278 | ||
946fef4e HX |
279 | config CRYPTO_DEV_HIFN_795X_RNG |
280 | bool "HIFN 795x random number generator" | |
281 | depends on CRYPTO_DEV_HIFN_795X | |
282 | help | |
283 | Select this option if you want to enable the random number generator | |
284 | on the HIFN 795x crypto adapters. | |
f7d0561e | 285 | |
8636a1f9 | 286 | source "drivers/crypto/caam/Kconfig" |
8e8ec596 | 287 | |
9c4a7965 KP |
288 | config CRYPTO_DEV_TALITOS |
289 | tristate "Talitos Freescale Security Engine (SEC)" | |
596103cf | 290 | select CRYPTO_AEAD |
9c4a7965 | 291 | select CRYPTO_AUTHENC |
b95bba5d | 292 | select CRYPTO_SKCIPHER |
596103cf | 293 | select CRYPTO_HASH |
dbc2e87b | 294 | select CRYPTO_LIB_DES |
9c4a7965 KP |
295 | select HW_RANDOM |
296 | depends on FSL_SOC | |
297 | help | |
298 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
299 | to offload cryptographic algorithm computation. | |
300 | ||
301 | The Freescale SEC is present on PowerQUICC 'E' processors, such | |
302 | as the MPC8349E and MPC8548E. | |
303 | ||
304 | To compile this driver as a module, choose M here: the module | |
305 | will be called talitos. | |
306 | ||
5b841a65 LC |
307 | config CRYPTO_DEV_TALITOS1 |
308 | bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" | |
309 | depends on CRYPTO_DEV_TALITOS | |
310 | depends on PPC_8xx || PPC_82xx | |
311 | default y | |
312 | help | |
313 | Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 | |
314 | found on MPC82xx or the Freescale Security Engine (SEC Lite) | |
315 | version 1.2 found on MPC8xx | |
316 | ||
317 | config CRYPTO_DEV_TALITOS2 | |
318 | bool "SEC2+ (SEC version 2.0 or upper)" | |
319 | depends on CRYPTO_DEV_TALITOS | |
320 | default y if !PPC_8xx | |
321 | help | |
322 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
323 | version 2 and following as found on MPC83xx, MPC85xx, etc ... | |
324 | ||
81bef015 CH |
325 | config CRYPTO_DEV_IXP4XX |
326 | tristate "Driver for IXP4xx crypto hardware acceleration" | |
9665c52b | 327 | depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE |
04007b0e | 328 | select CRYPTO_LIB_DES |
596103cf | 329 | select CRYPTO_AEAD |
090657e4 | 330 | select CRYPTO_AUTHENC |
b95bba5d | 331 | select CRYPTO_SKCIPHER |
81bef015 CH |
332 | help |
333 | Driver for the IXP4xx NPE crypto engine. | |
334 | ||
049359d6 JH |
335 | config CRYPTO_DEV_PPC4XX |
336 | tristate "Driver AMCC PPC4xx crypto accelerator" | |
337 | depends on PPC && 4xx | |
338 | select CRYPTO_HASH | |
a0aae821 | 339 | select CRYPTO_AEAD |
298b4c60 | 340 | select CRYPTO_AES |
da3e7a97 | 341 | select CRYPTO_LIB_AES |
a0aae821 | 342 | select CRYPTO_CCM |
98e87e3d | 343 | select CRYPTO_CTR |
a0aae821 | 344 | select CRYPTO_GCM |
b95bba5d | 345 | select CRYPTO_SKCIPHER |
049359d6 JH |
346 | help |
347 | This option allows you to have support for AMCC crypto acceleration. | |
348 | ||
5343e674 CL |
349 | config HW_RANDOM_PPC4XX |
350 | bool "PowerPC 4xx generic true random number generator support" | |
63b8ee4f | 351 | depends on CRYPTO_DEV_PPC4XX && HW_RANDOM=y |
5343e674 | 352 | default y |
a7f7f624 | 353 | help |
5343e674 CL |
354 | This option provides the kernel-side support for the TRNG hardware |
355 | found in the security function of some PowerPC 4xx SoCs. | |
356 | ||
74ed87e7 TK |
357 | config CRYPTO_DEV_OMAP |
358 | tristate "Support for OMAP crypto HW accelerators" | |
359 | depends on ARCH_OMAP2PLUS | |
360 | help | |
361 | OMAP processors have various crypto HW accelerators. Select this if | |
2452cfdf | 362 | you want to use the OMAP modules for any of the crypto algorithms. |
74ed87e7 TK |
363 | |
364 | if CRYPTO_DEV_OMAP | |
365 | ||
8628e7c8 | 366 | config CRYPTO_DEV_OMAP_SHAM |
eaef7e3f LV |
367 | tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator" |
368 | depends on ARCH_OMAP2PLUS | |
38281194 | 369 | select CRYPTO_ENGINE |
8628e7c8 DK |
370 | select CRYPTO_SHA1 |
371 | select CRYPTO_MD5 | |
eaef7e3f LV |
372 | select CRYPTO_SHA256 |
373 | select CRYPTO_SHA512 | |
374 | select CRYPTO_HMAC | |
8628e7c8 | 375 | help |
eaef7e3f LV |
376 | OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you |
377 | want to use the OMAP module for MD5/SHA1/SHA2 algorithms. | |
8628e7c8 | 378 | |
537559a5 DK |
379 | config CRYPTO_DEV_OMAP_AES |
380 | tristate "Support for OMAP AES hw engine" | |
1bbf6437 | 381 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS |
537559a5 | 382 | select CRYPTO_AES |
b95bba5d | 383 | select CRYPTO_SKCIPHER |
0529900a | 384 | select CRYPTO_ENGINE |
9fcb191a LV |
385 | select CRYPTO_CBC |
386 | select CRYPTO_ECB | |
387 | select CRYPTO_CTR | |
ad18cc9d | 388 | select CRYPTO_AEAD |
537559a5 DK |
389 | help |
390 | OMAP processors have AES module accelerator. Select this if you | |
391 | want to use the OMAP module for AES algorithms. | |
392 | ||
701d0f19 | 393 | config CRYPTO_DEV_OMAP_DES |
97ee7ed3 | 394 | tristate "Support for OMAP DES/3DES hw engine" |
701d0f19 | 395 | depends on ARCH_OMAP2PLUS |
04007b0e | 396 | select CRYPTO_LIB_DES |
b95bba5d | 397 | select CRYPTO_SKCIPHER |
f1b77aac | 398 | select CRYPTO_ENGINE |
701d0f19 JF |
399 | help |
400 | OMAP processors have DES/3DES module accelerator. Select this if you | |
401 | want to use the OMAP module for DES and 3DES algorithms. Currently | |
97ee7ed3 PM |
402 | the ECB and CBC modes of operation are supported by the driver. Also |
403 | accesses made on unaligned boundaries are supported. | |
701d0f19 | 404 | |
74ed87e7 TK |
405 | endif # CRYPTO_DEV_OMAP |
406 | ||
5de88752 JM |
407 | config CRYPTO_DEV_SAHARA |
408 | tristate "Support for SAHARA crypto accelerator" | |
74d24d83 | 409 | depends on ARCH_MXC && OF |
b95bba5d | 410 | select CRYPTO_SKCIPHER |
5de88752 JM |
411 | select CRYPTO_AES |
412 | select CRYPTO_ECB | |
413 | help | |
414 | This option enables support for the SAHARA HW crypto accelerator | |
415 | found in some Freescale i.MX chips. | |
416 | ||
c46ea13f | 417 | config CRYPTO_DEV_EXYNOS_RNG |
b279997f | 418 | tristate "Exynos HW pseudo random number generator support" |
c46ea13f KK |
419 | depends on ARCH_EXYNOS || COMPILE_TEST |
420 | depends on HAS_IOMEM | |
421 | select CRYPTO_RNG | |
a7f7f624 | 422 | help |
c46ea13f KK |
423 | This driver provides kernel-side support through the |
424 | cryptographic API for the pseudo random number generator hardware | |
425 | found on Exynos SoCs. | |
426 | ||
427 | To compile this driver as a module, choose M here: the | |
428 | module will be called exynos-rng. | |
429 | ||
430 | If unsure, say Y. | |
431 | ||
a49e490c | 432 | config CRYPTO_DEV_S5P |
e922e96f | 433 | tristate "Support for Samsung S5PV210/Exynos crypto accelerator" |
dc1d9dee | 434 | depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST |
ee1b23d1 | 435 | depends on HAS_IOMEM |
a49e490c | 436 | select CRYPTO_AES |
b95bba5d | 437 | select CRYPTO_SKCIPHER |
a49e490c VZ |
438 | help |
439 | This option allows you to have support for S5P crypto acceleration. | |
e922e96f | 440 | Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES |
a49e490c VZ |
441 | algorithms execution. |
442 | ||
c2afad6c KK |
443 | config CRYPTO_DEV_EXYNOS_HASH |
444 | bool "Support for Samsung Exynos HASH accelerator" | |
445 | depends on CRYPTO_DEV_S5P | |
446 | depends on !CRYPTO_DEV_EXYNOS_RNG && CRYPTO_DEV_EXYNOS_RNG!=m | |
447 | select CRYPTO_SHA1 | |
448 | select CRYPTO_MD5 | |
449 | select CRYPTO_SHA256 | |
450 | help | |
451 | Select this to offload Exynos from HASH MD5/SHA1/SHA256. | |
452 | This will select software SHA1, MD5 and SHA256 as they are | |
453 | needed for small and zero-size messages. | |
454 | HASH algorithms will be disabled if EXYNOS_RNG | |
455 | is enabled due to hw conflict. | |
456 | ||
aef7b31c | 457 | config CRYPTO_DEV_NX |
7011a122 DS |
458 | bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" |
459 | depends on PPC64 | |
aef7b31c | 460 | help |
7011a122 DS |
461 | This enables support for the NX hardware cryptographic accelerator |
462 | coprocessor that is in IBM PowerPC P7+ or later processors. This | |
463 | does not actually enable any drivers, it only allows you to select | |
464 | which acceleration type (encryption and/or compression) to enable. | |
322cacce SJ |
465 | |
466 | if CRYPTO_DEV_NX | |
467 | source "drivers/crypto/nx/Kconfig" | |
468 | endif | |
aef7b31c | 469 | |
2789c08f AW |
470 | config CRYPTO_DEV_UX500 |
471 | tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration" | |
472 | depends on ARCH_U8500 | |
2789c08f AW |
473 | help |
474 | Driver for ST-Ericsson UX500 crypto engine. | |
475 | ||
476 | if CRYPTO_DEV_UX500 | |
477 | source "drivers/crypto/ux500/Kconfig" | |
478 | endif # if CRYPTO_DEV_UX500 | |
479 | ||
89a82ef8 | 480 | config CRYPTO_DEV_ATMEL_AUTHENC |
aee1f9f3 | 481 | bool "Support for Atmel IPSEC/SSL hw accelerator" |
ceb4afb3 | 482 | depends on ARCH_AT91 || COMPILE_TEST |
aee1f9f3 | 483 | depends on CRYPTO_DEV_ATMEL_AES |
89a82ef8 CP |
484 | help |
485 | Some Atmel processors can combine the AES and SHA hw accelerators | |
486 | to enhance support of IPSEC/SSL. | |
487 | Select this if you want to use the Atmel modules for | |
488 | authenc(hmac(shaX),Y(cbc)) algorithms. | |
489 | ||
bd3c7b5c NR |
490 | config CRYPTO_DEV_ATMEL_AES |
491 | tristate "Support for Atmel AES hw accelerator" | |
ceb4afb3 | 492 | depends on ARCH_AT91 || COMPILE_TEST |
bd3c7b5c | 493 | select CRYPTO_AES |
d4419548 | 494 | select CRYPTO_AEAD |
b95bba5d | 495 | select CRYPTO_SKCIPHER |
aee1f9f3 Y |
496 | select CRYPTO_AUTHENC if CRYPTO_DEV_ATMEL_AUTHENC |
497 | select CRYPTO_DEV_ATMEL_SHA if CRYPTO_DEV_ATMEL_AUTHENC | |
bd3c7b5c NR |
498 | help |
499 | Some Atmel processors have AES hw accelerator. | |
500 | Select this if you want to use the Atmel module for | |
501 | AES algorithms. | |
502 | ||
503 | To compile this driver as a module, choose M here: the module | |
504 | will be called atmel-aes. | |
505 | ||
13802005 NR |
506 | config CRYPTO_DEV_ATMEL_TDES |
507 | tristate "Support for Atmel DES/TDES hw accelerator" | |
ceb4afb3 | 508 | depends on ARCH_AT91 || COMPILE_TEST |
04007b0e | 509 | select CRYPTO_LIB_DES |
b95bba5d | 510 | select CRYPTO_SKCIPHER |
13802005 NR |
511 | help |
512 | Some Atmel processors have DES/TDES hw accelerator. | |
513 | Select this if you want to use the Atmel module for | |
514 | DES/TDES algorithms. | |
515 | ||
516 | To compile this driver as a module, choose M here: the module | |
517 | will be called atmel-tdes. | |
518 | ||
ebc82efa | 519 | config CRYPTO_DEV_ATMEL_SHA |
d4905b38 | 520 | tristate "Support for Atmel SHA hw accelerator" |
ceb4afb3 | 521 | depends on ARCH_AT91 || COMPILE_TEST |
596103cf | 522 | select CRYPTO_HASH |
ebc82efa | 523 | help |
d4905b38 NR |
524 | Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512 |
525 | hw accelerator. | |
ebc82efa | 526 | Select this if you want to use the Atmel module for |
d4905b38 | 527 | SHA1/SHA224/SHA256/SHA384/SHA512 algorithms. |
ebc82efa NR |
528 | |
529 | To compile this driver as a module, choose M here: the module | |
530 | will be called atmel-sha. | |
531 | ||
c34a3201 AB |
532 | config CRYPTO_DEV_ATMEL_I2C |
533 | tristate | |
d33a23b0 | 534 | select BITREVERSE |
c34a3201 | 535 | |
11105693 TDA |
536 | config CRYPTO_DEV_ATMEL_ECC |
537 | tristate "Support for Microchip / Atmel ECC hw accelerator" | |
11105693 | 538 | depends on I2C |
c34a3201 | 539 | select CRYPTO_DEV_ATMEL_I2C |
11105693 TDA |
540 | select CRYPTO_ECDH |
541 | select CRC16 | |
542 | help | |
543 | Microhip / Atmel ECC hw accelerator. | |
544 | Select this if you want to use the Microchip / Atmel module for | |
545 | ECDH algorithm. | |
546 | ||
547 | To compile this driver as a module, choose M here: the module | |
548 | will be called atmel-ecc. | |
549 | ||
da001fb6 AB |
550 | config CRYPTO_DEV_ATMEL_SHA204A |
551 | tristate "Support for Microchip / Atmel SHA accelerator and RNG" | |
552 | depends on I2C | |
553 | select CRYPTO_DEV_ATMEL_I2C | |
554 | select HW_RANDOM | |
4bb02dbd | 555 | select CRC16 |
da001fb6 AB |
556 | help |
557 | Microhip / Atmel SHA accelerator and RNG. | |
558 | Select this if you want to use the Microchip / Atmel SHA204A | |
559 | module as a random number generator. (Other functions of the | |
560 | chip are currently not exposed by this driver) | |
561 | ||
562 | To compile this driver as a module, choose M here: the module | |
563 | will be called atmel-sha204a. | |
564 | ||
f1147660 | 565 | config CRYPTO_DEV_CCP |
720419f0 | 566 | bool "Support for AMD Secure Processor" |
6c506343 | 567 | depends on ((X86 && PCI) || (ARM64 && (OF_ADDRESS || ACPI))) && HAS_IOMEM |
f1147660 | 568 | help |
720419f0 BS |
569 | The AMD Secure Processor provides support for the Cryptographic Coprocessor |
570 | (CCP) and the Platform Security Processor (PSP) devices. | |
f1147660 TL |
571 | |
572 | if CRYPTO_DEV_CCP | |
573 | source "drivers/crypto/ccp/Kconfig" | |
574 | endif | |
575 | ||
15b59e7c MV |
576 | config CRYPTO_DEV_MXS_DCP |
577 | tristate "Support for Freescale MXS DCP" | |
a2712e6c | 578 | depends on (ARCH_MXS || ARCH_MXC) |
dc97fa02 | 579 | select STMP_DEVICE |
15b59e7c MV |
580 | select CRYPTO_CBC |
581 | select CRYPTO_ECB | |
582 | select CRYPTO_AES | |
b95bba5d | 583 | select CRYPTO_SKCIPHER |
596103cf | 584 | select CRYPTO_HASH |
15b59e7c MV |
585 | help |
586 | The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB | |
587 | co-processor on the die. | |
588 | ||
589 | To compile this driver as a module, choose M here: the module | |
590 | will be called mxs-dcp. | |
591 | ||
cea4001a | 592 | source "drivers/crypto/qat/Kconfig" |
62ad8b5c | 593 | source "drivers/crypto/cavium/cpt/Kconfig" |
14fa93cd | 594 | source "drivers/crypto/cavium/nitrox/Kconfig" |
655ff1a1 | 595 | source "drivers/crypto/marvell/Kconfig" |
c672752d | 596 | |
640035a2 MC |
597 | config CRYPTO_DEV_CAVIUM_ZIP |
598 | tristate "Cavium ZIP driver" | |
599 | depends on PCI && 64BIT && (ARM64 || COMPILE_TEST) | |
a7f7f624 | 600 | help |
640035a2 MC |
601 | Select this option if you want to enable compression/decompression |
602 | acceleration on Cavium's ARM based SoCs | |
603 | ||
c672752d SV |
604 | config CRYPTO_DEV_QCE |
605 | tristate "Qualcomm crypto engine accelerator" | |
ee1b23d1 GU |
606 | depends on ARCH_QCOM || COMPILE_TEST |
607 | depends on HAS_IOMEM | |
59e056cd EQ |
608 | help |
609 | This driver supports Qualcomm crypto engine accelerator | |
610 | hardware. To compile this driver as a module, choose M here. The | |
611 | module will be called qcrypto. | |
612 | ||
613 | config CRYPTO_DEV_QCE_SKCIPHER | |
614 | bool | |
615 | depends on CRYPTO_DEV_QCE | |
c672752d | 616 | select CRYPTO_AES |
04007b0e | 617 | select CRYPTO_LIB_DES |
c672752d SV |
618 | select CRYPTO_ECB |
619 | select CRYPTO_CBC | |
620 | select CRYPTO_XTS | |
621 | select CRYPTO_CTR | |
b95bba5d | 622 | select CRYPTO_SKCIPHER |
59e056cd EQ |
623 | |
624 | config CRYPTO_DEV_QCE_SHA | |
625 | bool | |
626 | depends on CRYPTO_DEV_QCE | |
8ac1b9cc SM |
627 | select CRYPTO_SHA1 |
628 | select CRYPTO_SHA256 | |
59e056cd EQ |
629 | |
630 | choice | |
631 | prompt "Algorithms enabled for QCE acceleration" | |
632 | default CRYPTO_DEV_QCE_ENABLE_ALL | |
633 | depends on CRYPTO_DEV_QCE | |
634 | help | |
2e0e386a | 635 | This option allows to choose whether to build support for all algorithms |
59e056cd EQ |
636 | (default), hashes-only, or skciphers-only. |
637 | ||
638 | The QCE engine does not appear to scale as well as the CPU to handle | |
639 | multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the | |
640 | QCE handles only 2 requests in parallel. | |
641 | ||
642 | Ipsec throughput seems to improve when disabling either family of | |
643 | algorithms, sharing the load with the CPU. Enabling skciphers-only | |
644 | appears to work best. | |
645 | ||
646 | config CRYPTO_DEV_QCE_ENABLE_ALL | |
647 | bool "All supported algorithms" | |
648 | select CRYPTO_DEV_QCE_SKCIPHER | |
649 | select CRYPTO_DEV_QCE_SHA | |
650 | help | |
651 | Enable all supported algorithms: | |
652 | - AES (CBC, CTR, ECB, XTS) | |
653 | - 3DES (CBC, ECB) | |
654 | - DES (CBC, ECB) | |
655 | - SHA1, HMAC-SHA1 | |
656 | - SHA256, HMAC-SHA256 | |
657 | ||
658 | config CRYPTO_DEV_QCE_ENABLE_SKCIPHER | |
659 | bool "Symmetric-key ciphers only" | |
660 | select CRYPTO_DEV_QCE_SKCIPHER | |
661 | help | |
662 | Enable symmetric-key ciphers only: | |
663 | - AES (CBC, CTR, ECB, XTS) | |
664 | - 3DES (ECB, CBC) | |
665 | - DES (ECB, CBC) | |
666 | ||
667 | config CRYPTO_DEV_QCE_ENABLE_SHA | |
668 | bool "Hash/HMAC only" | |
669 | select CRYPTO_DEV_QCE_SHA | |
670 | help | |
671 | Enable hashes/HMAC algorithms only: | |
672 | - SHA1, HMAC-SHA1 | |
673 | - SHA256, HMAC-SHA256 | |
674 | ||
675 | endchoice | |
c672752d | 676 | |
ce163ba0 EQ |
677 | config CRYPTO_DEV_QCE_SW_MAX_LEN |
678 | int "Default maximum request size to use software for AES" | |
679 | depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER | |
680 | default 512 | |
681 | help | |
682 | This sets the default maximum request size to perform AES requests | |
683 | using software instead of the crypto engine. It can be changed by | |
684 | setting the aes_sw_max_len parameter. | |
685 | ||
686 | Small blocks are processed faster in software than hardware. | |
687 | Considering the 256-bit ciphers, software is 2-3 times faster than | |
688 | qce at 256-bytes, 30% faster at 512, and about even at 768-bytes. | |
689 | With 128-bit keys, the break-even point would be around 1024-bytes. | |
690 | ||
691 | The default is set a little lower, to 512 bytes, to balance the | |
692 | cost in CPU usage. The minimum recommended setting is 16-bytes | |
693 | (1 AES block), since AES-GCM will fail if you set it lower. | |
694 | Setting this to zero will send all requests to the hardware. | |
695 | ||
696 | Note that 192-bit keys are not supported by the hardware and are | |
697 | always processed by the software fallback, and all DES requests | |
698 | are done by the hardware. | |
699 | ||
ceec5f5b VK |
700 | config CRYPTO_DEV_QCOM_RNG |
701 | tristate "Qualcomm Random Number Generator Driver" | |
702 | depends on ARCH_QCOM || COMPILE_TEST | |
703 | select CRYPTO_RNG | |
704 | help | |
705 | This driver provides support for the Random Number | |
706 | Generator hardware found on Qualcomm SoCs. | |
707 | ||
708 | To compile this driver as a module, choose M here. The | |
2452cfdf | 709 | module will be called qcom-rng. If unsure, say N. |
ceec5f5b | 710 | |
d2e3ae6f LB |
711 | config CRYPTO_DEV_VMX |
712 | bool "Support for VMX cryptographic acceleration instructions" | |
f1ab4287 | 713 | depends on PPC64 && VSX |
d2e3ae6f LB |
714 | help |
715 | Support for VMX cryptographic acceleration instructions. | |
716 | ||
717 | source "drivers/crypto/vmx/Kconfig" | |
718 | ||
d358f1ab | 719 | config CRYPTO_DEV_IMGTEC_HASH |
d358f1ab | 720 | tristate "Imagination Technologies hardware hash accelerator" |
8c98ebd7 | 721 | depends on MIPS || COMPILE_TEST |
d358f1ab JH |
722 | select CRYPTO_MD5 |
723 | select CRYPTO_SHA1 | |
d358f1ab JH |
724 | select CRYPTO_SHA256 |
725 | select CRYPTO_HASH | |
726 | help | |
727 | This driver interfaces with the Imagination Technologies | |
728 | hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 | |
729 | hashing algorithms. | |
730 | ||
433cd2c6 ZW |
731 | config CRYPTO_DEV_ROCKCHIP |
732 | tristate "Rockchip's Cryptographic Engine driver" | |
733 | depends on OF && ARCH_ROCKCHIP | |
734 | select CRYPTO_AES | |
04007b0e | 735 | select CRYPTO_LIB_DES |
bfd927ff ZW |
736 | select CRYPTO_MD5 |
737 | select CRYPTO_SHA1 | |
738 | select CRYPTO_SHA256 | |
739 | select CRYPTO_HASH | |
b95bba5d | 740 | select CRYPTO_SKCIPHER |
433cd2c6 ZW |
741 | |
742 | help | |
743 | This driver interfaces with the hardware crypto accelerator. | |
744 | Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. | |
745 | ||
4d96f7d4 KA |
746 | config CRYPTO_DEV_ZYNQMP_AES |
747 | tristate "Support for Xilinx ZynqMP AES hw accelerator" | |
748 | depends on ZYNQMP_FIRMWARE || COMPILE_TEST | |
749 | select CRYPTO_AES | |
750 | select CRYPTO_ENGINE | |
751 | select CRYPTO_AEAD | |
752 | help | |
753 | Xilinx ZynqMP has AES-GCM engine used for symmetric key | |
754 | encryption and decryption. This driver interfaces with AES hw | |
755 | accelerator. Select this if you want to use the ZynqMP module | |
756 | for AES algorithms. | |
757 | ||
02038fd6 HS |
758 | source "drivers/crypto/chelsio/Kconfig" |
759 | ||
dbaf0624 G |
760 | source "drivers/crypto/virtio/Kconfig" |
761 | ||
9d12ba86 RR |
762 | config CRYPTO_DEV_BCM_SPU |
763 | tristate "Broadcom symmetric crypto/hash acceleration support" | |
764 | depends on ARCH_BCM_IPROC | |
efc856ed | 765 | depends on MAILBOX |
9d12ba86 | 766 | default m |
ab57b335 | 767 | select CRYPTO_AUTHENC |
04007b0e | 768 | select CRYPTO_LIB_DES |
9d12ba86 RR |
769 | select CRYPTO_MD5 |
770 | select CRYPTO_SHA1 | |
771 | select CRYPTO_SHA256 | |
772 | select CRYPTO_SHA512 | |
773 | help | |
774 | This driver provides support for Broadcom crypto acceleration using the | |
a9c01cd6 | 775 | Secure Processing Unit (SPU). The SPU driver registers skcipher, |
9d12ba86 RR |
776 | ahash, and aead algorithms with the kernel cryptographic API. |
777 | ||
b51dbe90 FD |
778 | source "drivers/crypto/stm32/Kconfig" |
779 | ||
1b44c5a6 AT |
780 | config CRYPTO_DEV_SAFEXCEL |
781 | tristate "Inside Secure's SafeXcel cryptographic engine driver" | |
6dc0e310 | 782 | depends on (OF || PCI || COMPILE_TEST) && HAS_IOMEM |
363a90c2 | 783 | select CRYPTO_LIB_AES |
f6beaea3 | 784 | select CRYPTO_AUTHENC |
b95bba5d | 785 | select CRYPTO_SKCIPHER |
04007b0e | 786 | select CRYPTO_LIB_DES |
1b44c5a6 AT |
787 | select CRYPTO_HASH |
788 | select CRYPTO_HMAC | |
293f89cf | 789 | select CRYPTO_MD5 |
1b44c5a6 AT |
790 | select CRYPTO_SHA1 |
791 | select CRYPTO_SHA256 | |
792 | select CRYPTO_SHA512 | |
fc0f82b1 | 793 | select CRYPTO_CHACHA20POLY1305 |
1d448f27 | 794 | select CRYPTO_SHA3 |
1b44c5a6 | 795 | help |
0f6e5c82 PL |
796 | This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic |
797 | engines designed by Inside Secure. It currently accelerates DES, 3DES and | |
798 | AES block ciphers in ECB and CBC mode, as well as SHA1, SHA224, SHA256, | |
799 | SHA384 and SHA512 hash algorithms for both basic hash and HMAC. | |
800 | Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations. | |
1b44c5a6 | 801 | |
a21eb94f LP |
802 | config CRYPTO_DEV_ARTPEC6 |
803 | tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration." | |
804 | depends on ARM && (ARCH_ARTPEC || COMPILE_TEST) | |
a21eb94f LP |
805 | depends on OF |
806 | select CRYPTO_AEAD | |
807 | select CRYPTO_AES | |
808 | select CRYPTO_ALGAPI | |
b95bba5d | 809 | select CRYPTO_SKCIPHER |
a21eb94f LP |
810 | select CRYPTO_CTR |
811 | select CRYPTO_HASH | |
812 | select CRYPTO_SHA1 | |
813 | select CRYPTO_SHA256 | |
a21eb94f LP |
814 | select CRYPTO_SHA512 |
815 | help | |
816 | Enables the driver for the on-chip crypto accelerator | |
817 | of Axis ARTPEC SoCs. | |
818 | ||
819 | To compile this driver as a module, choose M here. | |
820 | ||
4c3f9727 GBY |
821 | config CRYPTO_DEV_CCREE |
822 | tristate "Support for ARM TrustZone CryptoCell family of security processors" | |
823 | depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA | |
824 | default n | |
825 | select CRYPTO_HASH | |
b95bba5d | 826 | select CRYPTO_SKCIPHER |
04007b0e | 827 | select CRYPTO_LIB_DES |
4c3f9727 GBY |
828 | select CRYPTO_AEAD |
829 | select CRYPTO_AUTHENC | |
830 | select CRYPTO_SHA1 | |
831 | select CRYPTO_MD5 | |
832 | select CRYPTO_SHA256 | |
833 | select CRYPTO_SHA512 | |
834 | select CRYPTO_HMAC | |
835 | select CRYPTO_AES | |
836 | select CRYPTO_CBC | |
837 | select CRYPTO_ECB | |
838 | select CRYPTO_CTR | |
839 | select CRYPTO_XTS | |
9b8d51f8 | 840 | select CRYPTO_SM4 |
927574e0 | 841 | select CRYPTO_SM3 |
4c3f9727 | 842 | help |
27b3b22d GBY |
843 | Say 'Y' to enable a driver for the REE interface of the Arm |
844 | TrustZone CryptoCell family of processors. Currently the | |
1c876a90 | 845 | CryptoCell 713, 703, 712, 710 and 630 are supported. |
4c3f9727 GBY |
846 | Choose this if you wish to use hardware acceleration of |
847 | cryptographic operations on the system REE. | |
848 | If unsure say Y. | |
849 | ||
915e4e84 JC |
850 | source "drivers/crypto/hisilicon/Kconfig" |
851 | ||
48fe583f CL |
852 | source "drivers/crypto/amlogic/Kconfig" |
853 | ||
7694b6ca K |
854 | config CRYPTO_DEV_SA2UL |
855 | tristate "Support for TI security accelerator" | |
856 | depends on ARCH_K3 || COMPILE_TEST | |
857 | select ARM64_CRYPTO | |
858 | select CRYPTO_AES | |
859 | select CRYPTO_AES_ARM64 | |
860 | select CRYPTO_ALGAPI | |
61f033ba | 861 | select CRYPTO_AUTHENC |
bfe8fe93 RD |
862 | select CRYPTO_SHA1 |
863 | select CRYPTO_SHA256 | |
864 | select CRYPTO_SHA512 | |
7694b6ca K |
865 | select HW_RANDOM |
866 | select SG_SPLIT | |
867 | help | |
868 | K3 devices include a security accelerator engine that may be | |
869 | used for crypto offload. Select this if you want to use hardware | |
870 | acceleration for cryptographic algorithms on these devices. | |
871 | ||
88574332 MH |
872 | source "drivers/crypto/keembay/Kconfig" |
873 | ||
b511431d | 874 | endif # CRYPTO_HW |