[linux-2.6-block.git] / drivers / cpufreq / tegra186-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
 */

#include <linux/cpufreq.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>

#define EDVD_CORE_VOLT_FREQ(core)		(0x20 + (core) * 0x4)
#define EDVD_CORE_VOLT_FREQ_F_SHIFT		0
#define EDVD_CORE_VOLT_FREQ_V_SHIFT		16

struct tegra186_cpufreq_cluster_info {
	unsigned long offset;
	int cpus[4];
	unsigned int bpmp_cluster_id;
};

#define NO_CPU -1
static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
	/* Denver cluster */
	{
		.offset = SZ_64K * 7,
		.cpus = { 1, 2, NO_CPU, NO_CPU },
		.bpmp_cluster_id = 0,
	},
	/* A57 cluster */
	{
		.offset = SZ_64K * 6,
		.cpus = { 0, 3, 4, 5 },
		.bpmp_cluster_id = 1,
	},
};

struct tegra186_cpufreq_cluster {
	const struct tegra186_cpufreq_cluster_info *info;
	struct cpufreq_frequency_table *table;
};

struct tegra186_cpufreq_data {
	void __iomem *regs;

	size_t num_clusters;
	struct tegra186_cpufreq_cluster *clusters;
};

static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
{
	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
	unsigned int i;

	for (i = 0; i < data->num_clusters; i++) {
		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
		const struct tegra186_cpufreq_cluster_info *info =
			cluster->info;
		int core;

		for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
			if (info->cpus[core] == policy->cpu)
				break;
		}
		if (core == ARRAY_SIZE(info->cpus))
			continue;

		policy->driver_data =
			data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
		policy->freq_table = cluster->table;
		break;
	}

	policy->cpuinfo.transition_latency = 300 * 1000;

	return 0;
}

static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
				       unsigned int index)
{
	struct cpufreq_frequency_table *tbl = policy->freq_table + index;
	void __iomem *edvd_reg = policy->driver_data;
	u32 edvd_val = tbl->driver_data;

	writel(edvd_val, edvd_reg);

	return 0;
}

static struct cpufreq_driver tegra186_cpufreq_driver = {
	.name = "tegra186",
	.flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = tegra186_cpufreq_set_target,
	.init = tegra186_cpufreq_init,
	.attr = cpufreq_generic_attr,
};

static struct cpufreq_frequency_table *init_vhint_table(
	struct platform_device *pdev, struct tegra_bpmp *bpmp,
	unsigned int cluster_id)
{
	struct cpufreq_frequency_table *table;
	struct mrq_cpu_vhint_request req;
	struct tegra_bpmp_message msg;
	struct cpu_vhint_data *data;
	int err, i, j, num_rates = 0;
	dma_addr_t phys;
	void *virt;

	virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
				  GFP_KERNEL);
	if (!virt)
		return ERR_PTR(-ENOMEM);

	data = (struct cpu_vhint_data *)virt;

	memset(&req, 0, sizeof(req));
	req.addr = phys;
	req.cluster_id = cluster_id;

	memset(&msg, 0, sizeof(msg));
	msg.mrq = MRQ_CPU_VHINT;
	msg.tx.data = &req;
	msg.tx.size = sizeof(req);

	err = tegra_bpmp_transfer(bpmp, &msg);
	if (err) {
		table = ERR_PTR(err);
		goto free;
	}

	for (i = data->vfloor; i <= data->vceil; i++) {
		u16 ndiv = data->ndiv[i];

		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
			continue;

		/* Only store lowest voltage index for each rate */
		if (i > 0 && ndiv == data->ndiv[i - 1])
			continue;

		num_rates++;
	}

	table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
			     GFP_KERNEL);
	if (!table) {
		table = ERR_PTR(-ENOMEM);
		goto free;
	}

	for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
		struct cpufreq_frequency_table *point;
		u16 ndiv = data->ndiv[i];
		u32 edvd_val = 0;

		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
			continue;

		/* Only store lowest voltage index for each rate */
		if (i > 0 && ndiv == data->ndiv[i - 1])
			continue;

		edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
		edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;

		point = &table[j++];
		point->driver_data = edvd_val;
		point->frequency = data->ref_clk_hz * ndiv / data->pdiv /
			data->mdiv / 1000;
	}

	table[j].frequency = CPUFREQ_TABLE_END;

free:
	dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);

	return table;
}

static int tegra186_cpufreq_probe(struct platform_device *pdev)
{
	struct tegra186_cpufreq_data *data;
	struct tegra_bpmp *bpmp;
	struct resource *res;
	unsigned int i = 0, err;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
				      sizeof(*data->clusters), GFP_KERNEL);
	if (!data->clusters)
		return -ENOMEM;

	data->num_clusters = ARRAY_SIZE(tegra186_clusters);

	bpmp = tegra_bpmp_get(&pdev->dev);
	if (IS_ERR(bpmp))
		return PTR_ERR(bpmp);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->regs)) {
		err = PTR_ERR(data->regs);
		goto put_bpmp;
	}

	for (i = 0; i < data->num_clusters; i++) {
		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];

		cluster->info = &tegra186_clusters[i];
		cluster->table = init_vhint_table(
			pdev, bpmp, cluster->info->bpmp_cluster_id);
		if (IS_ERR(cluster->table)) {
			err = PTR_ERR(cluster->table);
			goto put_bpmp;
		}
	}

	tegra_bpmp_put(bpmp);

	tegra186_cpufreq_driver.driver_data = data;

	err = cpufreq_register_driver(&tegra186_cpufreq_driver);
	if (err)
		return err;

	return 0;

put_bpmp:
	tegra_bpmp_put(bpmp);

	return err;
}

static int tegra186_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&tegra186_cpufreq_driver);

	return 0;
}

static const struct of_device_id tegra186_cpufreq_of_match[] = {
	{ .compatible = "nvidia,tegra186-ccplex-cluster", },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);

static struct platform_driver tegra186_cpufreq_platform_driver = {
	.driver = {
		.name = "tegra186-cpufreq",
		.of_match_table = tegra186_cpufreq_of_match,
	},
	.probe = tegra186_cpufreq_probe,
	.remove = tegra186_cpufreq_remove,
};
module_platform_driver(tegra186_cpufreq_platform_driver);

MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
939dc6f5 MP	2	/*
939dc6f5 MP	3	* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
939dc6f5 MP	4	*/
	5
	6	#include <linux/cpufreq.h>
	7	#include <linux/dma-mapping.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
	10	#include <linux/platform_device.h>
	11
	12	#include <soc/tegra/bpmp.h>
	13	#include <soc/tegra/bpmp-abi.h>
	14
	15	#define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4)
	16	#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
	17	#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
	18
	19	struct tegra186_cpufreq_cluster_info {
	20	unsigned long offset;
	21	int cpus[4];
	22	unsigned int bpmp_cluster_id;
	23	};
	24
	25	#define NO_CPU -1
	26	static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
	27	/* Denver cluster */
	28	{
	29	.offset = SZ_64K * 7,
	30	.cpus = { 1, 2, NO_CPU, NO_CPU },
	31	.bpmp_cluster_id = 0,
	32	},
	33	/* A57 cluster */
	34	{
	35	.offset = SZ_64K * 6,
	36	.cpus = { 0, 3, 4, 5 },
	37	.bpmp_cluster_id = 1,
	38	},
	39	};
	40
	41	struct tegra186_cpufreq_cluster {
	42	const struct tegra186_cpufreq_cluster_info *info;
	43	struct cpufreq_frequency_table *table;
	44	};
	45
	46	struct tegra186_cpufreq_data {
	47	void __iomem *regs;
	48
	49	size_t num_clusters;
	50	struct tegra186_cpufreq_cluster *clusters;
	51	};
	52
	53	static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
	54	{
	55	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
	56	unsigned int i;
	57
	58	for (i = 0; i < data->num_clusters; i++) {
	59	struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
	60	const struct tegra186_cpufreq_cluster_info *info =
	61	cluster->info;
	62	int core;
	63
	64	for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
	65	if (info->cpus[core] == policy->cpu)
	66	break;
	67	}
68	if (core == ARRAY_SIZE(info->cpus))
69	continue;
70
71	policy->driver_data =
72	data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
a8b69660	73	policy->freq_table = cluster->table;
3e3b507e	74	break;
939dc6f5 MP	75	}
	76
	77	policy->cpuinfo.transition_latency = 300 * 1000;
	78
	79	return 0;
	80	}
	81
	82	static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
	83	unsigned int index)
	84	{
	85	struct cpufreq_frequency_table *tbl = policy->freq_table + index;
	86	void __iomem *edvd_reg = policy->driver_data;
	87	u32 edvd_val = tbl->driver_data;
	88
	89	writel(edvd_val, edvd_reg);
	90
	91	return 0;
	92	}
	93
	94	static struct cpufreq_driver tegra186_cpufreq_driver = {
	95	.name = "tegra186",
	96	.flags = CPUFREQ_STICKY \| CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
	97	.verify = cpufreq_generic_frequency_table_verify,
	98	.target_index = tegra186_cpufreq_set_target,
	99	.init = tegra186_cpufreq_init,
	100	.attr = cpufreq_generic_attr,
	101	};
	102
	103	static struct cpufreq_frequency_table *init_vhint_table(
	104	struct platform_device pdev, struct tegra_bpmp bpmp,
	105	unsigned int cluster_id)
	106	{
	107	struct cpufreq_frequency_table *table;
	108	struct mrq_cpu_vhint_request req;
	109	struct tegra_bpmp_message msg;
	110	struct cpu_vhint_data *data;
	111	int err, i, j, num_rates = 0;
	112	dma_addr_t phys;
	113	void *virt;
	114
	115	virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
a3ade38d	116	GFP_KERNEL);
939dc6f5 MP	117	if (!virt)
	118	return ERR_PTR(-ENOMEM);
	119
	120	data = (struct cpu_vhint_data *)virt;
	121
	122	memset(&req, 0, sizeof(req));
	123	req.addr = phys;
	124	req.cluster_id = cluster_id;
	125
	126	memset(&msg, 0, sizeof(msg));
	127	msg.mrq = MRQ_CPU_VHINT;
	128	msg.tx.data = &req;
	129	msg.tx.size = sizeof(req);
	130
	131	err = tegra_bpmp_transfer(bpmp, &msg);
	132	if (err) {
	133	table = ERR_PTR(err);
	134	goto free;
	135	}
	136
	137	for (i = data->vfloor; i <= data->vceil; i++) {
	138	u16 ndiv = data->ndiv[i];
	139
	140	if (ndiv < data->ndiv_min \|\| ndiv > data->ndiv_max)
	141	continue;
	142
	143	/* Only store lowest voltage index for each rate */
	144	if (i > 0 && ndiv == data->ndiv[i - 1])
	145	continue;
	146
	147	num_rates++;
	148	}
	149
	150	table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
	151	GFP_KERNEL);
	152	if (!table) {
	153	table = ERR_PTR(-ENOMEM);
	154	goto free;
	155	}
	156
	157	for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
	158	struct cpufreq_frequency_table *point;
	159	u16 ndiv = data->ndiv[i];
	160	u32 edvd_val = 0;
	161
	162	if (ndiv < data->ndiv_min \|\| ndiv > data->ndiv_max)
	163	continue;
	164
	165	/* Only store lowest voltage index for each rate */
	166	if (i > 0 && ndiv == data->ndiv[i - 1])
	167	continue;
	168
	169	edvd_val \|= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
	170	edvd_val \|= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
	171
	172	point = &table[j++];
	173	point->driver_data = edvd_val;
	174	point->frequency = data->ref_clk_hz * ndiv / data->pdiv /
	175	data->mdiv / 1000;
	176	}
	177
	178	table[j].frequency = CPUFREQ_TABLE_END;
	179
	180	free:
181	dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
182
183	return table;
184	}
185
186	static int tegra186_cpufreq_probe(struct platform_device *pdev)
187	{
188	struct tegra186_cpufreq_data *data;
189	struct tegra_bpmp *bpmp;
190	struct resource *res;
191	unsigned int i = 0, err;
192
193	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
194	if (!data)
195	return -ENOMEM;
196
197	data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
198	sizeof(*data->clusters), GFP_KERNEL);
199	if (!data->clusters)
200	return -ENOMEM;
201
202	data->num_clusters = ARRAY_SIZE(tegra186_clusters);
203
204	bpmp = tegra_bpmp_get(&pdev->dev);
205	if (IS_ERR(bpmp))
206	return PTR_ERR(bpmp);
207
208	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
209	data->regs = devm_ioremap_resource(&pdev->dev, res);
210	if (IS_ERR(data->regs)) {
211	err = PTR_ERR(data->regs);
212	goto put_bpmp;
213	}
214
215	for (i = 0; i < data->num_clusters; i++) {
216	struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
217
218	cluster->info = &tegra186_clusters[i];
219	cluster->table = init_vhint_table(
220	pdev, bpmp, cluster->info->bpmp_cluster_id);
221	if (IS_ERR(cluster->table)) {
222	err = PTR_ERR(cluster->table);
223	goto put_bpmp;
224	}
225	}
226
227	tegra_bpmp_put(bpmp);
228
229	tegra186_cpufreq_driver.driver_data = data;
230
231	err = cpufreq_register_driver(&tegra186_cpufreq_driver);
232	if (err)
233	return err;
234
235	return 0;
236
237	put_bpmp:
238	tegra_bpmp_put(bpmp);
239
240	return err;
241	}
242
243	static int tegra186_cpufreq_remove(struct platform_device *pdev)
244	{
245	cpufreq_unregister_driver(&tegra186_cpufreq_driver);
246
247	return 0;
248	}
249
250	static const struct of_device_id tegra186_cpufreq_of_match[] = {
251	{ .compatible = "nvidia,tegra186-ccplex-cluster", },
252	{ }
253	};
254	MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
255
256	static struct platform_driver tegra186_cpufreq_platform_driver = {
257	.driver = {
258	.name = "tegra186-cpufreq",
259	.of_match_table = tegra186_cpufreq_of_match,
260	},
261	.probe = tegra186_cpufreq_probe,
262	.remove = tegra186_cpufreq_remove,
263	};
264	module_platform_driver(tegra186_cpufreq_platform_driver);
265
266	MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
267	MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
268	MODULE_LICENSE("GPL v2");