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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
939dc6f5 MP |
2 | /* |
3 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved | |
939dc6f5 MP |
4 | */ |
5 | ||
6 | #include <linux/cpufreq.h> | |
7 | #include <linux/dma-mapping.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/platform_device.h> | |
11 | ||
12 | #include <soc/tegra/bpmp.h> | |
13 | #include <soc/tegra/bpmp-abi.h> | |
14 | ||
15 | #define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4) | |
16 | #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 | |
17 | #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 | |
18 | ||
19 | struct tegra186_cpufreq_cluster_info { | |
20 | unsigned long offset; | |
21 | int cpus[4]; | |
22 | unsigned int bpmp_cluster_id; | |
23 | }; | |
24 | ||
25 | #define NO_CPU -1 | |
26 | static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = { | |
27 | /* Denver cluster */ | |
28 | { | |
29 | .offset = SZ_64K * 7, | |
30 | .cpus = { 1, 2, NO_CPU, NO_CPU }, | |
31 | .bpmp_cluster_id = 0, | |
32 | }, | |
33 | /* A57 cluster */ | |
34 | { | |
35 | .offset = SZ_64K * 6, | |
36 | .cpus = { 0, 3, 4, 5 }, | |
37 | .bpmp_cluster_id = 1, | |
38 | }, | |
39 | }; | |
40 | ||
41 | struct tegra186_cpufreq_cluster { | |
42 | const struct tegra186_cpufreq_cluster_info *info; | |
43 | struct cpufreq_frequency_table *table; | |
44 | }; | |
45 | ||
46 | struct tegra186_cpufreq_data { | |
47 | void __iomem *regs; | |
48 | ||
49 | size_t num_clusters; | |
50 | struct tegra186_cpufreq_cluster *clusters; | |
51 | }; | |
52 | ||
53 | static int tegra186_cpufreq_init(struct cpufreq_policy *policy) | |
54 | { | |
55 | struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); | |
56 | unsigned int i; | |
57 | ||
58 | for (i = 0; i < data->num_clusters; i++) { | |
59 | struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; | |
60 | const struct tegra186_cpufreq_cluster_info *info = | |
61 | cluster->info; | |
62 | int core; | |
63 | ||
64 | for (core = 0; core < ARRAY_SIZE(info->cpus); core++) { | |
65 | if (info->cpus[core] == policy->cpu) | |
66 | break; | |
67 | } | |
68 | if (core == ARRAY_SIZE(info->cpus)) | |
69 | continue; | |
70 | ||
71 | policy->driver_data = | |
72 | data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core); | |
a8b69660 | 73 | policy->freq_table = cluster->table; |
3e3b507e | 74 | break; |
939dc6f5 MP |
75 | } |
76 | ||
77 | policy->cpuinfo.transition_latency = 300 * 1000; | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, | |
83 | unsigned int index) | |
84 | { | |
85 | struct cpufreq_frequency_table *tbl = policy->freq_table + index; | |
86 | void __iomem *edvd_reg = policy->driver_data; | |
87 | u32 edvd_val = tbl->driver_data; | |
88 | ||
89 | writel(edvd_val, edvd_reg); | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | static struct cpufreq_driver tegra186_cpufreq_driver = { | |
95 | .name = "tegra186", | |
6cc3d0e9 MYK |
96 | .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY | |
97 | CPUFREQ_NEED_INITIAL_FREQ_CHECK, | |
939dc6f5 MP |
98 | .verify = cpufreq_generic_frequency_table_verify, |
99 | .target_index = tegra186_cpufreq_set_target, | |
100 | .init = tegra186_cpufreq_init, | |
101 | .attr = cpufreq_generic_attr, | |
102 | }; | |
103 | ||
104 | static struct cpufreq_frequency_table *init_vhint_table( | |
105 | struct platform_device *pdev, struct tegra_bpmp *bpmp, | |
106 | unsigned int cluster_id) | |
107 | { | |
108 | struct cpufreq_frequency_table *table; | |
109 | struct mrq_cpu_vhint_request req; | |
110 | struct tegra_bpmp_message msg; | |
111 | struct cpu_vhint_data *data; | |
112 | int err, i, j, num_rates = 0; | |
113 | dma_addr_t phys; | |
114 | void *virt; | |
115 | ||
116 | virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys, | |
a3ade38d | 117 | GFP_KERNEL); |
939dc6f5 MP |
118 | if (!virt) |
119 | return ERR_PTR(-ENOMEM); | |
120 | ||
121 | data = (struct cpu_vhint_data *)virt; | |
122 | ||
123 | memset(&req, 0, sizeof(req)); | |
124 | req.addr = phys; | |
125 | req.cluster_id = cluster_id; | |
126 | ||
127 | memset(&msg, 0, sizeof(msg)); | |
128 | msg.mrq = MRQ_CPU_VHINT; | |
129 | msg.tx.data = &req; | |
130 | msg.tx.size = sizeof(req); | |
131 | ||
132 | err = tegra_bpmp_transfer(bpmp, &msg); | |
133 | if (err) { | |
134 | table = ERR_PTR(err); | |
135 | goto free; | |
136 | } | |
137 | ||
138 | for (i = data->vfloor; i <= data->vceil; i++) { | |
139 | u16 ndiv = data->ndiv[i]; | |
140 | ||
141 | if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) | |
142 | continue; | |
143 | ||
144 | /* Only store lowest voltage index for each rate */ | |
145 | if (i > 0 && ndiv == data->ndiv[i - 1]) | |
146 | continue; | |
147 | ||
148 | num_rates++; | |
149 | } | |
150 | ||
151 | table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table), | |
152 | GFP_KERNEL); | |
153 | if (!table) { | |
154 | table = ERR_PTR(-ENOMEM); | |
155 | goto free; | |
156 | } | |
157 | ||
158 | for (i = data->vfloor, j = 0; i <= data->vceil; i++) { | |
159 | struct cpufreq_frequency_table *point; | |
160 | u16 ndiv = data->ndiv[i]; | |
161 | u32 edvd_val = 0; | |
162 | ||
163 | if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) | |
164 | continue; | |
165 | ||
166 | /* Only store lowest voltage index for each rate */ | |
167 | if (i > 0 && ndiv == data->ndiv[i - 1]) | |
168 | continue; | |
169 | ||
170 | edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT; | |
171 | edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; | |
172 | ||
173 | point = &table[j++]; | |
174 | point->driver_data = edvd_val; | |
175 | point->frequency = data->ref_clk_hz * ndiv / data->pdiv / | |
176 | data->mdiv / 1000; | |
177 | } | |
178 | ||
179 | table[j].frequency = CPUFREQ_TABLE_END; | |
180 | ||
181 | free: | |
182 | dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys); | |
183 | ||
184 | return table; | |
185 | } | |
186 | ||
187 | static int tegra186_cpufreq_probe(struct platform_device *pdev) | |
188 | { | |
189 | struct tegra186_cpufreq_data *data; | |
190 | struct tegra_bpmp *bpmp; | |
939dc6f5 MP |
191 | unsigned int i = 0, err; |
192 | ||
193 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
194 | if (!data) | |
195 | return -ENOMEM; | |
196 | ||
197 | data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters), | |
198 | sizeof(*data->clusters), GFP_KERNEL); | |
199 | if (!data->clusters) | |
200 | return -ENOMEM; | |
201 | ||
202 | data->num_clusters = ARRAY_SIZE(tegra186_clusters); | |
203 | ||
204 | bpmp = tegra_bpmp_get(&pdev->dev); | |
205 | if (IS_ERR(bpmp)) | |
206 | return PTR_ERR(bpmp); | |
207 | ||
308beafc | 208 | data->regs = devm_platform_ioremap_resource(pdev, 0); |
939dc6f5 MP |
209 | if (IS_ERR(data->regs)) { |
210 | err = PTR_ERR(data->regs); | |
211 | goto put_bpmp; | |
212 | } | |
213 | ||
214 | for (i = 0; i < data->num_clusters; i++) { | |
215 | struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; | |
216 | ||
217 | cluster->info = &tegra186_clusters[i]; | |
218 | cluster->table = init_vhint_table( | |
219 | pdev, bpmp, cluster->info->bpmp_cluster_id); | |
220 | if (IS_ERR(cluster->table)) { | |
221 | err = PTR_ERR(cluster->table); | |
222 | goto put_bpmp; | |
223 | } | |
224 | } | |
225 | ||
939dc6f5 MP |
226 | tegra186_cpufreq_driver.driver_data = data; |
227 | ||
228 | err = cpufreq_register_driver(&tegra186_cpufreq_driver); | |
939dc6f5 MP |
229 | |
230 | put_bpmp: | |
231 | tegra_bpmp_put(bpmp); | |
232 | ||
233 | return err; | |
234 | } | |
235 | ||
236 | static int tegra186_cpufreq_remove(struct platform_device *pdev) | |
237 | { | |
238 | cpufreq_unregister_driver(&tegra186_cpufreq_driver); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static const struct of_device_id tegra186_cpufreq_of_match[] = { | |
244 | { .compatible = "nvidia,tegra186-ccplex-cluster", }, | |
245 | { } | |
246 | }; | |
247 | MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match); | |
248 | ||
249 | static struct platform_driver tegra186_cpufreq_platform_driver = { | |
250 | .driver = { | |
251 | .name = "tegra186-cpufreq", | |
252 | .of_match_table = tegra186_cpufreq_of_match, | |
253 | }, | |
254 | .probe = tegra186_cpufreq_probe, | |
255 | .remove = tegra186_cpufreq_remove, | |
256 | }; | |
257 | module_platform_driver(tegra186_cpufreq_platform_driver); | |
258 | ||
259 | MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); | |
260 | MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver"); | |
261 | MODULE_LICENSE("GPL v2"); |