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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
be2de99b | 2 | /* |
b3748ddd MB |
3 | * Copyright 2009 Wolfson Microelectronics plc |
4 | * | |
5 | * S3C64xx CPUfreq Support | |
b3748ddd MB |
6 | */ |
7 | ||
a6a43412 MB |
8 | #define pr_fmt(fmt) "cpufreq: " fmt |
9 | ||
b3748ddd MB |
10 | #include <linux/kernel.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/cpufreq.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/regulator/consumer.h> | |
a6ee8779 | 17 | #include <linux/module.h> |
b3748ddd | 18 | |
b3748ddd | 19 | static struct regulator *vddarm; |
43f1069e | 20 | static unsigned long regulator_latency; |
b3748ddd MB |
21 | |
22 | #ifdef CONFIG_CPU_S3C6410 | |
23 | struct s3c64xx_dvfs { | |
24 | unsigned int vddarm_min; | |
25 | unsigned int vddarm_max; | |
26 | }; | |
27 | ||
28 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { | |
e9c08f0d MB |
29 | [0] = { 1000000, 1150000 }, |
30 | [1] = { 1050000, 1150000 }, | |
31 | [2] = { 1100000, 1150000 }, | |
32 | [3] = { 1200000, 1350000 }, | |
c6e2d685 | 33 | [4] = { 1300000, 1350000 }, |
b3748ddd MB |
34 | }; |
35 | ||
36 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | |
7f4b0461 VK |
37 | { 0, 0, 66000 }, |
38 | { 0, 0, 100000 }, | |
39 | { 0, 0, 133000 }, | |
40 | { 0, 1, 200000 }, | |
41 | { 0, 1, 222000 }, | |
42 | { 0, 1, 266000 }, | |
43 | { 0, 2, 333000 }, | |
44 | { 0, 2, 400000 }, | |
45 | { 0, 2, 532000 }, | |
46 | { 0, 2, 533000 }, | |
47 | { 0, 3, 667000 }, | |
48 | { 0, 4, 800000 }, | |
49 | { 0, 0, CPUFREQ_TABLE_END }, | |
b3748ddd MB |
50 | }; |
51 | #endif | |
52 | ||
b3748ddd | 53 | static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, |
9c0ebcf7 | 54 | unsigned int index) |
b3748ddd | 55 | { |
b3748ddd | 56 | struct s3c64xx_dvfs *dvfs; |
d4019f0a VK |
57 | unsigned int old_freq, new_freq; |
58 | int ret; | |
b3748ddd | 59 | |
652ed95d | 60 | old_freq = clk_get_rate(policy->clk) / 1000; |
d4019f0a | 61 | new_freq = s3c64xx_freq_table[index].frequency; |
9c0ebcf7 | 62 | dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; |
b3748ddd | 63 | |
b3748ddd | 64 | #ifdef CONFIG_REGULATOR |
d4019f0a | 65 | if (vddarm && new_freq > old_freq) { |
b3748ddd MB |
66 | ret = regulator_set_voltage(vddarm, |
67 | dvfs->vddarm_min, | |
68 | dvfs->vddarm_max); | |
69 | if (ret != 0) { | |
a6a43412 | 70 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
d4019f0a VK |
71 | new_freq, ret); |
72 | return ret; | |
b3748ddd MB |
73 | } |
74 | } | |
75 | #endif | |
76 | ||
652ed95d | 77 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
b3748ddd | 78 | if (ret < 0) { |
a6a43412 | 79 | pr_err("Failed to set rate %dkHz: %d\n", |
d4019f0a VK |
80 | new_freq, ret); |
81 | return ret; | |
b3748ddd MB |
82 | } |
83 | ||
84 | #ifdef CONFIG_REGULATOR | |
d4019f0a | 85 | if (vddarm && new_freq < old_freq) { |
b3748ddd MB |
86 | ret = regulator_set_voltage(vddarm, |
87 | dvfs->vddarm_min, | |
88 | dvfs->vddarm_max); | |
89 | if (ret != 0) { | |
a6a43412 | 90 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
d4019f0a | 91 | new_freq, ret); |
652ed95d | 92 | if (clk_set_rate(policy->clk, old_freq * 1000) < 0) |
d4019f0a VK |
93 | pr_err("Failed to restore original clock rate\n"); |
94 | ||
95 | return ret; | |
b3748ddd MB |
96 | } |
97 | } | |
98 | #endif | |
99 | ||
a6a43412 | 100 | pr_debug("Set actual frequency %lukHz\n", |
652ed95d | 101 | clk_get_rate(policy->clk) / 1000); |
b3748ddd MB |
102 | |
103 | return 0; | |
b3748ddd MB |
104 | } |
105 | ||
106 | #ifdef CONFIG_REGULATOR | |
adec57c6 | 107 | static void s3c64xx_cpufreq_config_regulator(void) |
b3748ddd MB |
108 | { |
109 | int count, v, i, found; | |
110 | struct cpufreq_frequency_table *freq; | |
111 | struct s3c64xx_dvfs *dvfs; | |
112 | ||
113 | count = regulator_count_voltages(vddarm); | |
114 | if (count < 0) { | |
a6a43412 | 115 | pr_err("Unable to check supported voltages\n"); |
b3748ddd MB |
116 | } |
117 | ||
041526f9 SK |
118 | if (!count) |
119 | goto out; | |
b3748ddd | 120 | |
041526f9 | 121 | cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) { |
0e824432 | 122 | dvfs = &s3c64xx_dvfs_table[freq->driver_data]; |
b3748ddd MB |
123 | found = 0; |
124 | ||
125 | for (i = 0; i < count; i++) { | |
126 | v = regulator_list_voltage(vddarm, i); | |
127 | if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) | |
128 | found = 1; | |
129 | } | |
130 | ||
131 | if (!found) { | |
a6a43412 | 132 | pr_debug("%dkHz unsupported by regulator\n", |
b3748ddd MB |
133 | freq->frequency); |
134 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
135 | } | |
b3748ddd | 136 | } |
43f1069e | 137 | |
041526f9 | 138 | out: |
43f1069e MB |
139 | /* Guess based on having to do an I2C/SPI write; in future we |
140 | * will be able to query the regulator performance here. */ | |
141 | regulator_latency = 1 * 1000 * 1000; | |
b3748ddd MB |
142 | } |
143 | #endif | |
144 | ||
6d0de157 | 145 | static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) |
b3748ddd MB |
146 | { |
147 | int ret; | |
148 | struct cpufreq_frequency_table *freq; | |
149 | ||
150 | if (policy->cpu != 0) | |
151 | return -EINVAL; | |
152 | ||
153 | if (s3c64xx_freq_table == NULL) { | |
a6a43412 | 154 | pr_err("No frequency information for this CPU\n"); |
b3748ddd MB |
155 | return -ENODEV; |
156 | } | |
157 | ||
652ed95d VK |
158 | policy->clk = clk_get(NULL, "armclk"); |
159 | if (IS_ERR(policy->clk)) { | |
a6a43412 | 160 | pr_err("Unable to obtain ARMCLK: %ld\n", |
652ed95d VK |
161 | PTR_ERR(policy->clk)); |
162 | return PTR_ERR(policy->clk); | |
b3748ddd MB |
163 | } |
164 | ||
165 | #ifdef CONFIG_REGULATOR | |
166 | vddarm = regulator_get(NULL, "vddarm"); | |
167 | if (IS_ERR(vddarm)) { | |
168 | ret = PTR_ERR(vddarm); | |
a6a43412 MB |
169 | pr_err("Failed to obtain VDDARM: %d\n", ret); |
170 | pr_err("Only frequency scaling available\n"); | |
b3748ddd MB |
171 | vddarm = NULL; |
172 | } else { | |
43f1069e | 173 | s3c64xx_cpufreq_config_regulator(); |
b3748ddd MB |
174 | } |
175 | #endif | |
176 | ||
041526f9 | 177 | cpufreq_for_each_entry(freq, s3c64xx_freq_table) { |
b3748ddd MB |
178 | unsigned long r; |
179 | ||
180 | /* Check for frequencies we can generate */ | |
652ed95d | 181 | r = clk_round_rate(policy->clk, freq->frequency * 1000); |
b3748ddd | 182 | r /= 1000; |
383af9c2 | 183 | if (r != freq->frequency) { |
a6a43412 | 184 | pr_debug("%dkHz unsupported by clock\n", |
383af9c2 | 185 | freq->frequency); |
b3748ddd | 186 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
383af9c2 | 187 | } |
b3748ddd MB |
188 | |
189 | /* If we have no regulator then assume startup | |
190 | * frequency is the maximum we can support. */ | |
652ed95d | 191 | if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) |
b3748ddd | 192 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
b3748ddd MB |
193 | } |
194 | ||
43f1069e MB |
195 | /* Datasheet says PLL stabalisation time (if we were to use |
196 | * the PLLs, which we don't currently) is ~300us worst case, | |
197 | * but add some fudge. | |
198 | */ | |
a307a1e6 VK |
199 | ret = cpufreq_generic_init(policy, s3c64xx_freq_table, |
200 | (500 * 1000) + regulator_latency); | |
b3748ddd | 201 | if (ret != 0) { |
a6a43412 | 202 | pr_err("Failed to configure frequency table: %d\n", |
b3748ddd MB |
203 | ret); |
204 | regulator_put(vddarm); | |
652ed95d | 205 | clk_put(policy->clk); |
b3748ddd MB |
206 | } |
207 | ||
208 | return ret; | |
209 | } | |
210 | ||
211 | static struct cpufreq_driver s3c64xx_cpufreq_driver = { | |
ae6b4271 | 212 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
e96a4105 | 213 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 214 | .target_index = s3c64xx_cpufreq_set_target, |
652ed95d | 215 | .get = cpufreq_generic_get, |
b3748ddd MB |
216 | .init = s3c64xx_cpufreq_driver_init, |
217 | .name = "s3c", | |
218 | }; | |
219 | ||
220 | static int __init s3c64xx_cpufreq_init(void) | |
221 | { | |
222 | return cpufreq_register_driver(&s3c64xx_cpufreq_driver); | |
223 | } | |
224 | module_init(s3c64xx_cpufreq_init); |