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09ec1d7e | 1 | /* |
e02f8664 | 2 | * Copyright (c) 2006-2008 Simtec Electronics |
2e4ea6e8 BD |
3 | * http://armlinux.simtec.co.uk/ |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX CPU Frequency scaling | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/cpufreq.h> | |
18 | #include <linux/cpu.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/io.h> | |
edbaa603 | 22 | #include <linux/device.h> |
2e4ea6e8 | 23 | #include <linux/sysfs.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2e4ea6e8 BD |
25 | |
26 | #include <asm/mach/arch.h> | |
27 | #include <asm/mach/map.h> | |
28 | ||
29 | #include <plat/cpu.h> | |
30 | #include <plat/clock.h> | |
31 | #include <plat/cpu-freq-core.h> | |
32 | ||
33 | #include <mach/regs-clock.h> | |
34 | ||
35 | /* note, cpufreq support deals in kHz, no Hz */ | |
36 | ||
37 | static struct cpufreq_driver s3c24xx_driver; | |
38 | static struct s3c_cpufreq_config cpu_cur; | |
39 | static struct s3c_iotimings s3c24xx_iotiming; | |
40 | static struct cpufreq_frequency_table *pll_reg; | |
41 | static unsigned int last_target = ~0; | |
42 | static unsigned int ftab_size; | |
43 | static struct cpufreq_frequency_table *ftab; | |
44 | ||
45 | static struct clk *_clk_mpll; | |
46 | static struct clk *_clk_xtal; | |
47 | static struct clk *clk_fclk; | |
48 | static struct clk *clk_hclk; | |
49 | static struct clk *clk_pclk; | |
50 | static struct clk *clk_arm; | |
51 | ||
4a6c4108 | 52 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS |
e6d197a6 BD |
53 | struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) |
54 | { | |
55 | return &cpu_cur; | |
56 | } | |
57 | ||
58 | struct s3c_iotimings *s3c_cpufreq_getiotimings(void) | |
59 | { | |
60 | return &s3c24xx_iotiming; | |
61 | } | |
4a6c4108 | 62 | #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */ |
e6d197a6 | 63 | |
2e4ea6e8 BD |
64 | static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) |
65 | { | |
66 | unsigned long fclk, pclk, hclk, armclk; | |
67 | ||
68 | cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); | |
69 | cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); | |
70 | cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); | |
71 | cfg->freq.armclk = armclk = clk_get_rate(clk_arm); | |
72 | ||
50701588 | 73 | cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
2e4ea6e8 BD |
74 | cfg->pll.frequency = fclk; |
75 | ||
76 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
77 | ||
78 | cfg->divs.h_divisor = fclk / hclk; | |
79 | cfg->divs.p_divisor = fclk / pclk; | |
80 | } | |
81 | ||
82 | static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) | |
83 | { | |
84 | unsigned long pll = cfg->pll.frequency; | |
85 | ||
86 | cfg->freq.fclk = pll; | |
87 | cfg->freq.hclk = pll / cfg->divs.h_divisor; | |
88 | cfg->freq.pclk = pll / cfg->divs.p_divisor; | |
89 | ||
90 | /* convert hclk into 10ths of nanoseconds for io calcs */ | |
91 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
92 | } | |
93 | ||
94 | static inline int closer(unsigned int target, unsigned int n, unsigned int c) | |
95 | { | |
96 | int diff_cur = abs(target - c); | |
97 | int diff_new = abs(target - n); | |
98 | ||
99 | return (diff_new < diff_cur); | |
100 | } | |
101 | ||
102 | static void s3c_cpufreq_show(const char *pfx, | |
103 | struct s3c_cpufreq_config *cfg) | |
104 | { | |
105 | s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", | |
106 | pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, | |
107 | cfg->freq.hclk, cfg->divs.h_divisor, | |
108 | cfg->freq.pclk, cfg->divs.p_divisor); | |
109 | } | |
110 | ||
111 | /* functions to wrapper the driver info calls to do the cpu specific work */ | |
112 | ||
113 | static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) | |
114 | { | |
115 | if (cfg->info->set_iotiming) | |
116 | (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); | |
117 | } | |
118 | ||
119 | static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) | |
120 | { | |
121 | if (cfg->info->calc_iotiming) | |
122 | return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | |
128 | { | |
129 | (cfg->info->set_refresh)(cfg); | |
130 | } | |
131 | ||
132 | static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | |
133 | { | |
134 | (cfg->info->set_divs)(cfg); | |
135 | } | |
136 | ||
137 | static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | |
138 | { | |
139 | return (cfg->info->calc_divs)(cfg); | |
140 | } | |
141 | ||
142 | static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) | |
143 | { | |
d8b53257 | 144 | cfg->mpll = _clk_mpll; |
2e4ea6e8 BD |
145 | (cfg->info->set_fvco)(cfg); |
146 | } | |
147 | ||
148 | static inline void s3c_cpufreq_resume_clocks(void) | |
149 | { | |
150 | cpu_cur.info->resume_clocks(); | |
151 | } | |
152 | ||
153 | static inline void s3c_cpufreq_updateclk(struct clk *clk, | |
154 | unsigned int freq) | |
155 | { | |
156 | clk_set_rate(clk, freq); | |
157 | } | |
158 | ||
159 | static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, | |
160 | unsigned int target_freq, | |
161 | struct cpufreq_frequency_table *pll) | |
162 | { | |
163 | struct s3c_cpufreq_freqs freqs; | |
164 | struct s3c_cpufreq_config cpu_new; | |
165 | unsigned long flags; | |
166 | ||
167 | cpu_new = cpu_cur; /* copy new from current */ | |
168 | ||
169 | s3c_cpufreq_show("cur", &cpu_cur); | |
170 | ||
171 | /* TODO - check for DMA currently outstanding */ | |
172 | ||
173 | cpu_new.pll = pll ? *pll : cpu_cur.pll; | |
174 | ||
175 | if (pll) | |
176 | freqs.pll_changing = 1; | |
177 | ||
178 | /* update our frequencies */ | |
179 | ||
180 | cpu_new.freq.armclk = target_freq; | |
181 | cpu_new.freq.fclk = cpu_new.pll.frequency; | |
182 | ||
183 | if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { | |
184 | printk(KERN_ERR "no divisors for %d\n", target_freq); | |
185 | goto err_notpossible; | |
186 | } | |
187 | ||
188 | s3c_freq_dbg("%s: got divs\n", __func__); | |
189 | ||
190 | s3c_cpufreq_calc(&cpu_new); | |
191 | ||
192 | s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); | |
193 | ||
194 | if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { | |
195 | if (s3c_cpufreq_calcio(&cpu_new) < 0) { | |
196 | printk(KERN_ERR "%s: no IO timings\n", __func__); | |
197 | goto err_notpossible; | |
198 | } | |
199 | } | |
200 | ||
201 | s3c_cpufreq_show("new", &cpu_new); | |
202 | ||
203 | /* setup our cpufreq parameters */ | |
204 | ||
205 | freqs.old = cpu_cur.freq; | |
206 | freqs.new = cpu_new.freq; | |
207 | ||
2e4ea6e8 BD |
208 | freqs.freqs.old = cpu_cur.freq.armclk / 1000; |
209 | freqs.freqs.new = cpu_new.freq.armclk / 1000; | |
210 | ||
211 | /* update f/h/p clock settings before we issue the change | |
212 | * notification, so that drivers do not need to do anything | |
213 | * special if they want to recalculate on CPUFREQ_PRECHANGE. */ | |
214 | ||
215 | s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); | |
216 | s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); | |
217 | s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); | |
218 | s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); | |
219 | ||
220 | /* start the frequency change */ | |
8fec051e | 221 | cpufreq_freq_transition_begin(policy, &freqs.freqs); |
2e4ea6e8 BD |
222 | |
223 | /* If hclk is staying the same, then we do not need to | |
224 | * re-write the IO or the refresh timings whilst we are changing | |
225 | * speed. */ | |
226 | ||
227 | local_irq_save(flags); | |
228 | ||
229 | /* is our memory clock slowing down? */ | |
230 | if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { | |
231 | s3c_cpufreq_setrefresh(&cpu_new); | |
232 | s3c_cpufreq_setio(&cpu_new); | |
233 | } | |
234 | ||
235 | if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { | |
236 | /* not changing PLL, just set the divisors */ | |
237 | ||
238 | s3c_cpufreq_setdivs(&cpu_new); | |
239 | } else { | |
240 | if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { | |
241 | /* slow the cpu down, then set divisors */ | |
242 | ||
243 | s3c_cpufreq_setfvco(&cpu_new); | |
244 | s3c_cpufreq_setdivs(&cpu_new); | |
245 | } else { | |
246 | /* set the divisors, then speed up */ | |
247 | ||
248 | s3c_cpufreq_setdivs(&cpu_new); | |
249 | s3c_cpufreq_setfvco(&cpu_new); | |
250 | } | |
251 | } | |
252 | ||
253 | /* did our memory clock speed up */ | |
254 | if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { | |
255 | s3c_cpufreq_setrefresh(&cpu_new); | |
256 | s3c_cpufreq_setio(&cpu_new); | |
257 | } | |
258 | ||
259 | /* update our current settings */ | |
260 | cpu_cur = cpu_new; | |
261 | ||
262 | local_irq_restore(flags); | |
263 | ||
264 | /* notify everyone we've done this */ | |
8fec051e | 265 | cpufreq_freq_transition_end(policy, &freqs.freqs, 0); |
2e4ea6e8 BD |
266 | |
267 | s3c_freq_dbg("%s: finished\n", __func__); | |
268 | return 0; | |
269 | ||
270 | err_notpossible: | |
271 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | |
272 | return -EINVAL; | |
273 | } | |
274 | ||
275 | /* s3c_cpufreq_target | |
276 | * | |
277 | * called by the cpufreq core to adjust the frequency that the CPU | |
278 | * is currently running at. | |
279 | */ | |
280 | ||
281 | static int s3c_cpufreq_target(struct cpufreq_policy *policy, | |
282 | unsigned int target_freq, | |
283 | unsigned int relation) | |
284 | { | |
285 | struct cpufreq_frequency_table *pll; | |
286 | unsigned int index; | |
287 | ||
288 | /* avoid repeated calls which cause a needless amout of duplicated | |
289 | * logging output (and CPU time as the calculation process is | |
290 | * done) */ | |
291 | if (target_freq == last_target) | |
292 | return 0; | |
293 | ||
294 | last_target = target_freq; | |
295 | ||
296 | s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", | |
297 | __func__, policy, target_freq, relation); | |
298 | ||
299 | if (ftab) { | |
300 | if (cpufreq_frequency_table_target(policy, ftab, | |
301 | target_freq, relation, | |
302 | &index)) { | |
303 | s3c_freq_dbg("%s: table failed\n", __func__); | |
304 | return -EINVAL; | |
305 | } | |
306 | ||
307 | s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, | |
308 | target_freq, index, ftab[index].frequency); | |
309 | target_freq = ftab[index].frequency; | |
310 | } | |
311 | ||
312 | target_freq *= 1000; /* convert target to Hz */ | |
313 | ||
314 | /* find the settings for our new frequency */ | |
315 | ||
316 | if (!pll_reg || cpu_cur.lock_pll) { | |
317 | /* either we've not got any PLL values, or we've locked | |
318 | * to the current one. */ | |
319 | pll = NULL; | |
320 | } else { | |
321 | struct cpufreq_policy tmp_policy; | |
322 | int ret; | |
323 | ||
324 | /* we keep the cpu pll table in Hz, to ensure we get an | |
325 | * accurate value for the PLL output. */ | |
326 | ||
327 | tmp_policy.min = policy->min * 1000; | |
328 | tmp_policy.max = policy->max * 1000; | |
329 | tmp_policy.cpu = policy->cpu; | |
330 | ||
331 | /* cpufreq_frequency_table_target uses a pointer to 'index' | |
332 | * which is the number of the table entry, not the value of | |
333 | * the table entry's index field. */ | |
334 | ||
335 | ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, | |
336 | target_freq, relation, | |
337 | &index); | |
338 | ||
339 | if (ret < 0) { | |
340 | printk(KERN_ERR "%s: no PLL available\n", __func__); | |
341 | goto err_notpossible; | |
342 | } | |
343 | ||
344 | pll = pll_reg + index; | |
345 | ||
346 | s3c_freq_dbg("%s: target %u => %u\n", | |
347 | __func__, target_freq, pll->frequency); | |
348 | ||
349 | target_freq = pll->frequency; | |
350 | } | |
351 | ||
352 | return s3c_cpufreq_settarget(policy, target_freq, pll); | |
353 | ||
354 | err_notpossible: | |
355 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | |
356 | return -EINVAL; | |
357 | } | |
358 | ||
2e4ea6e8 BD |
359 | struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) |
360 | { | |
361 | struct clk *clk; | |
362 | ||
363 | clk = clk_get(dev, name); | |
364 | if (IS_ERR(clk)) | |
365 | printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); | |
366 | ||
367 | return clk; | |
368 | } | |
369 | ||
370 | static int s3c_cpufreq_init(struct cpufreq_policy *policy) | |
371 | { | |
652ed95d | 372 | policy->clk = clk_arm; |
a307a1e6 | 373 | return cpufreq_generic_init(policy, ftab, cpu_cur.info->latency); |
2e4ea6e8 BD |
374 | } |
375 | ||
21b4c415 | 376 | static int __init s3c_cpufreq_initclks(void) |
2e4ea6e8 BD |
377 | { |
378 | _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); | |
379 | _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | |
380 | clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | |
381 | clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | |
382 | clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); | |
383 | clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); | |
384 | ||
385 | if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || | |
386 | IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { | |
387 | printk(KERN_ERR "%s: could not get clock(s)\n", __func__); | |
388 | return -ENOENT; | |
389 | } | |
390 | ||
391 | printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, | |
392 | clk_get_rate(clk_fclk) / 1000, | |
393 | clk_get_rate(clk_hclk) / 1000, | |
394 | clk_get_rate(clk_pclk) / 1000, | |
395 | clk_get_rate(clk_arm) / 1000); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
2e4ea6e8 BD |
400 | #ifdef CONFIG_PM |
401 | static struct cpufreq_frequency_table suspend_pll; | |
402 | static unsigned int suspend_freq; | |
403 | ||
7ca64e2d | 404 | static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) |
2e4ea6e8 BD |
405 | { |
406 | suspend_pll.frequency = clk_get_rate(_clk_mpll); | |
50701588 | 407 | suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
652ed95d | 408 | suspend_freq = clk_get_rate(clk_arm); |
2e4ea6e8 BD |
409 | |
410 | return 0; | |
411 | } | |
412 | ||
413 | static int s3c_cpufreq_resume(struct cpufreq_policy *policy) | |
414 | { | |
415 | int ret; | |
416 | ||
417 | s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); | |
418 | ||
419 | last_target = ~0; /* invalidate last_target setting */ | |
420 | ||
421 | /* first, find out what speed we resumed at. */ | |
422 | s3c_cpufreq_resume_clocks(); | |
423 | ||
424 | /* whilst we will be called later on, we try and re-set the | |
425 | * cpu frequencies as soon as possible so that we do not end | |
25985edc | 426 | * up resuming devices and then immediately having to re-set |
2e4ea6e8 BD |
427 | * a number of settings once these devices have restarted. |
428 | * | |
429 | * as a note, it is expected devices are not used until they | |
430 | * have been un-suspended and at that time they should have | |
431 | * used the updated clock settings. | |
432 | */ | |
433 | ||
434 | ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); | |
435 | if (ret) { | |
436 | printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); | |
437 | return ret; | |
438 | } | |
439 | ||
440 | return 0; | |
441 | } | |
442 | #else | |
443 | #define s3c_cpufreq_resume NULL | |
444 | #define s3c_cpufreq_suspend NULL | |
445 | #endif | |
446 | ||
447 | static struct cpufreq_driver s3c24xx_driver = { | |
ae6b4271 | 448 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
2e4ea6e8 | 449 | .target = s3c_cpufreq_target, |
652ed95d | 450 | .get = cpufreq_generic_get, |
2e4ea6e8 BD |
451 | .init = s3c_cpufreq_init, |
452 | .suspend = s3c_cpufreq_suspend, | |
453 | .resume = s3c_cpufreq_resume, | |
454 | .name = "s3c24xx", | |
455 | }; | |
456 | ||
457 | ||
458 | int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) | |
459 | { | |
460 | if (!info || !info->name) { | |
461 | printk(KERN_ERR "%s: failed to pass valid information\n", | |
462 | __func__); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", | |
467 | info->name); | |
468 | ||
469 | /* check our driver info has valid data */ | |
470 | ||
471 | BUG_ON(info->set_refresh == NULL); | |
472 | BUG_ON(info->set_divs == NULL); | |
473 | BUG_ON(info->calc_divs == NULL); | |
474 | ||
475 | /* info->set_fvco is optional, depending on whether there | |
476 | * is a need to set the clock code. */ | |
477 | ||
478 | cpu_cur.info = info; | |
479 | ||
480 | /* Note, driver registering should probably update locktime */ | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | |
486 | { | |
487 | struct s3c_cpufreq_board *ours; | |
488 | ||
489 | if (!board) { | |
490 | printk(KERN_INFO "%s: no board data\n", __func__); | |
491 | return -EINVAL; | |
492 | } | |
493 | ||
494 | /* Copy the board information so that each board can make this | |
495 | * initdata. */ | |
496 | ||
d5b73cd8 | 497 | ours = kzalloc(sizeof(*ours), GFP_KERNEL); |
2e4ea6e8 BD |
498 | if (ours == NULL) { |
499 | printk(KERN_ERR "%s: no memory\n", __func__); | |
500 | return -ENOMEM; | |
501 | } | |
502 | ||
503 | *ours = *board; | |
504 | cpu_cur.board = ours; | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
87ae97f1 | 509 | static int __init s3c_cpufreq_auto_io(void) |
2e4ea6e8 BD |
510 | { |
511 | int ret; | |
512 | ||
513 | if (!cpu_cur.info->get_iotiming) { | |
514 | printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); | |
515 | return -ENOENT; | |
516 | } | |
517 | ||
518 | printk(KERN_INFO "%s: working out IO settings\n", __func__); | |
519 | ||
520 | ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); | |
521 | if (ret) | |
522 | printk(KERN_ERR "%s: failed to get timings\n", __func__); | |
523 | ||
524 | return ret; | |
525 | } | |
526 | ||
527 | /* if one or is zero, then return the other, otherwise return the min */ | |
528 | #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) | |
529 | ||
530 | /** | |
531 | * s3c_cpufreq_freq_min - find the minimum settings for the given freq. | |
532 | * @dst: The destination structure | |
533 | * @a: One argument. | |
534 | * @b: The other argument. | |
535 | * | |
536 | * Create a minimum of each frequency entry in the 'struct s3c_freq', | |
537 | * unless the entry is zero when it is ignored and the non-zero argument | |
538 | * used. | |
539 | */ | |
540 | static void s3c_cpufreq_freq_min(struct s3c_freq *dst, | |
541 | struct s3c_freq *a, struct s3c_freq *b) | |
542 | { | |
543 | dst->fclk = do_min(a->fclk, b->fclk); | |
544 | dst->hclk = do_min(a->hclk, b->hclk); | |
545 | dst->pclk = do_min(a->pclk, b->pclk); | |
546 | dst->armclk = do_min(a->armclk, b->armclk); | |
547 | } | |
548 | ||
549 | static inline u32 calc_locktime(u32 freq, u32 time_us) | |
550 | { | |
551 | u32 result; | |
552 | ||
553 | result = freq * time_us; | |
554 | result = DIV_ROUND_UP(result, 1000 * 1000); | |
555 | ||
556 | return result; | |
557 | } | |
558 | ||
559 | static void s3c_cpufreq_update_loctkime(void) | |
560 | { | |
561 | unsigned int bits = cpu_cur.info->locktime_bits; | |
562 | u32 rate = (u32)clk_get_rate(_clk_xtal); | |
563 | u32 val; | |
564 | ||
565 | if (bits == 0) { | |
566 | WARN_ON(1); | |
567 | return; | |
568 | } | |
569 | ||
570 | val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; | |
571 | val |= calc_locktime(rate, cpu_cur.info->locktime_m); | |
572 | ||
573 | printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); | |
574 | __raw_writel(val, S3C2410_LOCKTIME); | |
575 | } | |
576 | ||
577 | static int s3c_cpufreq_build_freq(void) | |
578 | { | |
579 | int size, ret; | |
580 | ||
581 | if (!cpu_cur.info->calc_freqtable) | |
582 | return -EINVAL; | |
583 | ||
584 | kfree(ftab); | |
585 | ftab = NULL; | |
586 | ||
587 | size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); | |
588 | size++; | |
589 | ||
71508a1f | 590 | ftab = kzalloc(sizeof(*ftab) * size, GFP_KERNEL); |
2e4ea6e8 BD |
591 | if (!ftab) { |
592 | printk(KERN_ERR "%s: no memory for tables\n", __func__); | |
593 | return -ENOMEM; | |
594 | } | |
595 | ||
596 | ftab_size = size; | |
597 | ||
598 | ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); | |
599 | s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static int __init s3c_cpufreq_initcall(void) | |
605 | { | |
606 | int ret = 0; | |
607 | ||
608 | if (cpu_cur.info && cpu_cur.board) { | |
609 | ret = s3c_cpufreq_initclks(); | |
610 | if (ret) | |
611 | goto out; | |
612 | ||
613 | /* get current settings */ | |
614 | s3c_cpufreq_getcur(&cpu_cur); | |
615 | s3c_cpufreq_show("cur", &cpu_cur); | |
616 | ||
617 | if (cpu_cur.board->auto_io) { | |
618 | ret = s3c_cpufreq_auto_io(); | |
619 | if (ret) { | |
620 | printk(KERN_ERR "%s: failed to get io timing\n", | |
621 | __func__); | |
622 | goto out; | |
623 | } | |
624 | } | |
625 | ||
626 | if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { | |
627 | printk(KERN_ERR "%s: no IO support registered\n", | |
628 | __func__); | |
629 | ret = -EINVAL; | |
630 | goto out; | |
631 | } | |
632 | ||
633 | if (!cpu_cur.info->need_pll) | |
634 | cpu_cur.lock_pll = 1; | |
635 | ||
636 | s3c_cpufreq_update_loctkime(); | |
637 | ||
638 | s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, | |
639 | &cpu_cur.info->max); | |
640 | ||
641 | if (cpu_cur.info->calc_freqtable) | |
642 | s3c_cpufreq_build_freq(); | |
643 | ||
644 | ret = cpufreq_register_driver(&s3c24xx_driver); | |
645 | } | |
646 | ||
647 | out: | |
648 | return ret; | |
649 | } | |
650 | ||
651 | late_initcall(s3c_cpufreq_initcall); | |
652 | ||
653 | /** | |
654 | * s3c_plltab_register - register CPU PLL table. | |
655 | * @plls: The list of PLL entries. | |
656 | * @plls_no: The size of the PLL entries @plls. | |
657 | * | |
658 | * Register the given set of PLLs with the system. | |
659 | */ | |
660 | int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, | |
661 | unsigned int plls_no) | |
662 | { | |
663 | struct cpufreq_frequency_table *vals; | |
664 | unsigned int size; | |
665 | ||
d5b73cd8 | 666 | size = sizeof(*vals) * (plls_no + 1); |
2e4ea6e8 | 667 | |
71508a1f | 668 | vals = kzalloc(size, GFP_KERNEL); |
2e4ea6e8 BD |
669 | if (vals) { |
670 | memcpy(vals, plls, size); | |
671 | pll_reg = vals; | |
672 | ||
673 | /* write a terminating entry, we don't store it in the | |
674 | * table that is stored in the kernel */ | |
675 | vals += plls_no; | |
676 | vals->frequency = CPUFREQ_TABLE_END; | |
677 | ||
678 | printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); | |
679 | } else | |
680 | printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); | |
681 | ||
682 | return vals ? 0 : -ENOMEM; | |
683 | } |