[linux-2.6-block.git] / drivers / cpufreq / qoriq-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpufreq.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

/**
 * struct cpu_data
 * @pclk: the parent clock of cpu
 * @table: frequency table
 */
struct cpu_data {
	struct clk **pclk;
	struct cpufreq_frequency_table *table;
};

/*
 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
 * matched a more generic compatible.
 */
#define SOC_BLACKLIST		1

/**
 * struct soc_data - SoC specific data
 * @flags: SOC_xxx
 */
struct soc_data {
	u32 flags;
};

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;
	struct clk *pltclk;
	int ret;

	/* get platform freq by searching bus-frequency property */
	soc = of_find_node_by_type(NULL, "soc");
	if (soc) {
		ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
		of_node_put(soc);
		if (!ret)
			return sysfreq;
	}

	/* get platform freq by its clock name */
	pltclk = clk_get(NULL, "cg-pll0-div1");
	if (IS_ERR(pltclk)) {
		pr_err("%s: can't get bus frequency %ld\n",
		       __func__, PTR_ERR(pltclk));
		return PTR_ERR(pltclk);
	}

	return clk_get_rate(pltclk);
}

static struct clk *cpu_to_clk(int cpu)
{
	struct device_node *np;
	struct clk *clk;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk = of_clk_get(np, 0);
	of_node_put(np);
	return clk;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct cpumask *dstp = policy->cpus;
	struct clk *clk;
	int i;

	for_each_present_cpu(i) {
		clk = cpu_to_clk(i);
		if (IS_ERR(clk)) {
			pr_err("%s: no clock for cpu %d\n", __func__, i);
			continue;
		}

		if (clk_is_match(policy->clk, clk))
			cpumask_set_cpu(i, dstp);
	}
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np;
	int i, count;
	u32 freq;
	struct clk *clk;
	const struct clk_hw *hwclk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	hwclk = __clk_get_hw(policy->clk);
	count = clk_hw_get_num_parents(hwclk);

	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	if (!data->pclk)
		goto err_nomem2;

	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table)
		goto err_pclk;

	for (i = 0; i < count; i++) {
		clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
		data->pclk[i] = clk;
		freq = clk_get_rate(clk);
		table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;
	policy->freq_table = table;
	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);

	return 0;

err_pclk:
	kfree(data->pclk);
err_nomem2:
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	kfree(data->pclk);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = data->pclk[data->table[index].driver_data];
	return clk_set_parent(policy->clk, parent);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS |
			  CPUFREQ_IS_COOLING_DEV,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= qoriq_cpufreq_cpu_exit,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.attr		= cpufreq_generic_attr,
};

static const struct soc_data blacklist = {
	.flags = SOC_BLACKLIST,
};

static const struct of_device_id node_matches[] __initconst = {
	/* e6500 cannot use cpufreq due to erratum A-008083 */
	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	{ .compatible = "fsl,t4240-clockgen", &blacklist },

	{ .compatible = "fsl,ls1012a-clockgen", },
	{ .compatible = "fsl,ls1021a-clockgen", },
	{ .compatible = "fsl,ls1028a-clockgen", },
	{ .compatible = "fsl,ls1043a-clockgen", },
	{ .compatible = "fsl,ls1046a-clockgen", },
	{ .compatible = "fsl,ls1088a-clockgen", },
	{ .compatible = "fsl,ls2080a-clockgen", },
	{ .compatible = "fsl,lx2160a-clockgen", },
	{ .compatible = "fsl,p4080-clockgen", },
	{ .compatible = "fsl,qoriq-clockgen-1.0", },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;

	of_node_put(np);

	if (data && data->flags & SOC_BLACKLIST)
		return -ENODEV;

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
defa4c73 TY	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
a4f20742	5	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	6	*/
	7
	8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	9
	10	#include <linux/clk.h>
b1e9a649	11	#include <linux/clk-provider.h>
defa4c73 TY	12	#include <linux/cpufreq.h>
defa4c73 TY	13	#include <linux/errno.h>
defa4c73 TY	14	#include <linux/init.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/of.h>
	19	#include <linux/slab.h>
	20	#include <linux/smp.h>
	21
	22	/**
a4f20742	23	* struct cpu_data
8a95c144	24	* @pclk: the parent clock of cpu
defa4c73 TY	25	* @table: frequency table
	26	*/
	27	struct cpu_data {
8a95c144	28	struct clk **pclk;
defa4c73 TY	29	struct cpufreq_frequency_table *table;
	30	};
	31
b1e9a649 TY	32	/*
	33	* Don't use cpufreq on this SoC -- used when the SoC would have otherwise
	34	* matched a more generic compatible.
	35	*/
	36	#define SOC_BLACKLIST 1
	37
defa4c73 TY	38	/**
defa4c73 TY	39	* struct soc_data - SoC specific data
b1e9a649	40	* @flags: SOC_xxx
defa4c73 TY	41	*/
defa4c73 TY	42	struct soc_data {
b1e9a649	43	u32 flags;
defa4c73 TY	44	};
defa4c73 TY	45
a4f20742 TY	46	static u32 get_bus_freq(void)
	47	{
	48	struct device_node *soc;
	49	u32 sysfreq;
b51d3388 YT	50	struct clk *pltclk;
b51d3388 YT	51	int ret;
a4f20742	52
b51d3388	53	/* get platform freq by searching bus-frequency property */
a4f20742	54	soc = of_find_node_by_type(NULL, "soc");
b51d3388 YT	55	if (soc) {
	56	ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
	57	of_node_put(soc);
	58	if (!ret)
	59	return sysfreq;
	60	}
a4f20742	61
b51d3388 YT	62	/* get platform freq by its clock name */
	63	pltclk = clk_get(NULL, "cg-pll0-div1");
	64	if (IS_ERR(pltclk)) {
	65	pr_err("%s: can't get bus frequency %ld\n",
	66	__func__, PTR_ERR(pltclk));
	67	return PTR_ERR(pltclk);
	68	}
defa4c73	69
b51d3388	70	return clk_get_rate(pltclk);
a4f20742	71	}
defa4c73	72
b1e9a649	73	static struct clk *cpu_to_clk(int cpu)
defa4c73	74	{
b1e9a649 TY	75	struct device_node *np;
b1e9a649 TY	76	struct clk *clk;
a4f20742 TY	77
	78	if (!cpu_present(cpu))
	79	return NULL;
	80
	81	np = of_get_cpu_node(cpu, NULL);
	82	if (!np)
	83	return NULL;
	84
b1e9a649	85	clk = of_clk_get(np, 0);
a4f20742	86	of_node_put(np);
b1e9a649	87	return clk;
a4f20742 TY	88	}
	89
	90	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	91	static void set_affected_cpus(struct cpufreq_policy *policy)
	92	{
a4f20742	93	struct cpumask *dstp = policy->cpus;
b1e9a649	94	struct clk *clk;
a4f20742 TY	95	int i;
a4f20742 TY	96
a4f20742	97	for_each_present_cpu(i) {
b1e9a649 TY	98	clk = cpu_to_clk(i);
	99	if (IS_ERR(clk)) {
	100	pr_err("%s: no clock for cpu %d\n", __func__, i);
a4f20742	101	continue;
b1e9a649	102	}
a4f20742	103
b1e9a649	104	if (clk_is_match(policy->clk, clk))
a4f20742	105	cpumask_set_cpu(i, dstp);
a4f20742	106	}
defa4c73	107	}
defa4c73	108
defa4c73 TY	109	/* reduce the duplicated frequencies in frequency table */
	110	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	111	int count)
	112	{
	113	int i, j;
	114
	115	for (i = 1; i < count; i++) {
	116	for (j = 0; j < i; j++) {
	117	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	118	freq_table[j].frequency !=
	119	freq_table[i].frequency)
	120	continue;
	121
	122	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	123	break;
	124	}
	125	}
	126	}
	127
	128	/* sort the frequencies in frequency table in descenting order */
	129	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	130	int count)
	131	{
	132	int i, j, ind;
	133	unsigned int freq, max_freq;
	134	struct cpufreq_frequency_table table;
a4f20742	135
defa4c73 TY	136	for (i = 0; i < count - 1; i++) {
	137	max_freq = freq_table[i].frequency;
	138	ind = i;
	139	for (j = i + 1; j < count; j++) {
	140	freq = freq_table[j].frequency;
	141	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	142	freq <= max_freq)
	143	continue;
	144	ind = j;
	145	max_freq = freq;
	146	}
	147
	148	if (ind != i) {
	149	/* exchange the frequencies */
	150	table.driver_data = freq_table[i].driver_data;
	151	table.frequency = freq_table[i].frequency;
	152	freq_table[i].driver_data = freq_table[ind].driver_data;
	153	freq_table[i].frequency = freq_table[ind].frequency;
	154	freq_table[ind].driver_data = table.driver_data;
	155	freq_table[ind].frequency = table.frequency;
	156	}
	157	}
	158	}
	159
a4f20742	160	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73	161	{
b1e9a649	162	struct device_node *np;
5ab508be	163	int i, count;
b1e9a649	164	u32 freq;
defa4c73	165	struct clk *clk;
b1e9a649	166	const struct clk_hw *hwclk;
defa4c73 TY	167	struct cpufreq_frequency_table *table;
	168	struct cpu_data *data;
	169	unsigned int cpu = policy->cpu;
906fe033	170	u64 u64temp;
defa4c73 TY	171
	172	np = of_get_cpu_node(cpu, NULL);
	173	if (!np)
	174	return -ENODEV;
	175
	176	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	177	if (!data)
defa4c73	178	goto err_np;
defa4c73	179
652ed95d VK	180	policy->clk = of_clk_get(np, 0);
652ed95d VK	181	if (IS_ERR(policy->clk)) {
defa4c73 TY	182	pr_err("%s: no clock information\n", __func__);
	183	goto err_nomem2;
	184	}
	185
b1e9a649 TY	186	hwclk = __clk_get_hw(policy->clk);
b1e9a649 TY	187	count = clk_hw_get_num_parents(hwclk);
defa4c73	188
8a95c144	189	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
d6b96e47	190	if (!data->pclk)
b1e9a649	191	goto err_nomem2;
8a95c144	192
defa4c73	193	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
d6b96e47	194	if (!table)
8a95c144	195	goto err_pclk;
defa4c73	196
defa4c73	197	for (i = 0; i < count; i++) {
b1e9a649	198	clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
8a95c144	199	data->pclk[i] = clk;
defa4c73	200	freq = clk_get_rate(clk);
b1e9a649	201	table[i].frequency = freq / 1000;
defa4c73 TY	202	table[i].driver_data = i;
	203	}
	204	freq_table_redup(table, count);
	205	freq_table_sort(table, count);
	206	table[i].frequency = CPUFREQ_TABLE_END;
5ab508be	207	policy->freq_table = table;
defa4c73	208	data->table = table;
defa4c73 TY	209
defa4c73 TY	210	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	211	set_affected_cpus(policy);
a4f20742 TY	212	policy->driver_data = data;
defa4c73	213
906fe033 ES	214	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	215	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	216	do_div(u64temp, get_bus_freq());
906fe033	217	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	218
defa4c73 TY	219	of_node_put(np);
	220
	221	return 0;
	222
8a95c144 TY	223	err_pclk:
8a95c144 TY	224	kfree(data->pclk);
defa4c73	225	err_nomem2:
defa4c73 TY	226	kfree(data);
	227	err_np:
	228	of_node_put(np);
	229
	230	return -ENODEV;
	231	}
	232
495c716f	233	static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	234	{
a4f20742	235	struct cpu_data *data = policy->driver_data;
defa4c73	236
8a95c144	237	kfree(data->pclk);
defa4c73 TY	238	kfree(data->table);
defa4c73 TY	239	kfree(data);
a4f20742	240	policy->driver_data = NULL;
defa4c73 TY	241
	242	return 0;
	243	}
	244
a4f20742	245	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	246	unsigned int index)
defa4c73	247	{
defa4c73	248	struct clk *parent;
a4f20742	249	struct cpu_data *data = policy->driver_data;
defa4c73	250
8a95c144	251	parent = data->pclk[data->table[index].driver_data];
652ed95d	252	return clk_set_parent(policy->clk, parent);
defa4c73 TY	253	}
defa4c73 TY	254
a4f20742 TY	255	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	256	.name = "qoriq_cpufreq",
17170ec1 AK	257	.flags = CPUFREQ_CONST_LOOPS \|
17170ec1 AK	258	CPUFREQ_IS_COOLING_DEV,
a4f20742	259	.init = qoriq_cpufreq_cpu_init,
495c716f	260	.exit = qoriq_cpufreq_cpu_exit,
dc2398d7	261	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	262	.target_index = qoriq_cpufreq_target,
652ed95d	263	.get = cpufreq_generic_get,
dc2398d7	264	.attr = cpufreq_generic_attr,
defa4c73 TY	265	};
defa4c73 TY	266
b1e9a649 TY	267	static const struct soc_data blacklist = {
	268	.flags = SOC_BLACKLIST,
	269	};
	270
a4f20742	271	static const struct of_device_id node_matches[] __initconst = {
b1e9a649 TY	272	/* e6500 cannot use cpufreq due to erratum A-008083 */
	273	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	274	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	275	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	276	{ .compatible = "fsl,t4240-clockgen", &blacklist },
	277
	278	{ .compatible = "fsl,ls1012a-clockgen", },
	279	{ .compatible = "fsl,ls1021a-clockgen", },
4235a594	280	{ .compatible = "fsl,ls1028a-clockgen", },
b1e9a649 TY	281	{ .compatible = "fsl,ls1043a-clockgen", },
	282	{ .compatible = "fsl,ls1046a-clockgen", },
	283	{ .compatible = "fsl,ls1088a-clockgen", },
	284	{ .compatible = "fsl,ls2080a-clockgen", },
712e9ad0	285	{ .compatible = "fsl,lx2160a-clockgen", },
b1e9a649 TY	286	{ .compatible = "fsl,p4080-clockgen", },
b1e9a649 TY	287	{ .compatible = "fsl,qoriq-clockgen-1.0", },
defa4c73 TY	288	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	289	{}
	290	};
	291
a4f20742	292	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	293	{
	294	int ret;
	295	struct device_node *np;
	296	const struct of_device_id *match;
	297	const struct soc_data *data;
defa4c73 TY	298
	299	np = of_find_matching_node(NULL, node_matches);
	300	if (!np)
	301	return -ENODEV;
	302
defa4c73 TY	303	match = of_match_node(node_matches, np);
defa4c73 TY	304	data = match->data;
defa4c73 TY	305
	306	of_node_put(np);
	307
b1e9a649 TY	308	if (data && data->flags & SOC_BLACKLIST)
	309	return -ENODEV;
	310
a4f20742	311	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	312	if (!ret)
a4f20742	313	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	314
defa4c73 TY	315	return ret;
defa4c73	316	}
a4f20742	317	module_init(qoriq_cpufreq_init);
defa4c73	318
a4f20742	319	static void __exit qoriq_cpufreq_exit(void)
defa4c73	320	{
a4f20742	321	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	322	}
a4f20742	323	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	324
	325	MODULE_LICENSE("GPL");
	326	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
a4f20742	327	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");