[linux-2.6-block.git] / drivers / cpufreq / pxa2xx-cpufreq.c

/*
 *  Copyright (C) 2002,2003 Intrinsyc Software
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * History:
 *   31-Jul-2002 : Initial version [FB]
 *   29-Jan-2003 : added PXA255 support [FB]
 *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
 *
 * Note:
 *   This driver may change the memory bus clock rate, but will not do any
 *   platform specific access timing changes... for example if you have flash
 *   memory connected to CS0, you will need to register a platform specific
 *   notifier which will adjust the memory access strobes to maintain a
 *   minimum strobe width.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/io.h>

#include <mach/pxa2xx-regs.h>
#include <mach/smemc.h>

#ifdef DEBUG
static unsigned int freq_debug;
module_param(freq_debug, uint, 0);
MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
#else
#define freq_debug  0
#endif

static struct regulator *vcc_core;

static unsigned int pxa27x_maxfreq;
module_param(pxa27x_maxfreq, uint, 0);
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");

typedef struct {
	unsigned int khz;
	unsigned int membus;
	unsigned int cccr;
	unsigned int div2;
	unsigned int cclkcfg;
	int vmin;
	int vmax;
} pxa_freqs_t;

/* Define the refresh period in mSec for the SDRAM and the number of rows */
#define SDRAM_TREF	64	/* standard 64ms SDRAM */
static unsigned int sdram_rows;

#define CCLKCFG_TURBO		0x1
#define CCLKCFG_FCS		0x2
#define CCLKCFG_HALFTURBO	0x4
#define CCLKCFG_FASTBUS		0x8
#define MDREFR_DB2_MASK		(MDREFR_K2DB2 | MDREFR_K1DB2)
#define MDREFR_DRI_MASK		0xFFF

#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)

/*
 * PXA255 definitions
 */
/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
#define CCLKCFG			CCLKCFG_TURBO | CCLKCFG_FCS

static pxa_freqs_t pxa255_run_freqs[] =
{
	/* CPU   MEMBUS  CCCR  DIV2 CCLKCFG	           run  turbo PXbus SDRAM */
	{ 99500,  99500, 0x121, 1,  CCLKCFG, -1, -1},	/*  99,   99,   50,   50  */
	{132700, 132700, 0x123, 1,  CCLKCFG, -1, -1},	/* 133,  133,   66,   66  */
	{199100,  99500, 0x141, 0,  CCLKCFG, -1, -1},	/* 199,  199,   99,   99  */
	{265400, 132700, 0x143, 1,  CCLKCFG, -1, -1},	/* 265,  265,  133,   66  */
	{331800, 165900, 0x145, 1,  CCLKCFG, -1, -1},	/* 331,  331,  166,   83  */
	{398100,  99500, 0x161, 0,  CCLKCFG, -1, -1},	/* 398,  398,  196,   99  */
};

/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static pxa_freqs_t pxa255_turbo_freqs[] =
{
	/* CPU   MEMBUS  CCCR  DIV2 CCLKCFG	   run  turbo PXbus SDRAM */
	{ 99500, 99500,  0x121, 1,  CCLKCFG, -1, -1},	/*  99,   99,   50,   50  */
	{199100, 99500,  0x221, 0,  CCLKCFG, -1, -1},	/*  99,  199,   50,   99  */
	{298500, 99500,  0x321, 0,  CCLKCFG, -1, -1},	/*  99,  287,   50,   99  */
	{298600, 99500,  0x1c1, 0,  CCLKCFG, -1, -1},	/* 199,  287,   99,   99  */
	{398100, 99500,  0x241, 0,  CCLKCFG, -1, -1},	/* 199,  398,   99,   99  */
};

#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)

static struct cpufreq_frequency_table
	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
static struct cpufreq_frequency_table
	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];

static unsigned int pxa255_turbo_table;
module_param(pxa255_turbo_table, uint, 0);
MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");

/*
 * PXA270 definitions
 *
 * For the PXA27x:
 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
 *
 * A = 0 => memory controller clock from table 3-7,
 * A = 1 => memory controller clock = system bus clock
 * Run mode frequency	= 13 MHz * L
 * Turbo mode frequency = 13 MHz * L * N
 * System bus frequency = 13 MHz * L / (B + 1)
 *
 * In CCCR:
 * A = 1
 * L = 16	  oscillator to run mode ratio
 * 2N = 6	  2 * (turbo mode to run mode ratio)
 *
 * In CCLKCFG:
 * B = 1	  Fast bus mode
 * HT = 0	  Half-Turbo mode
 * T = 1	  Turbo mode
 *
 * For now, just support some of the combinations in table 3-7 of
 * PXA27x Processor Family Developer's Manual to simplify frequency
 * change sequences.
 */
#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
#define CCLKCFG2(B, HT, T) \
  (CCLKCFG_FCS | \
   ((B)  ? CCLKCFG_FASTBUS : 0) | \
   ((HT) ? CCLKCFG_HALFTURBO : 0) | \
   ((T)  ? CCLKCFG_TURBO : 0))

static pxa_freqs_t pxa27x_freqs[] = {
	{104000, 104000, PXA27x_CCCR(1,	 8, 2), 0, CCLKCFG2(1, 0, 1),  900000, 1705000 },
	{156000, 104000, PXA27x_CCCR(1,	 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
	{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
	{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
	{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
	{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
	{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
};

#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
static struct cpufreq_frequency_table
	pxa27x_freq_table[NUM_PXA27x_FREQS+1];

extern unsigned get_clk_frequency_khz(int info);

#ifdef CONFIG_REGULATOR

static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
{
	int ret = 0;
	int vmin, vmax;

	if (!cpu_is_pxa27x())
		return 0;

	vmin = pxa_freq->vmin;
	vmax = pxa_freq->vmax;
	if ((vmin == -1) || (vmax == -1))
		return 0;

	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	if (ret)
		pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
		       vmin, vmax);
	return ret;
}

static void __init pxa_cpufreq_init_voltages(void)
{
	vcc_core = regulator_get(NULL, "vcc_core");
	if (IS_ERR(vcc_core)) {
		pr_info("cpufreq: Didn't find vcc_core regulator\n");
		vcc_core = NULL;
	} else {
		pr_info("cpufreq: Found vcc_core regulator\n");
	}
}
#else
static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
{
	return 0;
}

static void __init pxa_cpufreq_init_voltages(void) { }
#endif

static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
			     pxa_freqs_t **pxa_freqs)
{
	if (cpu_is_pxa25x()) {
		if (!pxa255_turbo_table) {
			*pxa_freqs = pxa255_run_freqs;
			*freq_table = pxa255_run_freq_table;
		} else {
			*pxa_freqs = pxa255_turbo_freqs;
			*freq_table = pxa255_turbo_freq_table;
		}
	} else if (cpu_is_pxa27x()) {
		*pxa_freqs = pxa27x_freqs;
		*freq_table = pxa27x_freq_table;
	} else {
		BUG();
	}
}

static void pxa27x_guess_max_freq(void)
{
	if (!pxa27x_maxfreq) {
		pxa27x_maxfreq = 416000;
		printk(KERN_INFO "PXA CPU 27x max frequency not defined "
		       "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
		       pxa27x_maxfreq);
	} else {
		pxa27x_maxfreq *= 1000;
	}
}

static void init_sdram_rows(void)
{
	uint32_t mdcnfg = __raw_readl(MDCNFG);
	unsigned int drac2 = 0, drac0 = 0;

	if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
		drac2 = MDCNFG_DRAC2(mdcnfg);

	if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
		drac0 = MDCNFG_DRAC0(mdcnfg);

	sdram_rows = 1 << (11 + max(drac0, drac2));
}

static u32 mdrefr_dri(unsigned int freq)
{
	u32 interval = freq * SDRAM_TREF / sdram_rows;

	return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
}

static unsigned int pxa_cpufreq_get(unsigned int cpu)
{
	return get_clk_frequency_khz(0);
}

static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
{
	struct cpufreq_frequency_table *pxa_freqs_table;
	pxa_freqs_t *pxa_freq_settings;
	struct cpufreq_freqs freqs;
	unsigned long flags;
	unsigned int new_freq_cpu, new_freq_mem;
	unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
	int ret = 0;

	/* Get the current policy */
	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);

	new_freq_cpu = pxa_freq_settings[idx].khz;
	new_freq_mem = pxa_freq_settings[idx].membus;
	freqs.old = policy->cur;
	freqs.new = new_freq_cpu;

	if (freq_debug)
		pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
			 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
			 (new_freq_mem / 2000) : (new_freq_mem / 1000));

	if (vcc_core && freqs.new > freqs.old)
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
	if (ret)
		return ret;
	/*
	 * Tell everyone what we're about to do...
	 * you should add a notify client with any platform specific
	 * Vcc changing capability
	 */
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	/* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
	 * we need to preset the smaller DRI before the change.	 If we're
	 * speeding up we need to set the larger DRI value after the change.
	 */
	preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
	if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
		preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
		preset_mdrefr |= mdrefr_dri(new_freq_mem);
	}
	postset_mdrefr =
		(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);

	/* If we're dividing the memory clock by two for the SDRAM clock, this
	 * must be set prior to the change.  Clearing the divide must be done
	 * after the change.
	 */
	if (pxa_freq_settings[idx].div2) {
		preset_mdrefr  |= MDREFR_DB2_MASK;
		postset_mdrefr |= MDREFR_DB2_MASK;
	} else {
		postset_mdrefr &= ~MDREFR_DB2_MASK;
	}

	local_irq_save(flags);

	/* Set new the CCCR and prepare CCLKCFG */
	CCCR = pxa_freq_settings[idx].cccr;
	cclkcfg = pxa_freq_settings[idx].cclkcfg;

	asm volatile("							\n\
		ldr	r4, [%1]		/* load MDREFR */	\n\
		b	2f						\n\
		.align	5						\n\
1:									\n\
		str	%3, [%1]		/* preset the MDREFR */	\n\
		mcr	p14, 0, %2, c6, c0, 0	/* set CCLKCFG[FCS] */	\n\
		str	%4, [%1]		/* postset the MDREFR */ \n\
									\n\
		b	3f						\n\
2:		b	1b						\n\
3:		nop							\n\
	  "
		     : "=&r" (unused)
		     : "r" (MDREFR), "r" (cclkcfg),
		       "r" (preset_mdrefr), "r" (postset_mdrefr)
		     : "r4", "r5");
	local_irq_restore(flags);

	/*
	 * Tell everyone what we've just done...
	 * you should add a notify client with any platform specific
	 * SDRAM refresh timer adjustments
	 */
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	/*
	 * Even if voltage setting fails, we don't report it, as the frequency
	 * change succeeded. The voltage reduction is not a critical failure,
	 * only power savings will suffer from this.
	 *
	 * Note: if the voltage change fails, and a return value is returned, a
	 * bug is triggered (seems a deadlock). Should anybody find out where,
	 * the "return 0" should become a "return ret".
	 */
	if (vcc_core && freqs.new < freqs.old)
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);

	return 0;
}

static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
	int i;
	unsigned int freq;
	struct cpufreq_frequency_table *pxa255_freq_table;
	pxa_freqs_t *pxa255_freqs;

	/* try to guess pxa27x cpu */
	if (cpu_is_pxa27x())
		pxa27x_guess_max_freq();

	pxa_cpufreq_init_voltages();

	init_sdram_rows();

	/* set default policy and cpuinfo */
	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */

	/* Generate pxa25x the run cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
		pxa255_run_freq_table[i].driver_data = i;
	}
	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
		pxa255_turbo_freq_table[i].frequency =
			pxa255_turbo_freqs[i].khz;
		pxa255_turbo_freq_table[i].driver_data = i;
	}
	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;

	pxa255_turbo_table = !!pxa255_turbo_table;

	/* Generate the pxa27x cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
		freq = pxa27x_freqs[i].khz;
		if (freq > pxa27x_maxfreq)
			break;
		pxa27x_freq_table[i].frequency = freq;
		pxa27x_freq_table[i].driver_data = i;
	}
	pxa27x_freq_table[i].driver_data = i;
	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/*
	 * Set the policy's minimum and maximum frequencies from the tables
	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
	 */
	if (cpu_is_pxa25x()) {
		find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
		pr_info("PXA255 cpufreq using %s frequency table\n",
			pxa255_turbo_table ? "turbo" : "run");

		cpufreq_table_validate_and_show(policy, pxa255_freq_table);
	}
	else if (cpu_is_pxa27x()) {
		cpufreq_table_validate_and_show(policy, pxa27x_freq_table);
	}

	printk(KERN_INFO "PXA CPU frequency change support initialized\n");

	return 0;
}

static struct cpufreq_driver pxa_cpufreq_driver = {
	.verify	= cpufreq_generic_frequency_table_verify,
	.target_index = pxa_set_target,
	.init	= pxa_cpufreq_init,
	.exit	= cpufreq_generic_exit,
	.get	= pxa_cpufreq_get,
	.name	= "PXA2xx",
};

static int __init pxa_cpu_init(void)
{
	int ret = -ENODEV;
	if (cpu_is_pxa25x() || cpu_is_pxa27x())
		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	return ret;
}

static void __exit pxa_cpu_exit(void)
{
	cpufreq_unregister_driver(&pxa_cpufreq_driver);
}


MODULE_AUTHOR("Intrinsyc Software Inc.");
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
MODULE_LICENSE("GPL");
module_init(pxa_cpu_init);
module_exit(pxa_cpu_exit);
Commit	Line	Data
9e2697ff	1	/*
9e2697ff RK	2	* Copyright (C) 2002,2003 Intrinsyc Software
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	* History:
	19	* 31-Jul-2002 : Initial version [FB]
	20	* 29-Jan-2003 : added PXA255 support [FB]
	21	* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
	22	*
	23	* Note:
	24	* This driver may change the memory bus clock rate, but will not do any
	25	* platform specific access timing changes... for example if you have flash
	26	* memory connected to CS0, you will need to register a platform specific
	27	* notifier which will adjust the memory access strobes to maintain a
	28	* minimum strobe width.
	29	*
	30	*/
	31
	32	#include <linux/kernel.h>
	33	#include <linux/module.h>
	34	#include <linux/sched.h>
	35	#include <linux/init.h>
	36	#include <linux/cpufreq.h>
3dbeef23 RJ	37	#include <linux/err.h>
3dbeef23 RJ	38	#include <linux/regulator/consumer.h>
ad68bb9f	39	#include <linux/io.h>
9e2697ff	40
a09e64fb	41	#include <mach/pxa2xx-regs.h>
ad68bb9f	42	#include <mach/smemc.h>
9e2697ff RK	43
	44	#ifdef DEBUG
	45	static unsigned int freq_debug;
c710e39c	46	module_param(freq_debug, uint, 0);
9e2697ff RK	47	MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
	48	#else
	49	#define freq_debug 0
	50	#endif
	51
3dbeef23 RJ	52	static struct regulator *vcc_core;
3dbeef23 RJ	53
592eb999 RJ	54	static unsigned int pxa27x_maxfreq;
	55	module_param(pxa27x_maxfreq, uint, 0);
	56	MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
	57	"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
	58
9e2697ff RK	59	typedef struct {
	60	unsigned int khz;
	61	unsigned int membus;
	62	unsigned int cccr;
	63	unsigned int div2;
592eb999	64	unsigned int cclkcfg;
3dbeef23 RJ	65	int vmin;
3dbeef23 RJ	66	int vmax;
9e2697ff RK	67	} pxa_freqs_t;
	68
	69	/* Define the refresh period in mSec for the SDRAM and the number of rows */
3679389b	70	#define SDRAM_TREF 64 /* standard 64ms SDRAM */
a10c287d	71	static unsigned int sdram_rows;
9e2697ff	72
3679389b RJ	73	#define CCLKCFG_TURBO 0x1
3679389b RJ	74	#define CCLKCFG_FCS 0x2
592eb999 RJ	75	#define CCLKCFG_HALFTURBO 0x4
592eb999 RJ	76	#define CCLKCFG_FASTBUS 0x8
3679389b RJ	77	#define MDREFR_DB2_MASK (MDREFR_K2DB2 \| MDREFR_K1DB2)
3679389b RJ	78	#define MDREFR_DRI_MASK 0xFFF
9e2697ff	79
a10c287d PZ	80	#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
	81	#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
	82
592eb999 RJ	83	/*
	84	* PXA255 definitions
	85	*/
9e2697ff	86	/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
592eb999 RJ	87	#define CCLKCFG CCLKCFG_TURBO \| CCLKCFG_FCS
592eb999 RJ	88
9e2697ff RK	89	static pxa_freqs_t pxa255_run_freqs[] =
9e2697ff RK	90	{
3dbeef23 RJ	91	/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
	92	{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
	93	{132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
	94	{199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
	95	{265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
	96	{331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
	97	{398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
9e2697ff	98	};
9e2697ff RK	99
	100	/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
	101	static pxa_freqs_t pxa255_turbo_freqs[] =
	102	{
592eb999	103	/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
3dbeef23 RJ	104	{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
	105	{199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
	106	{298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
	107	{298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
	108	{398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
9e2697ff	109	};
9e2697ff	110
592eb999 RJ	111	#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
	112	#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
	113
	114	static struct cpufreq_frequency_table
	115	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
3679389b	116	static struct cpufreq_frequency_table
592eb999 RJ	117	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
592eb999 RJ	118
65587f7d MZ	119	static unsigned int pxa255_turbo_table;
	120	module_param(pxa255_turbo_table, uint, 0);
	121	MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
	122
592eb999 RJ	123	/*
	124	* PXA270 definitions
	125	*
	126	* For the PXA27x:
	127	* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
	128	*
	129	* A = 0 => memory controller clock from table 3-7,
	130	* A = 1 => memory controller clock = system bus clock
	131	* Run mode frequency = 13 MHz * L
	132	* Turbo mode frequency = 13 MHz * L * N
	133	* System bus frequency = 13 MHz * L / (B + 1)
	134	*
	135	* In CCCR:
	136	* A = 1
	137	* L = 16 oscillator to run mode ratio
	138	* 2N = 6 2 * (turbo mode to run mode ratio)
	139	*
	140	* In CCLKCFG:
	141	* B = 1 Fast bus mode
	142	* HT = 0 Half-Turbo mode
	143	* T = 1 Turbo mode
	144	*
	145	* For now, just support some of the combinations in table 3-7 of
	146	* PXA27x Processor Family Developer's Manual to simplify frequency
	147	* change sequences.
	148	*/
	149	#define PXA27x_CCCR(A, L, N2) (A << 25 \| N2 << 7 \| L)
	150	#define CCLKCFG2(B, HT, T) \
	151	(CCLKCFG_FCS \| \
	152	((B) ? CCLKCFG_FASTBUS : 0) \| \
	153	((HT) ? CCLKCFG_HALFTURBO : 0) \| \
	154	((T) ? CCLKCFG_TURBO : 0))
	155
	156	static pxa_freqs_t pxa27x_freqs[] = {
3dbeef23	157	{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
4367216a	158	{156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
3dbeef23 RJ	159	{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
	160	{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
	161	{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
	162	{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
	163	{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
592eb999 RJ	164	};
	165
	166	#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
	167	static struct cpufreq_frequency_table
	168	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
9e2697ff RK	169
	170	extern unsigned get_clk_frequency_khz(int info);
	171
3dbeef23 RJ	172	#ifdef CONFIG_REGULATOR
	173
	174	static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
	175	{
	176	int ret = 0;
	177	int vmin, vmax;
	178
	179	if (!cpu_is_pxa27x())
	180	return 0;
	181
	182	vmin = pxa_freq->vmin;
	183	vmax = pxa_freq->vmax;
	184	if ((vmin == -1) \|\| (vmax == -1))
	185	return 0;
	186
	187	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	188	if (ret)
	189	pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
	190	vmin, vmax);
	191	return ret;
	192	}
	193
295dbde1	194	static void __init pxa_cpufreq_init_voltages(void)
3dbeef23 RJ	195	{
	196	vcc_core = regulator_get(NULL, "vcc_core");
	197	if (IS_ERR(vcc_core)) {
	198	pr_info("cpufreq: Didn't find vcc_core regulator\n");
	199	vcc_core = NULL;
	200	} else {
	201	pr_info("cpufreq: Found vcc_core regulator\n");
	202	}
	203	}
	204	#else
	205	static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
	206	{
	207	return 0;
	208	}
	209
295dbde1	210	static void __init pxa_cpufreq_init_voltages(void) { }
3dbeef23 RJ	211	#endif
3dbeef23 RJ	212
65587f7d	213	static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
592eb999 RJ	214	pxa_freqs_t **pxa_freqs)
	215	{
	216	if (cpu_is_pxa25x()) {
65587f7d	217	if (!pxa255_turbo_table) {
592eb999 RJ	218	*pxa_freqs = pxa255_run_freqs;
592eb999 RJ	219	*freq_table = pxa255_run_freq_table;
65587f7d	220	} else {
592eb999 RJ	221	*pxa_freqs = pxa255_turbo_freqs;
592eb999 RJ	222	*freq_table = pxa255_turbo_freq_table;
592eb999	223	}
7264a2bb	224	} else if (cpu_is_pxa27x()) {
592eb999 RJ	225	*pxa_freqs = pxa27x_freqs;
592eb999 RJ	226	*freq_table = pxa27x_freq_table;
7264a2bb AB	227	} else {
7264a2bb AB	228	BUG();
592eb999 RJ	229	}
	230	}
	231
	232	static void pxa27x_guess_max_freq(void)
	233	{
	234	if (!pxa27x_maxfreq) {
	235	pxa27x_maxfreq = 416000;
	236	printk(KERN_INFO "PXA CPU 27x max frequency not defined "
	237	"(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
	238	pxa27x_maxfreq);
	239	} else {
	240	pxa27x_maxfreq *= 1000;
	241	}
	242	}
	243
a10c287d PZ	244	static void init_sdram_rows(void)
a10c287d PZ	245	{
ad68bb9f	246	uint32_t mdcnfg = __raw_readl(MDCNFG);
a10c287d PZ	247	unsigned int drac2 = 0, drac0 = 0;
	248
	249	if (mdcnfg & (MDCNFG_DE2 \| MDCNFG_DE3))
	250	drac2 = MDCNFG_DRAC2(mdcnfg);
	251
	252	if (mdcnfg & (MDCNFG_DE0 \| MDCNFG_DE1))
	253	drac0 = MDCNFG_DRAC0(mdcnfg);
	254
	255	sdram_rows = 1 << (11 + max(drac0, drac2));
	256	}
	257
592eb999 RJ	258	static u32 mdrefr_dri(unsigned int freq)
592eb999 RJ	259	{
3d3d0fbf	260	u32 interval = freq * SDRAM_TREF / sdram_rows;
592eb999	261
3d3d0fbf	262	return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
592eb999 RJ	263	}
592eb999 RJ	264
592eb999 RJ	265	static unsigned int pxa_cpufreq_get(unsigned int cpu)
	266	{
	267	return get_clk_frequency_khz(0);
	268	}
	269
9c0ebcf7	270	static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
9e2697ff RK	271	{
	272	struct cpufreq_frequency_table *pxa_freqs_table;
	273	pxa_freqs_t *pxa_freq_settings;
	274	struct cpufreq_freqs freqs;
9e2697ff	275	unsigned long flags;
592eb999 RJ	276	unsigned int new_freq_cpu, new_freq_mem;
592eb999 RJ	277	unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
3dbeef23	278	int ret = 0;
9e2697ff RK	279
9e2697ff RK	280	/* Get the current policy */
65587f7d	281	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
9e2697ff	282
592eb999 RJ	283	new_freq_cpu = pxa_freq_settings[idx].khz;
592eb999 RJ	284	new_freq_mem = pxa_freq_settings[idx].membus;
9e2697ff	285	freqs.old = policy->cur;
592eb999	286	freqs.new = new_freq_cpu;
9e2697ff RK	287
9e2697ff RK	288	if (freq_debug)
d4202806	289	pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
3679389b	290	freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
592eb999	291	(new_freq_mem / 2000) : (new_freq_mem / 1000));
9e2697ff	292
3dbeef23 RJ	293	if (vcc_core && freqs.new > freqs.old)
	294	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
	295	if (ret)
	296	return ret;
9e2697ff RK	297	/*
	298	* Tell everyone what we're about to do...
	299	* you should add a notify client with any platform specific
	300	* Vcc changing capability
	301	*/
b43a7ffb	302	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
9e2697ff RK	303
9e2697ff RK	304	/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
3679389b RJ	305	* we need to preset the smaller DRI before the change. If we're
3679389b RJ	306	* speeding up we need to set the larger DRI value after the change.
9e2697ff	307	*/
ad68bb9f MV	308	preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
ad68bb9f MV	309	if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
592eb999 RJ	310	preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
592eb999 RJ	311	preset_mdrefr \|= mdrefr_dri(new_freq_mem);
9e2697ff	312	}
592eb999 RJ	313	postset_mdrefr =
592eb999 RJ	314	(postset_mdrefr & ~MDREFR_DRI_MASK) \| mdrefr_dri(new_freq_mem);
9e2697ff RK	315
	316	/* If we're dividing the memory clock by two for the SDRAM clock, this
	317	* must be set prior to the change. Clearing the divide must be done
	318	* after the change.
	319	*/
	320	if (pxa_freq_settings[idx].div2) {
	321	preset_mdrefr \|= MDREFR_DB2_MASK;
	322	postset_mdrefr \|= MDREFR_DB2_MASK;
	323	} else {
	324	postset_mdrefr &= ~MDREFR_DB2_MASK;
	325	}
	326
	327	local_irq_save(flags);
	328
592eb999	329	/* Set new the CCCR and prepare CCLKCFG */
9e2697ff	330	CCCR = pxa_freq_settings[idx].cccr;
592eb999	331	cclkcfg = pxa_freq_settings[idx].cclkcfg;
9e2697ff RK	332
	333	asm volatile(" \n\
	334	ldr r4, [%1] /* load MDREFR */ \n\
	335	b 2f \n\
3679389b	336	.align 5 \n\
9e2697ff	337	1: \n\
592eb999	338	str %3, [%1] /* preset the MDREFR */ \n\
9e2697ff	339	mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
592eb999	340	str %4, [%1] /* postset the MDREFR */ \n\
9e2697ff RK	341	\n\
	342	b 3f \n\
	343	2: b 1b \n\
	344	3: nop \n\
	345	"
3679389b	346	: "=&r" (unused)
ad68bb9f	347	: "r" (MDREFR), "r" (cclkcfg),
592eb999	348	"r" (preset_mdrefr), "r" (postset_mdrefr)
3679389b	349	: "r4", "r5");
9e2697ff RK	350	local_irq_restore(flags);
	351
	352	/*
	353	* Tell everyone what we've just done...
	354	* you should add a notify client with any platform specific
	355	* SDRAM refresh timer adjustments
	356	*/
b43a7ffb	357	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
9e2697ff	358
3dbeef23 RJ	359	/*
	360	* Even if voltage setting fails, we don't report it, as the frequency
	361	* change succeeded. The voltage reduction is not a critical failure,
	362	* only power savings will suffer from this.
	363	*
	364	* Note: if the voltage change fails, and a return value is returned, a
	365	* bug is triggered (seems a deadlock). Should anybody find out where,
	366	* the "return 0" should become a "return ret".
	367	*/
	368	if (vcc_core && freqs.new < freqs.old)
	369	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
	370
9e2697ff RK	371	return 0;
	372	}
	373
50e77fcd	374	static int pxa_cpufreq_init(struct cpufreq_policy *policy)
9e2697ff RK	375	{
9e2697ff RK	376	int i;
592eb999	377	unsigned int freq;
65587f7d MZ	378	struct cpufreq_frequency_table *pxa255_freq_table;
65587f7d MZ	379	pxa_freqs_t *pxa255_freqs;
592eb999 RJ	380
	381	/* try to guess pxa27x cpu */
	382	if (cpu_is_pxa27x())
	383	pxa27x_guess_max_freq();
9e2697ff	384
3dbeef23 RJ	385	pxa_cpufreq_init_voltages();
3dbeef23 RJ	386
a10c287d PZ	387	init_sdram_rows();
a10c287d PZ	388
9e2697ff	389	/* set default policy and cpuinfo */
9e2697ff	390	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
9e2697ff	391
592eb999 RJ	392	/* Generate pxa25x the run cpufreq_frequency_table struct */
592eb999 RJ	393	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
9e2697ff	394	pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
50701588	395	pxa255_run_freq_table[i].driver_data = i;
9e2697ff	396	}
9e2697ff	397	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
592eb999 RJ	398
	399	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	400	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
3679389b RJ	401	pxa255_turbo_freq_table[i].frequency =
3679389b RJ	402	pxa255_turbo_freqs[i].khz;
50701588	403	pxa255_turbo_freq_table[i].driver_data = i;
9e2697ff RK	404	}
	405	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
	406
65587f7d MZ	407	pxa255_turbo_table = !!pxa255_turbo_table;
65587f7d MZ	408
592eb999 RJ	409	/* Generate the pxa27x cpufreq_frequency_table struct */
	410	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
	411	freq = pxa27x_freqs[i].khz;
	412	if (freq > pxa27x_maxfreq)
	413	break;
	414	pxa27x_freq_table[i].frequency = freq;
50701588	415	pxa27x_freq_table[i].driver_data = i;
592eb999	416	}
50701588	417	pxa27x_freq_table[i].driver_data = i;
592eb999 RJ	418	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
	419
	420	/*
	421	* Set the policy's minimum and maximum frequencies from the tables
	422	* just constructed. This sets cpuinfo.mxx_freq, min and max.
	423	*/
65587f7d MZ	424	if (cpu_is_pxa25x()) {
	425	find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
	426	pr_info("PXA255 cpufreq using %s frequency table\n",
	427	pxa255_turbo_table ? "turbo" : "run");
6a77a1e6	428
15cc921b	429	cpufreq_table_validate_and_show(policy, pxa255_freq_table);
65587f7d	430	}
6a77a1e6	431	else if (cpu_is_pxa27x()) {
15cc921b	432	cpufreq_table_validate_and_show(policy, pxa27x_freq_table);
6a77a1e6	433	}
592eb999	434
9e2697ff RK	435	printk(KERN_INFO "PXA CPU frequency change support initialized\n");
	436
	437	return 0;
	438	}
	439
	440	static struct cpufreq_driver pxa_cpufreq_driver = {
bf36e48d	441	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	442	.target_index = pxa_set_target,
9e2697ff	443	.init = pxa_cpufreq_init,
bf36e48d	444	.exit = cpufreq_generic_exit,
ea833f0b	445	.get = pxa_cpufreq_get,
592eb999	446	.name = "PXA2xx",
9e2697ff RK	447	};
	448
	449	static int __init pxa_cpu_init(void)
	450	{
	451	int ret = -ENODEV;
592eb999	452	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x())
9e2697ff RK	453	ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	454	return ret;
	455	}
	456
	457	static void __exit pxa_cpu_exit(void)
	458	{
592eb999	459	cpufreq_unregister_driver(&pxa_cpufreq_driver);
9e2697ff RK	460	}
	461
	462
3679389b RJ	463	MODULE_AUTHOR("Intrinsyc Software Inc.");
3679389b RJ	464	MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
9e2697ff RK	465	MODULE_LICENSE("GPL");
	466	module_init(pxa_cpu_init);
	467	module_exit(pxa_cpu_exit);