[linux-2.6-block.git] / drivers / cpufreq / pxa2xx-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2002,2003 Intrinsyc Software
 *
 * History:
 *   31-Jul-2002 : Initial version [FB]
 *   29-Jan-2003 : added PXA255 support [FB]
 *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
 *
 * Note:
 *   This driver may change the memory bus clock rate, but will not do any
 *   platform specific access timing changes... for example if you have flash
 *   memory connected to CS0, you will need to register a platform specific
 *   notifier which will adjust the memory access strobes to maintain a
 *   minimum strobe width.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/io.h>

#include <mach/pxa2xx-regs.h>
#include <mach/smemc.h>

#ifdef DEBUG
static unsigned int freq_debug;
module_param(freq_debug, uint, 0);
MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
#else
#define freq_debug  0
#endif

static struct regulator *vcc_core;

static unsigned int pxa27x_maxfreq;
module_param(pxa27x_maxfreq, uint, 0);
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");

struct pxa_cpufreq_data {
	struct clk *clk_core;
};
static struct pxa_cpufreq_data  pxa_cpufreq_data;

struct pxa_freqs {
	unsigned int khz;
	int vmin;
	int vmax;
};

/*
 * PXA255 definitions
 */
static const struct pxa_freqs pxa255_run_freqs[] =
{
	/* CPU   MEMBUS		   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{132700, -1, -1},	/* 133,  133,   66,   66  */
	{199100, -1, -1},	/* 199,  199,   99,   99  */
	{265400, -1, -1},	/* 265,  265,  133,   66  */
	{331800, -1, -1},	/* 331,  331,  166,   83  */
	{398100, -1, -1},	/* 398,  398,  196,   99  */
};

/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static const struct pxa_freqs pxa255_turbo_freqs[] =
{
	/* CPU			   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{199100, -1, -1},	/*  99,  199,   50,   99  */
	{298500, -1, -1},	/*  99,  287,   50,   99  */
	{298600, -1, -1},	/* 199,  287,   99,   99  */
	{398100, -1, -1},	/* 199,  398,   99,   99  */
};

#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)

static struct cpufreq_frequency_table
	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
static struct cpufreq_frequency_table
	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];

static unsigned int pxa255_turbo_table;
module_param(pxa255_turbo_table, uint, 0);
MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");

static struct pxa_freqs pxa27x_freqs[] = {
	{104000,  900000, 1705000 },
	{156000, 1000000, 1705000 },
	{208000, 1180000, 1705000 },
	{312000, 1250000, 1705000 },
	{416000, 1350000, 1705000 },
	{520000, 1450000, 1705000 },
	{624000, 1550000, 1705000 }
};

#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
static struct cpufreq_frequency_table
	pxa27x_freq_table[NUM_PXA27x_FREQS+1];

extern unsigned get_clk_frequency_khz(int info);

#ifdef CONFIG_REGULATOR

static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	int ret = 0;
	int vmin, vmax;

	if (!cpu_is_pxa27x())
		return 0;

	vmin = pxa_freq->vmin;
	vmax = pxa_freq->vmax;
	if ((vmin == -1) || (vmax == -1))
		return 0;

	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	if (ret)
		pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
	return ret;
}

static void pxa_cpufreq_init_voltages(void)
{
	vcc_core = regulator_get(NULL, "vcc_core");
	if (IS_ERR(vcc_core)) {
		pr_info("Didn't find vcc_core regulator\n");
		vcc_core = NULL;
	} else {
		pr_info("Found vcc_core regulator\n");
	}
}
#else
static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	return 0;
}

static void pxa_cpufreq_init_voltages(void) { }
#endif

static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
			     const struct pxa_freqs **pxa_freqs)
{
	if (cpu_is_pxa25x()) {
		if (!pxa255_turbo_table) {
			*pxa_freqs = pxa255_run_freqs;
			*freq_table = pxa255_run_freq_table;
		} else {
			*pxa_freqs = pxa255_turbo_freqs;
			*freq_table = pxa255_turbo_freq_table;
		}
	} else if (cpu_is_pxa27x()) {
		*pxa_freqs = pxa27x_freqs;
		*freq_table = pxa27x_freq_table;
	} else {
		BUG();
	}
}

static void pxa27x_guess_max_freq(void)
{
	if (!pxa27x_maxfreq) {
		pxa27x_maxfreq = 416000;
		pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
			pxa27x_maxfreq);
	} else {
		pxa27x_maxfreq *= 1000;
	}
}

static unsigned int pxa_cpufreq_get(unsigned int cpu)
{
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();

	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
}

static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
{
	struct cpufreq_frequency_table *pxa_freqs_table;
	const struct pxa_freqs *pxa_freq_settings;
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	unsigned int new_freq_cpu;
	int ret = 0;

	/* Get the current policy */
	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);

	new_freq_cpu = pxa_freq_settings[idx].khz;

	if (freq_debug)
		pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
			 policy->cur / 1000,  new_freq_cpu / 1000);

	if (vcc_core && new_freq_cpu > policy->cur) {
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
		if (ret)
			return ret;
	}

	clk_set_rate(data->clk_core, new_freq_cpu * 1000);

	/*
	 * Even if voltage setting fails, we don't report it, as the frequency
	 * change succeeded. The voltage reduction is not a critical failure,
	 * only power savings will suffer from this.
	 *
	 * Note: if the voltage change fails, and a return value is returned, a
	 * bug is triggered (seems a deadlock). Should anybody find out where,
	 * the "return 0" should become a "return ret".
	 */
	if (vcc_core && new_freq_cpu < policy->cur)
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);

	return 0;
}

static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
	int i;
	unsigned int freq;
	struct cpufreq_frequency_table *pxa255_freq_table;
	const struct pxa_freqs *pxa255_freqs;

	/* try to guess pxa27x cpu */
	if (cpu_is_pxa27x())
		pxa27x_guess_max_freq();

	pxa_cpufreq_init_voltages();

	/* set default policy and cpuinfo */
	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */

	/* Generate pxa25x the run cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
		pxa255_run_freq_table[i].driver_data = i;
	}
	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
		pxa255_turbo_freq_table[i].frequency =
			pxa255_turbo_freqs[i].khz;
		pxa255_turbo_freq_table[i].driver_data = i;
	}
	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;

	pxa255_turbo_table = !!pxa255_turbo_table;

	/* Generate the pxa27x cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
		freq = pxa27x_freqs[i].khz;
		if (freq > pxa27x_maxfreq)
			break;
		pxa27x_freq_table[i].frequency = freq;
		pxa27x_freq_table[i].driver_data = i;
	}
	pxa27x_freq_table[i].driver_data = i;
	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/*
	 * Set the policy's minimum and maximum frequencies from the tables
	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
	 */
	if (cpu_is_pxa25x()) {
		find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
		pr_info("using %s frequency table\n",
			pxa255_turbo_table ? "turbo" : "run");

		policy->freq_table = pxa255_freq_table;
	}
	else if (cpu_is_pxa27x()) {
		policy->freq_table = pxa27x_freq_table;
	}

	pr_info("frequency change support initialized\n");

	return 0;
}

static struct cpufreq_driver pxa_cpufreq_driver = {
	.flags	= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify	= cpufreq_generic_frequency_table_verify,
	.target_index = pxa_set_target,
	.init	= pxa_cpufreq_init,
	.get	= pxa_cpufreq_get,
	.name	= "PXA2xx",
	.driver_data = &pxa_cpufreq_data,
};

static int __init pxa_cpu_init(void)
{
	int ret = -ENODEV;

	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	if (IS_ERR(pxa_cpufreq_data.clk_core))
		return PTR_ERR(pxa_cpufreq_data.clk_core);

	if (cpu_is_pxa25x() || cpu_is_pxa27x())
		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	return ret;
}

static void __exit pxa_cpu_exit(void)
{
	cpufreq_unregister_driver(&pxa_cpufreq_driver);
}


MODULE_AUTHOR("Intrinsyc Software Inc.");
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
MODULE_LICENSE("GPL");
module_init(pxa_cpu_init);
module_exit(pxa_cpu_exit);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
9e2697ff	2	/*
9e2697ff RK	3	* Copyright (C) 2002,2003 Intrinsyc Software
9e2697ff RK	4	*
9e2697ff RK	5	* History:
	6	* 31-Jul-2002 : Initial version [FB]
	7	* 29-Jan-2003 : added PXA255 support [FB]
	8	* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
	9	*
	10	* Note:
	11	* This driver may change the memory bus clock rate, but will not do any
	12	* platform specific access timing changes... for example if you have flash
	13	* memory connected to CS0, you will need to register a platform specific
	14	* notifier which will adjust the memory access strobes to maintain a
	15	* minimum strobe width.
9e2697ff RK	16	*/
9e2697ff RK	17
1c5864e2 JP	18	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	19
9e2697ff RK	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/sched.h>
	23	#include <linux/init.h>
	24	#include <linux/cpufreq.h>
3dbeef23 RJ	25	#include <linux/err.h>
3dbeef23 RJ	26	#include <linux/regulator/consumer.h>
ad68bb9f	27	#include <linux/io.h>
9e2697ff	28
a09e64fb	29	#include <mach/pxa2xx-regs.h>
ad68bb9f	30	#include <mach/smemc.h>
9e2697ff RK	31
	32	#ifdef DEBUG
	33	static unsigned int freq_debug;
c710e39c	34	module_param(freq_debug, uint, 0);
9e2697ff RK	35	MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
	36	#else
	37	#define freq_debug 0
	38	#endif
	39
3dbeef23 RJ	40	static struct regulator *vcc_core;
3dbeef23 RJ	41
592eb999 RJ	42	static unsigned int pxa27x_maxfreq;
	43	module_param(pxa27x_maxfreq, uint, 0);
	44	MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
	45	"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
	46
d9278077 RJ	47	struct pxa_cpufreq_data {
	48	struct clk *clk_core;
	49	};
	50	static struct pxa_cpufreq_data pxa_cpufreq_data;
	51
52352558	52	struct pxa_freqs {
9e2697ff	53	unsigned int khz;
3dbeef23 RJ	54	int vmin;
3dbeef23 RJ	55	int vmax;
52352558	56	};
9e2697ff	57
592eb999 RJ	58	/*
	59	* PXA255 definitions
	60	*/
03c22990	61	static const struct pxa_freqs pxa255_run_freqs[] =
9e2697ff	62	{
d9278077 RJ	63	/* CPU MEMBUS run turbo PXbus SDRAM */
	64	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	65	{132700, -1, -1}, /* 133, 133, 66, 66 */
	66	{199100, -1, -1}, /* 199, 199, 99, 99 */
	67	{265400, -1, -1}, /* 265, 265, 133, 66 */
	68	{331800, -1, -1}, /* 331, 331, 166, 83 */
	69	{398100, -1, -1}, /* 398, 398, 196, 99 */
9e2697ff	70	};
9e2697ff RK	71
9e2697ff RK	72	/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
03c22990	73	static const struct pxa_freqs pxa255_turbo_freqs[] =
9e2697ff	74	{
d9278077 RJ	75	/* CPU run turbo PXbus SDRAM */
	76	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	77	{199100, -1, -1}, /* 99, 199, 50, 99 */
	78	{298500, -1, -1}, /* 99, 287, 50, 99 */
	79	{298600, -1, -1}, /* 199, 287, 99, 99 */
	80	{398100, -1, -1}, /* 199, 398, 99, 99 */
9e2697ff	81	};
9e2697ff	82
592eb999 RJ	83	#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
	84	#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
	85
	86	static struct cpufreq_frequency_table
	87	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
3679389b	88	static struct cpufreq_frequency_table
592eb999 RJ	89	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
592eb999 RJ	90
65587f7d MZ	91	static unsigned int pxa255_turbo_table;
	92	module_param(pxa255_turbo_table, uint, 0);
	93	MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
	94
52352558	95	static struct pxa_freqs pxa27x_freqs[] = {
d9278077 RJ	96	{104000, 900000, 1705000 },
	97	{156000, 1000000, 1705000 },
	98	{208000, 1180000, 1705000 },
	99	{312000, 1250000, 1705000 },
	100	{416000, 1350000, 1705000 },
	101	{520000, 1450000, 1705000 },
	102	{624000, 1550000, 1705000 }
592eb999 RJ	103	};
	104
	105	#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
	106	static struct cpufreq_frequency_table
	107	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
9e2697ff RK	108
	109	extern unsigned get_clk_frequency_khz(int info);
	110
3dbeef23 RJ	111	#ifdef CONFIG_REGULATOR
3dbeef23 RJ	112
03c22990	113	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	114	{
	115	int ret = 0;
	116	int vmin, vmax;
	117
	118	if (!cpu_is_pxa27x())
	119	return 0;
	120
	121	vmin = pxa_freq->vmin;
	122	vmax = pxa_freq->vmax;
	123	if ((vmin == -1) \|\| (vmax == -1))
	124	return 0;
	125
	126	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	127	if (ret)
1c5864e2	128	pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
3dbeef23 RJ	129	return ret;
	130	}
	131
9505b98c	132	static void pxa_cpufreq_init_voltages(void)
3dbeef23 RJ	133	{
	134	vcc_core = regulator_get(NULL, "vcc_core");
	135	if (IS_ERR(vcc_core)) {
1c5864e2	136	pr_info("Didn't find vcc_core regulator\n");
3dbeef23 RJ	137	vcc_core = NULL;
3dbeef23 RJ	138	} else {
1c5864e2	139	pr_info("Found vcc_core regulator\n");
3dbeef23 RJ	140	}
	141	}
	142	#else
fb2a24a1	143	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	144	{
	145	return 0;
	146	}
	147
9505b98c	148	static void pxa_cpufreq_init_voltages(void) { }
3dbeef23 RJ	149	#endif
3dbeef23 RJ	150
65587f7d	151	static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
03c22990	152	const struct pxa_freqs **pxa_freqs)
592eb999 RJ	153	{
592eb999 RJ	154	if (cpu_is_pxa25x()) {
65587f7d	155	if (!pxa255_turbo_table) {
592eb999 RJ	156	*pxa_freqs = pxa255_run_freqs;
592eb999 RJ	157	*freq_table = pxa255_run_freq_table;
65587f7d	158	} else {
592eb999 RJ	159	*pxa_freqs = pxa255_turbo_freqs;
592eb999 RJ	160	*freq_table = pxa255_turbo_freq_table;
592eb999	161	}
7264a2bb	162	} else if (cpu_is_pxa27x()) {
592eb999 RJ	163	*pxa_freqs = pxa27x_freqs;
592eb999 RJ	164	*freq_table = pxa27x_freq_table;
7264a2bb AB	165	} else {
7264a2bb AB	166	BUG();
592eb999 RJ	167	}
	168	}
	169
	170	static void pxa27x_guess_max_freq(void)
	171	{
	172	if (!pxa27x_maxfreq) {
	173	pxa27x_maxfreq = 416000;
b49c22a6 JP	174	pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
b49c22a6 JP	175	pxa27x_maxfreq);
592eb999 RJ	176	} else {
	177	pxa27x_maxfreq *= 1000;
	178	}
	179	}
	180
592eb999 RJ	181	static unsigned int pxa_cpufreq_get(unsigned int cpu)
592eb999 RJ	182	{
d9278077 RJ	183	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	184
	185	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
592eb999 RJ	186	}
592eb999 RJ	187
9c0ebcf7	188	static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
9e2697ff RK	189	{
9e2697ff RK	190	struct cpufreq_frequency_table *pxa_freqs_table;
03c22990	191	const struct pxa_freqs *pxa_freq_settings;
d9278077 RJ	192	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
d9278077 RJ	193	unsigned int new_freq_cpu;
3dbeef23	194	int ret = 0;
9e2697ff RK	195
9e2697ff RK	196	/* Get the current policy */
65587f7d	197	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
9e2697ff	198
592eb999	199	new_freq_cpu = pxa_freq_settings[idx].khz;
9e2697ff RK	200
9e2697ff RK	201	if (freq_debug)
d9278077 RJ	202	pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
d9278077 RJ	203	policy->cur / 1000, new_freq_cpu / 1000);
9e2697ff	204
d4019f0a	205	if (vcc_core && new_freq_cpu > policy->cur) {
3dbeef23	206	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
d4019f0a VK	207	if (ret)
	208	return ret;
	209	}
9e2697ff	210
d9278077	211	clk_set_rate(data->clk_core, new_freq_cpu * 1000);
9e2697ff	212
3dbeef23 RJ	213	/*
	214	* Even if voltage setting fails, we don't report it, as the frequency
	215	* change succeeded. The voltage reduction is not a critical failure,
	216	* only power savings will suffer from this.
	217	*
	218	* Note: if the voltage change fails, and a return value is returned, a
	219	* bug is triggered (seems a deadlock). Should anybody find out where,
	220	* the "return 0" should become a "return ret".
	221	*/
d4019f0a	222	if (vcc_core && new_freq_cpu < policy->cur)
3dbeef23 RJ	223	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
3dbeef23 RJ	224
9e2697ff RK	225	return 0;
	226	}
	227
50e77fcd	228	static int pxa_cpufreq_init(struct cpufreq_policy *policy)
9e2697ff RK	229	{
9e2697ff RK	230	int i;
592eb999	231	unsigned int freq;
65587f7d	232	struct cpufreq_frequency_table *pxa255_freq_table;
03c22990	233	const struct pxa_freqs *pxa255_freqs;
592eb999 RJ	234
	235	/* try to guess pxa27x cpu */
	236	if (cpu_is_pxa27x())
	237	pxa27x_guess_max_freq();
9e2697ff	238
3dbeef23 RJ	239	pxa_cpufreq_init_voltages();
3dbeef23 RJ	240
9e2697ff	241	/* set default policy and cpuinfo */
9e2697ff	242	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
9e2697ff	243
592eb999 RJ	244	/* Generate pxa25x the run cpufreq_frequency_table struct */
592eb999 RJ	245	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
9e2697ff	246	pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
50701588	247	pxa255_run_freq_table[i].driver_data = i;
9e2697ff	248	}
9e2697ff	249	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
592eb999 RJ	250
	251	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	252	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
3679389b RJ	253	pxa255_turbo_freq_table[i].frequency =
3679389b RJ	254	pxa255_turbo_freqs[i].khz;
50701588	255	pxa255_turbo_freq_table[i].driver_data = i;
9e2697ff RK	256	}
	257	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
	258
65587f7d MZ	259	pxa255_turbo_table = !!pxa255_turbo_table;
65587f7d MZ	260
592eb999 RJ	261	/* Generate the pxa27x cpufreq_frequency_table struct */
	262	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
	263	freq = pxa27x_freqs[i].khz;
	264	if (freq > pxa27x_maxfreq)
	265	break;
	266	pxa27x_freq_table[i].frequency = freq;
50701588	267	pxa27x_freq_table[i].driver_data = i;
592eb999	268	}
50701588	269	pxa27x_freq_table[i].driver_data = i;
592eb999 RJ	270	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
	271
	272	/*
	273	* Set the policy's minimum and maximum frequencies from the tables
	274	* just constructed. This sets cpuinfo.mxx_freq, min and max.
	275	*/
65587f7d MZ	276	if (cpu_is_pxa25x()) {
65587f7d MZ	277	find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
1c5864e2	278	pr_info("using %s frequency table\n",
65587f7d	279	pxa255_turbo_table ? "turbo" : "run");
6a77a1e6	280
8ed5a219	281	policy->freq_table = pxa255_freq_table;
65587f7d	282	}
6a77a1e6	283	else if (cpu_is_pxa27x()) {
8ed5a219	284	policy->freq_table = pxa27x_freq_table;
6a77a1e6	285	}
592eb999	286
1c5864e2	287	pr_info("frequency change support initialized\n");
9e2697ff RK	288
	289	return 0;
	290	}
	291
	292	static struct cpufreq_driver pxa_cpufreq_driver = {
ae6b4271	293	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
bf36e48d	294	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	295	.target_index = pxa_set_target,
9e2697ff	296	.init = pxa_cpufreq_init,
ea833f0b	297	.get = pxa_cpufreq_get,
592eb999	298	.name = "PXA2xx",
d9278077	299	.driver_data = &pxa_cpufreq_data,
9e2697ff RK	300	};
	301
	302	static int __init pxa_cpu_init(void)
	303	{
	304	int ret = -ENODEV;
d9278077 RJ	305
	306	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	307	if (IS_ERR(pxa_cpufreq_data.clk_core))
	308	return PTR_ERR(pxa_cpufreq_data.clk_core);
	309
592eb999	310	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x())
9e2697ff RK	311	ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	312	return ret;
	313	}
	314
	315	static void __exit pxa_cpu_exit(void)
	316	{
592eb999	317	cpufreq_unregister_driver(&pxa_cpufreq_driver);
9e2697ff RK	318	}
	319
	320
3679389b RJ	321	MODULE_AUTHOR("Intrinsyc Software Inc.");
3679389b RJ	322	MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
9e2697ff RK	323	MODULE_LICENSE("GPL");
	324	module_init(pxa_cpu_init);
	325	module_exit(pxa_cpu_exit);