[linux-2.6-block.git] / drivers / cpufreq / pxa2xx-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2002,2003 Intrinsyc Software
 *
 * History:
 *   31-Jul-2002 : Initial version [FB]
 *   29-Jan-2003 : added PXA255 support [FB]
 *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
 *
 * Note:
 *   This driver may change the memory bus clock rate, but will not do any
 *   platform specific access timing changes... for example if you have flash
 *   memory connected to CS0, you will need to register a platform specific
 *   notifier which will adjust the memory access strobes to maintain a
 *   minimum strobe width.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/pxa/cpu.h>
#include <linux/io.h>

#ifdef DEBUG
static unsigned int freq_debug;
module_param(freq_debug, uint, 0);
MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
#else
#define freq_debug  0
#endif

static struct regulator *vcc_core;

static unsigned int pxa27x_maxfreq;
module_param(pxa27x_maxfreq, uint, 0);
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");

struct pxa_cpufreq_data {
	struct clk *clk_core;
};
static struct pxa_cpufreq_data  pxa_cpufreq_data;

struct pxa_freqs {
	unsigned int khz;
	int vmin;
	int vmax;
};

/*
 * PXA255 definitions
 */
static const struct pxa_freqs pxa255_run_freqs[] =
{
	/* CPU   MEMBUS		   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{132700, -1, -1},	/* 133,  133,   66,   66  */
	{199100, -1, -1},	/* 199,  199,   99,   99  */
	{265400, -1, -1},	/* 265,  265,  133,   66  */
	{331800, -1, -1},	/* 331,  331,  166,   83  */
	{398100, -1, -1},	/* 398,  398,  196,   99  */
};

/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static const struct pxa_freqs pxa255_turbo_freqs[] =
{
	/* CPU			   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{199100, -1, -1},	/*  99,  199,   50,   99  */
	{298500, -1, -1},	/*  99,  287,   50,   99  */
	{298600, -1, -1},	/* 199,  287,   99,   99  */
	{398100, -1, -1},	/* 199,  398,   99,   99  */
};

#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)

static struct cpufreq_frequency_table
	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
static struct cpufreq_frequency_table
	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];

static unsigned int pxa255_turbo_table;
module_param(pxa255_turbo_table, uint, 0);
MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");

static struct pxa_freqs pxa27x_freqs[] = {
	{104000,  900000, 1705000 },
	{156000, 1000000, 1705000 },
	{208000, 1180000, 1705000 },
	{312000, 1250000, 1705000 },
	{416000, 1350000, 1705000 },
	{520000, 1450000, 1705000 },
	{624000, 1550000, 1705000 }
};

#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
static struct cpufreq_frequency_table
	pxa27x_freq_table[NUM_PXA27x_FREQS+1];

#ifdef CONFIG_REGULATOR

static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	int ret = 0;
	int vmin, vmax;

	if (!cpu_is_pxa27x())
		return 0;

	vmin = pxa_freq->vmin;
	vmax = pxa_freq->vmax;
	if ((vmin == -1) || (vmax == -1))
		return 0;

	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	if (ret)
		pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
	return ret;
}

static void pxa_cpufreq_init_voltages(void)
{
	vcc_core = regulator_get(NULL, "vcc_core");
	if (IS_ERR(vcc_core)) {
		pr_info("Didn't find vcc_core regulator\n");
		vcc_core = NULL;
	} else {
		pr_info("Found vcc_core regulator\n");
	}
}
#else
static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	return 0;
}

static void pxa_cpufreq_init_voltages(void) { }
#endif

static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
			     const struct pxa_freqs **pxa_freqs)
{
	if (cpu_is_pxa25x()) {
		if (!pxa255_turbo_table) {
			*pxa_freqs = pxa255_run_freqs;
			*freq_table = pxa255_run_freq_table;
		} else {
			*pxa_freqs = pxa255_turbo_freqs;
			*freq_table = pxa255_turbo_freq_table;
		}
	} else if (cpu_is_pxa27x()) {
		*pxa_freqs = pxa27x_freqs;
		*freq_table = pxa27x_freq_table;
	} else {
		BUG();
	}
}

static void pxa27x_guess_max_freq(void)
{
	if (!pxa27x_maxfreq) {
		pxa27x_maxfreq = 416000;
		pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
			pxa27x_maxfreq);
	} else {
		pxa27x_maxfreq *= 1000;
	}
}

static unsigned int pxa_cpufreq_get(unsigned int cpu)
{
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();

	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
}

static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
{
	struct cpufreq_frequency_table *pxa_freqs_table;
	const struct pxa_freqs *pxa_freq_settings;
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	unsigned int new_freq_cpu;
	int ret = 0;

	/* Get the current policy */
	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);

	new_freq_cpu = pxa_freq_settings[idx].khz;

	if (freq_debug)
		pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
			 policy->cur / 1000,  new_freq_cpu / 1000);

	if (vcc_core && new_freq_cpu > policy->cur) {
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
		if (ret)
			return ret;
	}

	clk_set_rate(data->clk_core, new_freq_cpu * 1000);

	/*
	 * Even if voltage setting fails, we don't report it, as the frequency
	 * change succeeded. The voltage reduction is not a critical failure,
	 * only power savings will suffer from this.
	 *
	 * Note: if the voltage change fails, and a return value is returned, a
	 * bug is triggered (seems a deadlock). Should anybody find out where,
	 * the "return 0" should become a "return ret".
	 */
	if (vcc_core && new_freq_cpu < policy->cur)
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);

	return 0;
}

static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
	int i;
	unsigned int freq;
	struct cpufreq_frequency_table *pxa255_freq_table;
	const struct pxa_freqs *pxa255_freqs;

	/* try to guess pxa27x cpu */
	if (cpu_is_pxa27x())
		pxa27x_guess_max_freq();

	pxa_cpufreq_init_voltages();

	/* set default policy and cpuinfo */
	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */

	/* Generate pxa25x the run cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
		pxa255_run_freq_table[i].driver_data = i;
	}
	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
		pxa255_turbo_freq_table[i].frequency =
			pxa255_turbo_freqs[i].khz;
		pxa255_turbo_freq_table[i].driver_data = i;
	}
	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;

	pxa255_turbo_table = !!pxa255_turbo_table;

	/* Generate the pxa27x cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
		freq = pxa27x_freqs[i].khz;
		if (freq > pxa27x_maxfreq)
			break;
		pxa27x_freq_table[i].frequency = freq;
		pxa27x_freq_table[i].driver_data = i;
	}
	pxa27x_freq_table[i].driver_data = i;
	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/*
	 * Set the policy's minimum and maximum frequencies from the tables
	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
	 */
	if (cpu_is_pxa25x()) {
		find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
		pr_info("using %s frequency table\n",
			pxa255_turbo_table ? "turbo" : "run");

		policy->freq_table = pxa255_freq_table;
	}
	else if (cpu_is_pxa27x()) {
		policy->freq_table = pxa27x_freq_table;
	}

	pr_info("frequency change support initialized\n");

	return 0;
}

static struct cpufreq_driver pxa_cpufreq_driver = {
	.flags	= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify	= cpufreq_generic_frequency_table_verify,
	.target_index = pxa_set_target,
	.init	= pxa_cpufreq_init,
	.get	= pxa_cpufreq_get,
	.name	= "PXA2xx",
	.driver_data = &pxa_cpufreq_data,
};

static int __init pxa_cpu_init(void)
{
	int ret = -ENODEV;

	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	if (IS_ERR(pxa_cpufreq_data.clk_core))
		return PTR_ERR(pxa_cpufreq_data.clk_core);

	if (cpu_is_pxa25x() || cpu_is_pxa27x())
		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	return ret;
}

static void __exit pxa_cpu_exit(void)
{
	cpufreq_unregister_driver(&pxa_cpufreq_driver);
}


MODULE_AUTHOR("Intrinsyc Software Inc.");
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
MODULE_LICENSE("GPL");
module_init(pxa_cpu_init);
module_exit(pxa_cpu_exit);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
9e2697ff	2	/*
9e2697ff RK	3	* Copyright (C) 2002,2003 Intrinsyc Software
9e2697ff RK	4	*
9e2697ff RK	5	* History:
	6	* 31-Jul-2002 : Initial version [FB]
	7	* 29-Jan-2003 : added PXA255 support [FB]
	8	* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
	9	*
	10	* Note:
	11	* This driver may change the memory bus clock rate, but will not do any
	12	* platform specific access timing changes... for example if you have flash
	13	* memory connected to CS0, you will need to register a platform specific
	14	* notifier which will adjust the memory access strobes to maintain a
	15	* minimum strobe width.
9e2697ff RK	16	*/
9e2697ff RK	17
1c5864e2 JP	18	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	19
9e2697ff RK	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/sched.h>
	23	#include <linux/init.h>
	24	#include <linux/cpufreq.h>
3dbeef23 RJ	25	#include <linux/err.h>
3dbeef23 RJ	26	#include <linux/regulator/consumer.h>
08d3df8c	27	#include <linux/soc/pxa/cpu.h>
ad68bb9f	28	#include <linux/io.h>
9e2697ff	29
9e2697ff RK	30	#ifdef DEBUG
9e2697ff RK	31	static unsigned int freq_debug;
c710e39c	32	module_param(freq_debug, uint, 0);
9e2697ff RK	33	MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
	34	#else
	35	#define freq_debug 0
	36	#endif
	37
3dbeef23 RJ	38	static struct regulator *vcc_core;
3dbeef23 RJ	39
592eb999 RJ	40	static unsigned int pxa27x_maxfreq;
	41	module_param(pxa27x_maxfreq, uint, 0);
	42	MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
	43	"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
	44
d9278077 RJ	45	struct pxa_cpufreq_data {
	46	struct clk *clk_core;
	47	};
	48	static struct pxa_cpufreq_data pxa_cpufreq_data;
	49
52352558	50	struct pxa_freqs {
9e2697ff	51	unsigned int khz;
3dbeef23 RJ	52	int vmin;
3dbeef23 RJ	53	int vmax;
52352558	54	};
9e2697ff	55
592eb999 RJ	56	/*
	57	* PXA255 definitions
	58	*/
03c22990	59	static const struct pxa_freqs pxa255_run_freqs[] =
9e2697ff	60	{
d9278077 RJ	61	/* CPU MEMBUS run turbo PXbus SDRAM */
	62	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	63	{132700, -1, -1}, /* 133, 133, 66, 66 */
	64	{199100, -1, -1}, /* 199, 199, 99, 99 */
	65	{265400, -1, -1}, /* 265, 265, 133, 66 */
	66	{331800, -1, -1}, /* 331, 331, 166, 83 */
	67	{398100, -1, -1}, /* 398, 398, 196, 99 */
9e2697ff	68	};
9e2697ff RK	69
9e2697ff RK	70	/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
03c22990	71	static const struct pxa_freqs pxa255_turbo_freqs[] =
9e2697ff	72	{
d9278077 RJ	73	/* CPU run turbo PXbus SDRAM */
	74	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	75	{199100, -1, -1}, /* 99, 199, 50, 99 */
	76	{298500, -1, -1}, /* 99, 287, 50, 99 */
	77	{298600, -1, -1}, /* 199, 287, 99, 99 */
	78	{398100, -1, -1}, /* 199, 398, 99, 99 */
9e2697ff	79	};
9e2697ff	80
592eb999 RJ	81	#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
	82	#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
	83
	84	static struct cpufreq_frequency_table
	85	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
3679389b	86	static struct cpufreq_frequency_table
592eb999 RJ	87	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
592eb999 RJ	88
65587f7d MZ	89	static unsigned int pxa255_turbo_table;
	90	module_param(pxa255_turbo_table, uint, 0);
	91	MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
	92
52352558	93	static struct pxa_freqs pxa27x_freqs[] = {
d9278077 RJ	94	{104000, 900000, 1705000 },
	95	{156000, 1000000, 1705000 },
	96	{208000, 1180000, 1705000 },
	97	{312000, 1250000, 1705000 },
	98	{416000, 1350000, 1705000 },
	99	{520000, 1450000, 1705000 },
	100	{624000, 1550000, 1705000 }
592eb999 RJ	101	};
	102
	103	#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
	104	static struct cpufreq_frequency_table
	105	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
9e2697ff	106
3dbeef23 RJ	107	#ifdef CONFIG_REGULATOR
3dbeef23 RJ	108
03c22990	109	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	110	{
	111	int ret = 0;
	112	int vmin, vmax;
	113
	114	if (!cpu_is_pxa27x())
	115	return 0;
	116
	117	vmin = pxa_freq->vmin;
	118	vmax = pxa_freq->vmax;
	119	if ((vmin == -1) \|\| (vmax == -1))
	120	return 0;
	121
	122	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	123	if (ret)
1c5864e2	124	pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
3dbeef23 RJ	125	return ret;
	126	}
	127
9505b98c	128	static void pxa_cpufreq_init_voltages(void)
3dbeef23 RJ	129	{
	130	vcc_core = regulator_get(NULL, "vcc_core");
	131	if (IS_ERR(vcc_core)) {
1c5864e2	132	pr_info("Didn't find vcc_core regulator\n");
3dbeef23 RJ	133	vcc_core = NULL;
3dbeef23 RJ	134	} else {
1c5864e2	135	pr_info("Found vcc_core regulator\n");
3dbeef23 RJ	136	}
	137	}
	138	#else
fb2a24a1	139	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	140	{
	141	return 0;
	142	}
	143
9505b98c	144	static void pxa_cpufreq_init_voltages(void) { }
3dbeef23 RJ	145	#endif
3dbeef23 RJ	146
65587f7d	147	static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
03c22990	148	const struct pxa_freqs **pxa_freqs)
592eb999 RJ	149	{
592eb999 RJ	150	if (cpu_is_pxa25x()) {
65587f7d	151	if (!pxa255_turbo_table) {
592eb999 RJ	152	*pxa_freqs = pxa255_run_freqs;
592eb999 RJ	153	*freq_table = pxa255_run_freq_table;
65587f7d	154	} else {
592eb999 RJ	155	*pxa_freqs = pxa255_turbo_freqs;
592eb999 RJ	156	*freq_table = pxa255_turbo_freq_table;
592eb999	157	}
7264a2bb	158	} else if (cpu_is_pxa27x()) {
592eb999 RJ	159	*pxa_freqs = pxa27x_freqs;
592eb999 RJ	160	*freq_table = pxa27x_freq_table;
7264a2bb AB	161	} else {
7264a2bb AB	162	BUG();
592eb999 RJ	163	}
	164	}
	165
	166	static void pxa27x_guess_max_freq(void)
	167	{
	168	if (!pxa27x_maxfreq) {
	169	pxa27x_maxfreq = 416000;
b49c22a6 JP	170	pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
b49c22a6 JP	171	pxa27x_maxfreq);
592eb999 RJ	172	} else {
	173	pxa27x_maxfreq *= 1000;
	174	}
	175	}
	176
592eb999 RJ	177	static unsigned int pxa_cpufreq_get(unsigned int cpu)
592eb999 RJ	178	{
d9278077 RJ	179	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	180
	181	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
592eb999 RJ	182	}
592eb999 RJ	183
9c0ebcf7	184	static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
9e2697ff RK	185	{
9e2697ff RK	186	struct cpufreq_frequency_table *pxa_freqs_table;
03c22990	187	const struct pxa_freqs *pxa_freq_settings;
d9278077 RJ	188	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
d9278077 RJ	189	unsigned int new_freq_cpu;
3dbeef23	190	int ret = 0;
9e2697ff RK	191
9e2697ff RK	192	/* Get the current policy */
65587f7d	193	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
9e2697ff	194
592eb999	195	new_freq_cpu = pxa_freq_settings[idx].khz;
9e2697ff RK	196
9e2697ff RK	197	if (freq_debug)
d9278077 RJ	198	pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
d9278077 RJ	199	policy->cur / 1000, new_freq_cpu / 1000);
9e2697ff	200
d4019f0a	201	if (vcc_core && new_freq_cpu > policy->cur) {
3dbeef23	202	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
d4019f0a VK	203	if (ret)
	204	return ret;
	205	}
9e2697ff	206
d9278077	207	clk_set_rate(data->clk_core, new_freq_cpu * 1000);
9e2697ff	208
3dbeef23 RJ	209	/*
	210	* Even if voltage setting fails, we don't report it, as the frequency
	211	* change succeeded. The voltage reduction is not a critical failure,
	212	* only power savings will suffer from this.
	213	*
	214	* Note: if the voltage change fails, and a return value is returned, a
	215	* bug is triggered (seems a deadlock). Should anybody find out where,
	216	* the "return 0" should become a "return ret".
	217	*/
d4019f0a	218	if (vcc_core && new_freq_cpu < policy->cur)
3dbeef23 RJ	219	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
3dbeef23 RJ	220
9e2697ff RK	221	return 0;
	222	}
	223
50e77fcd	224	static int pxa_cpufreq_init(struct cpufreq_policy *policy)
9e2697ff RK	225	{
9e2697ff RK	226	int i;
592eb999	227	unsigned int freq;
65587f7d	228	struct cpufreq_frequency_table *pxa255_freq_table;
03c22990	229	const struct pxa_freqs *pxa255_freqs;
592eb999 RJ	230
	231	/* try to guess pxa27x cpu */
	232	if (cpu_is_pxa27x())
	233	pxa27x_guess_max_freq();
9e2697ff	234
3dbeef23 RJ	235	pxa_cpufreq_init_voltages();
3dbeef23 RJ	236
9e2697ff	237	/* set default policy and cpuinfo */
9e2697ff	238	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
9e2697ff	239
592eb999 RJ	240	/* Generate pxa25x the run cpufreq_frequency_table struct */
592eb999 RJ	241	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
9e2697ff	242	pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
50701588	243	pxa255_run_freq_table[i].driver_data = i;
9e2697ff	244	}
9e2697ff	245	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
592eb999 RJ	246
	247	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	248	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
3679389b RJ	249	pxa255_turbo_freq_table[i].frequency =
3679389b RJ	250	pxa255_turbo_freqs[i].khz;
50701588	251	pxa255_turbo_freq_table[i].driver_data = i;
9e2697ff RK	252	}
	253	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
	254
65587f7d MZ	255	pxa255_turbo_table = !!pxa255_turbo_table;
65587f7d MZ	256
592eb999 RJ	257	/* Generate the pxa27x cpufreq_frequency_table struct */
	258	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
	259	freq = pxa27x_freqs[i].khz;
	260	if (freq > pxa27x_maxfreq)
	261	break;
	262	pxa27x_freq_table[i].frequency = freq;
50701588	263	pxa27x_freq_table[i].driver_data = i;
592eb999	264	}
50701588	265	pxa27x_freq_table[i].driver_data = i;
592eb999 RJ	266	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
	267
	268	/*
	269	* Set the policy's minimum and maximum frequencies from the tables
	270	* just constructed. This sets cpuinfo.mxx_freq, min and max.
	271	*/
65587f7d MZ	272	if (cpu_is_pxa25x()) {
65587f7d MZ	273	find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
1c5864e2	274	pr_info("using %s frequency table\n",
65587f7d	275	pxa255_turbo_table ? "turbo" : "run");
6a77a1e6	276
8ed5a219	277	policy->freq_table = pxa255_freq_table;
65587f7d	278	}
6a77a1e6	279	else if (cpu_is_pxa27x()) {
8ed5a219	280	policy->freq_table = pxa27x_freq_table;
6a77a1e6	281	}
592eb999	282
1c5864e2	283	pr_info("frequency change support initialized\n");
9e2697ff RK	284
	285	return 0;
	286	}
	287
	288	static struct cpufreq_driver pxa_cpufreq_driver = {
ae6b4271	289	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
bf36e48d	290	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	291	.target_index = pxa_set_target,
9e2697ff	292	.init = pxa_cpufreq_init,
ea833f0b	293	.get = pxa_cpufreq_get,
592eb999	294	.name = "PXA2xx",
d9278077	295	.driver_data = &pxa_cpufreq_data,
9e2697ff RK	296	};
	297
	298	static int __init pxa_cpu_init(void)
	299	{
	300	int ret = -ENODEV;
d9278077 RJ	301
	302	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	303	if (IS_ERR(pxa_cpufreq_data.clk_core))
	304	return PTR_ERR(pxa_cpufreq_data.clk_core);
	305
592eb999	306	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x())
9e2697ff RK	307	ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	308	return ret;
	309	}
	310
	311	static void __exit pxa_cpu_exit(void)
	312	{
592eb999	313	cpufreq_unregister_driver(&pxa_cpufreq_driver);
9e2697ff RK	314	}
	315
	316
3679389b RJ	317	MODULE_AUTHOR("Intrinsyc Software Inc.");
3679389b RJ	318	MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
9e2697ff RK	319	MODULE_LICENSE("GPL");
	320	module_init(pxa_cpu_init);
	321	module_exit(pxa_cpu_exit);