[linux-2.6-block.git] / drivers / cpufreq / pxa2xx-cpufreq.c

/*
 *  Copyright (C) 2002,2003 Intrinsyc Software
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * History:
 *   31-Jul-2002 : Initial version [FB]
 *   29-Jan-2003 : added PXA255 support [FB]
 *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
 *
 * Note:
 *   This driver may change the memory bus clock rate, but will not do any
 *   platform specific access timing changes... for example if you have flash
 *   memory connected to CS0, you will need to register a platform specific
 *   notifier which will adjust the memory access strobes to maintain a
 *   minimum strobe width.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/io.h>

#include <mach/pxa2xx-regs.h>
#include <mach/smemc.h>

#ifdef DEBUG
static unsigned int freq_debug;
module_param(freq_debug, uint, 0);
MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
#else
#define freq_debug  0
#endif

static struct regulator *vcc_core;

static unsigned int pxa27x_maxfreq;
module_param(pxa27x_maxfreq, uint, 0);
MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");

struct pxa_cpufreq_data {
	struct clk *clk_core;
};
static struct pxa_cpufreq_data  pxa_cpufreq_data;

struct pxa_freqs {
	unsigned int khz;
	int vmin;
	int vmax;
};

/*
 * PXA255 definitions
 */
static const struct pxa_freqs pxa255_run_freqs[] =
{
	/* CPU   MEMBUS		   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{132700, -1, -1},	/* 133,  133,   66,   66  */
	{199100, -1, -1},	/* 199,  199,   99,   99  */
	{265400, -1, -1},	/* 265,  265,  133,   66  */
	{331800, -1, -1},	/* 331,  331,  166,   83  */
	{398100, -1, -1},	/* 398,  398,  196,   99  */
};

/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
static const struct pxa_freqs pxa255_turbo_freqs[] =
{
	/* CPU			   run  turbo PXbus SDRAM */
	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
	{199100, -1, -1},	/*  99,  199,   50,   99  */
	{298500, -1, -1},	/*  99,  287,   50,   99  */
	{298600, -1, -1},	/* 199,  287,   99,   99  */
	{398100, -1, -1},	/* 199,  398,   99,   99  */
};

#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)

static struct cpufreq_frequency_table
	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
static struct cpufreq_frequency_table
	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];

static unsigned int pxa255_turbo_table;
module_param(pxa255_turbo_table, uint, 0);
MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");

static struct pxa_freqs pxa27x_freqs[] = {
	{104000,  900000, 1705000 },
	{156000, 1000000, 1705000 },
	{208000, 1180000, 1705000 },
	{312000, 1250000, 1705000 },
	{416000, 1350000, 1705000 },
	{520000, 1450000, 1705000 },
	{624000, 1550000, 1705000 }
};

#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
static struct cpufreq_frequency_table
	pxa27x_freq_table[NUM_PXA27x_FREQS+1];

extern unsigned get_clk_frequency_khz(int info);

#ifdef CONFIG_REGULATOR

static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	int ret = 0;
	int vmin, vmax;

	if (!cpu_is_pxa27x())
		return 0;

	vmin = pxa_freq->vmin;
	vmax = pxa_freq->vmax;
	if ((vmin == -1) || (vmax == -1))
		return 0;

	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	if (ret)
		pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
	return ret;
}

static void __init pxa_cpufreq_init_voltages(void)
{
	vcc_core = regulator_get(NULL, "vcc_core");
	if (IS_ERR(vcc_core)) {
		pr_info("Didn't find vcc_core regulator\n");
		vcc_core = NULL;
	} else {
		pr_info("Found vcc_core regulator\n");
	}
}
#else
static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
{
	return 0;
}

static void __init pxa_cpufreq_init_voltages(void) { }
#endif

static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
			     const struct pxa_freqs **pxa_freqs)
{
	if (cpu_is_pxa25x()) {
		if (!pxa255_turbo_table) {
			*pxa_freqs = pxa255_run_freqs;
			*freq_table = pxa255_run_freq_table;
		} else {
			*pxa_freqs = pxa255_turbo_freqs;
			*freq_table = pxa255_turbo_freq_table;
		}
	} else if (cpu_is_pxa27x()) {
		*pxa_freqs = pxa27x_freqs;
		*freq_table = pxa27x_freq_table;
	} else {
		BUG();
	}
}

static void pxa27x_guess_max_freq(void)
{
	if (!pxa27x_maxfreq) {
		pxa27x_maxfreq = 416000;
		pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
			pxa27x_maxfreq);
	} else {
		pxa27x_maxfreq *= 1000;
	}
}

static unsigned int pxa_cpufreq_get(unsigned int cpu)
{
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();

	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
}

static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
{
	struct cpufreq_frequency_table *pxa_freqs_table;
	const struct pxa_freqs *pxa_freq_settings;
	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	unsigned int new_freq_cpu;
	int ret = 0;

	/* Get the current policy */
	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);

	new_freq_cpu = pxa_freq_settings[idx].khz;

	if (freq_debug)
		pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
			 policy->cur / 1000,  new_freq_cpu / 1000);

	if (vcc_core && new_freq_cpu > policy->cur) {
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
		if (ret)
			return ret;
	}

	clk_set_rate(data->clk_core, new_freq_cpu * 1000);

	/*
	 * Even if voltage setting fails, we don't report it, as the frequency
	 * change succeeded. The voltage reduction is not a critical failure,
	 * only power savings will suffer from this.
	 *
	 * Note: if the voltage change fails, and a return value is returned, a
	 * bug is triggered (seems a deadlock). Should anybody find out where,
	 * the "return 0" should become a "return ret".
	 */
	if (vcc_core && new_freq_cpu < policy->cur)
		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);

	return 0;
}

static int pxa_cpufreq_init(struct cpufreq_policy *policy)
{
	int i;
	unsigned int freq;
	struct cpufreq_frequency_table *pxa255_freq_table;
	const struct pxa_freqs *pxa255_freqs;

	/* try to guess pxa27x cpu */
	if (cpu_is_pxa27x())
		pxa27x_guess_max_freq();

	pxa_cpufreq_init_voltages();

	/* set default policy and cpuinfo */
	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */

	/* Generate pxa25x the run cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
		pxa255_run_freq_table[i].driver_data = i;
	}
	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
		pxa255_turbo_freq_table[i].frequency =
			pxa255_turbo_freqs[i].khz;
		pxa255_turbo_freq_table[i].driver_data = i;
	}
	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;

	pxa255_turbo_table = !!pxa255_turbo_table;

	/* Generate the pxa27x cpufreq_frequency_table struct */
	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
		freq = pxa27x_freqs[i].khz;
		if (freq > pxa27x_maxfreq)
			break;
		pxa27x_freq_table[i].frequency = freq;
		pxa27x_freq_table[i].driver_data = i;
	}
	pxa27x_freq_table[i].driver_data = i;
	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;

	/*
	 * Set the policy's minimum and maximum frequencies from the tables
	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
	 */
	if (cpu_is_pxa25x()) {
		find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
		pr_info("using %s frequency table\n",
			pxa255_turbo_table ? "turbo" : "run");

		policy->freq_table = pxa255_freq_table;
	}
	else if (cpu_is_pxa27x()) {
		policy->freq_table = pxa27x_freq_table;
	}

	pr_info("frequency change support initialized\n");

	return 0;
}

static struct cpufreq_driver pxa_cpufreq_driver = {
	.flags	= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify	= cpufreq_generic_frequency_table_verify,
	.target_index = pxa_set_target,
	.init	= pxa_cpufreq_init,
	.get	= pxa_cpufreq_get,
	.name	= "PXA2xx",
	.driver_data = &pxa_cpufreq_data,
};

static int __init pxa_cpu_init(void)
{
	int ret = -ENODEV;

	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	if (IS_ERR(pxa_cpufreq_data.clk_core))
		return PTR_ERR(pxa_cpufreq_data.clk_core);

	if (cpu_is_pxa25x() || cpu_is_pxa27x())
		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	return ret;
}

static void __exit pxa_cpu_exit(void)
{
	cpufreq_unregister_driver(&pxa_cpufreq_driver);
}


MODULE_AUTHOR("Intrinsyc Software Inc.");
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
MODULE_LICENSE("GPL");
module_init(pxa_cpu_init);
module_exit(pxa_cpu_exit);
Commit	Line	Data
9e2697ff	1	/*
9e2697ff RK	2	* Copyright (C) 2002,2003 Intrinsyc Software
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	* History:
	19	* 31-Jul-2002 : Initial version [FB]
	20	* 29-Jan-2003 : added PXA255 support [FB]
	21	* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
	22	*
	23	* Note:
	24	* This driver may change the memory bus clock rate, but will not do any
	25	* platform specific access timing changes... for example if you have flash
	26	* memory connected to CS0, you will need to register a platform specific
	27	* notifier which will adjust the memory access strobes to maintain a
	28	* minimum strobe width.
	29	*
	30	*/
	31
1c5864e2 JP	32	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	33
9e2697ff RK	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/sched.h>
	37	#include <linux/init.h>
	38	#include <linux/cpufreq.h>
3dbeef23 RJ	39	#include <linux/err.h>
3dbeef23 RJ	40	#include <linux/regulator/consumer.h>
ad68bb9f	41	#include <linux/io.h>
9e2697ff	42
a09e64fb	43	#include <mach/pxa2xx-regs.h>
ad68bb9f	44	#include <mach/smemc.h>
9e2697ff RK	45
	46	#ifdef DEBUG
	47	static unsigned int freq_debug;
c710e39c	48	module_param(freq_debug, uint, 0);
9e2697ff RK	49	MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
	50	#else
	51	#define freq_debug 0
	52	#endif
	53
3dbeef23 RJ	54	static struct regulator *vcc_core;
3dbeef23 RJ	55
592eb999 RJ	56	static unsigned int pxa27x_maxfreq;
	57	module_param(pxa27x_maxfreq, uint, 0);
	58	MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
	59	"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
	60
d9278077 RJ	61	struct pxa_cpufreq_data {
	62	struct clk *clk_core;
	63	};
	64	static struct pxa_cpufreq_data pxa_cpufreq_data;
	65
52352558	66	struct pxa_freqs {
9e2697ff	67	unsigned int khz;
3dbeef23 RJ	68	int vmin;
3dbeef23 RJ	69	int vmax;
52352558	70	};
9e2697ff	71
592eb999 RJ	72	/*
	73	* PXA255 definitions
	74	*/
03c22990	75	static const struct pxa_freqs pxa255_run_freqs[] =
9e2697ff	76	{
d9278077 RJ	77	/* CPU MEMBUS run turbo PXbus SDRAM */
	78	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	79	{132700, -1, -1}, /* 133, 133, 66, 66 */
	80	{199100, -1, -1}, /* 199, 199, 99, 99 */
	81	{265400, -1, -1}, /* 265, 265, 133, 66 */
	82	{331800, -1, -1}, /* 331, 331, 166, 83 */
	83	{398100, -1, -1}, /* 398, 398, 196, 99 */
9e2697ff	84	};
9e2697ff RK	85
9e2697ff RK	86	/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
03c22990	87	static const struct pxa_freqs pxa255_turbo_freqs[] =
9e2697ff	88	{
d9278077 RJ	89	/* CPU run turbo PXbus SDRAM */
	90	{ 99500, -1, -1}, /* 99, 99, 50, 50 */
	91	{199100, -1, -1}, /* 99, 199, 50, 99 */
	92	{298500, -1, -1}, /* 99, 287, 50, 99 */
	93	{298600, -1, -1}, /* 199, 287, 99, 99 */
	94	{398100, -1, -1}, /* 199, 398, 99, 99 */
9e2697ff	95	};
9e2697ff	96
592eb999 RJ	97	#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
	98	#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
	99
	100	static struct cpufreq_frequency_table
	101	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
3679389b	102	static struct cpufreq_frequency_table
592eb999 RJ	103	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
592eb999 RJ	104
65587f7d MZ	105	static unsigned int pxa255_turbo_table;
	106	module_param(pxa255_turbo_table, uint, 0);
	107	MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
	108
52352558	109	static struct pxa_freqs pxa27x_freqs[] = {
d9278077 RJ	110	{104000, 900000, 1705000 },
	111	{156000, 1000000, 1705000 },
	112	{208000, 1180000, 1705000 },
	113	{312000, 1250000, 1705000 },
	114	{416000, 1350000, 1705000 },
	115	{520000, 1450000, 1705000 },
	116	{624000, 1550000, 1705000 }
592eb999 RJ	117	};
	118
	119	#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
	120	static struct cpufreq_frequency_table
	121	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
9e2697ff RK	122
	123	extern unsigned get_clk_frequency_khz(int info);
	124
3dbeef23 RJ	125	#ifdef CONFIG_REGULATOR
3dbeef23 RJ	126
03c22990	127	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	128	{
	129	int ret = 0;
	130	int vmin, vmax;
	131
	132	if (!cpu_is_pxa27x())
	133	return 0;
	134
	135	vmin = pxa_freq->vmin;
	136	vmax = pxa_freq->vmax;
	137	if ((vmin == -1) \|\| (vmax == -1))
	138	return 0;
	139
	140	ret = regulator_set_voltage(vcc_core, vmin, vmax);
	141	if (ret)
1c5864e2	142	pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
3dbeef23 RJ	143	return ret;
	144	}
	145
295dbde1	146	static void __init pxa_cpufreq_init_voltages(void)
3dbeef23 RJ	147	{
	148	vcc_core = regulator_get(NULL, "vcc_core");
	149	if (IS_ERR(vcc_core)) {
1c5864e2	150	pr_info("Didn't find vcc_core regulator\n");
3dbeef23 RJ	151	vcc_core = NULL;
3dbeef23 RJ	152	} else {
1c5864e2	153	pr_info("Found vcc_core regulator\n");
3dbeef23 RJ	154	}
	155	}
	156	#else
fb2a24a1	157	static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
3dbeef23 RJ	158	{
	159	return 0;
	160	}
	161
295dbde1	162	static void __init pxa_cpufreq_init_voltages(void) { }
3dbeef23 RJ	163	#endif
3dbeef23 RJ	164
65587f7d	165	static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
03c22990	166	const struct pxa_freqs **pxa_freqs)
592eb999 RJ	167	{
592eb999 RJ	168	if (cpu_is_pxa25x()) {
65587f7d	169	if (!pxa255_turbo_table) {
592eb999 RJ	170	*pxa_freqs = pxa255_run_freqs;
592eb999 RJ	171	*freq_table = pxa255_run_freq_table;
65587f7d	172	} else {
592eb999 RJ	173	*pxa_freqs = pxa255_turbo_freqs;
592eb999 RJ	174	*freq_table = pxa255_turbo_freq_table;
592eb999	175	}
7264a2bb	176	} else if (cpu_is_pxa27x()) {
592eb999 RJ	177	*pxa_freqs = pxa27x_freqs;
592eb999 RJ	178	*freq_table = pxa27x_freq_table;
7264a2bb AB	179	} else {
7264a2bb AB	180	BUG();
592eb999 RJ	181	}
	182	}
	183
	184	static void pxa27x_guess_max_freq(void)
	185	{
	186	if (!pxa27x_maxfreq) {
	187	pxa27x_maxfreq = 416000;
b49c22a6 JP	188	pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
b49c22a6 JP	189	pxa27x_maxfreq);
592eb999 RJ	190	} else {
	191	pxa27x_maxfreq *= 1000;
	192	}
	193	}
	194
592eb999 RJ	195	static unsigned int pxa_cpufreq_get(unsigned int cpu)
592eb999 RJ	196	{
d9278077 RJ	197	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
	198
	199	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
592eb999 RJ	200	}
592eb999 RJ	201
9c0ebcf7	202	static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
9e2697ff RK	203	{
9e2697ff RK	204	struct cpufreq_frequency_table *pxa_freqs_table;
03c22990	205	const struct pxa_freqs *pxa_freq_settings;
d9278077 RJ	206	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
d9278077 RJ	207	unsigned int new_freq_cpu;
3dbeef23	208	int ret = 0;
9e2697ff RK	209
9e2697ff RK	210	/* Get the current policy */
65587f7d	211	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
9e2697ff	212
592eb999	213	new_freq_cpu = pxa_freq_settings[idx].khz;
9e2697ff RK	214
9e2697ff RK	215	if (freq_debug)
d9278077 RJ	216	pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
d9278077 RJ	217	policy->cur / 1000, new_freq_cpu / 1000);
9e2697ff	218
d4019f0a	219	if (vcc_core && new_freq_cpu > policy->cur) {
3dbeef23	220	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
d4019f0a VK	221	if (ret)
	222	return ret;
	223	}
9e2697ff	224
d9278077	225	clk_set_rate(data->clk_core, new_freq_cpu * 1000);
9e2697ff	226
3dbeef23 RJ	227	/*
	228	* Even if voltage setting fails, we don't report it, as the frequency
	229	* change succeeded. The voltage reduction is not a critical failure,
	230	* only power savings will suffer from this.
	231	*
	232	* Note: if the voltage change fails, and a return value is returned, a
	233	* bug is triggered (seems a deadlock). Should anybody find out where,
	234	* the "return 0" should become a "return ret".
	235	*/
d4019f0a	236	if (vcc_core && new_freq_cpu < policy->cur)
3dbeef23 RJ	237	ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
3dbeef23 RJ	238
9e2697ff RK	239	return 0;
	240	}
	241
50e77fcd	242	static int pxa_cpufreq_init(struct cpufreq_policy *policy)
9e2697ff RK	243	{
9e2697ff RK	244	int i;
592eb999	245	unsigned int freq;
65587f7d	246	struct cpufreq_frequency_table *pxa255_freq_table;
03c22990	247	const struct pxa_freqs *pxa255_freqs;
592eb999 RJ	248
	249	/* try to guess pxa27x cpu */
	250	if (cpu_is_pxa27x())
	251	pxa27x_guess_max_freq();
9e2697ff	252
3dbeef23 RJ	253	pxa_cpufreq_init_voltages();
3dbeef23 RJ	254
9e2697ff	255	/* set default policy and cpuinfo */
9e2697ff	256	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
9e2697ff	257
592eb999 RJ	258	/* Generate pxa25x the run cpufreq_frequency_table struct */
592eb999 RJ	259	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
9e2697ff	260	pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
50701588	261	pxa255_run_freq_table[i].driver_data = i;
9e2697ff	262	}
9e2697ff	263	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
592eb999 RJ	264
	265	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
	266	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
3679389b RJ	267	pxa255_turbo_freq_table[i].frequency =
3679389b RJ	268	pxa255_turbo_freqs[i].khz;
50701588	269	pxa255_turbo_freq_table[i].driver_data = i;
9e2697ff RK	270	}
	271	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
	272
65587f7d MZ	273	pxa255_turbo_table = !!pxa255_turbo_table;
65587f7d MZ	274
592eb999 RJ	275	/* Generate the pxa27x cpufreq_frequency_table struct */
	276	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
	277	freq = pxa27x_freqs[i].khz;
	278	if (freq > pxa27x_maxfreq)
	279	break;
	280	pxa27x_freq_table[i].frequency = freq;
50701588	281	pxa27x_freq_table[i].driver_data = i;
592eb999	282	}
50701588	283	pxa27x_freq_table[i].driver_data = i;
592eb999 RJ	284	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
	285
	286	/*
	287	* Set the policy's minimum and maximum frequencies from the tables
	288	* just constructed. This sets cpuinfo.mxx_freq, min and max.
	289	*/
65587f7d MZ	290	if (cpu_is_pxa25x()) {
65587f7d MZ	291	find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
1c5864e2	292	pr_info("using %s frequency table\n",
65587f7d	293	pxa255_turbo_table ? "turbo" : "run");
6a77a1e6	294
8ed5a219	295	policy->freq_table = pxa255_freq_table;
65587f7d	296	}
6a77a1e6	297	else if (cpu_is_pxa27x()) {
8ed5a219	298	policy->freq_table = pxa27x_freq_table;
6a77a1e6	299	}
592eb999	300
1c5864e2	301	pr_info("frequency change support initialized\n");
9e2697ff RK	302
	303	return 0;
	304	}
	305
	306	static struct cpufreq_driver pxa_cpufreq_driver = {
ae6b4271	307	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
bf36e48d	308	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	309	.target_index = pxa_set_target,
9e2697ff	310	.init = pxa_cpufreq_init,
ea833f0b	311	.get = pxa_cpufreq_get,
592eb999	312	.name = "PXA2xx",
d9278077	313	.driver_data = &pxa_cpufreq_data,
9e2697ff RK	314	};
	315
	316	static int __init pxa_cpu_init(void)
	317	{
	318	int ret = -ENODEV;
d9278077 RJ	319
	320	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
	321	if (IS_ERR(pxa_cpufreq_data.clk_core))
	322	return PTR_ERR(pxa_cpufreq_data.clk_core);
	323
592eb999	324	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x())
9e2697ff RK	325	ret = cpufreq_register_driver(&pxa_cpufreq_driver);
	326	return ret;
	327	}
	328
	329	static void __exit pxa_cpu_exit(void)
	330	{
592eb999	331	cpufreq_unregister_driver(&pxa_cpufreq_driver);
9e2697ff RK	332	}
	333
	334
3679389b RJ	335	MODULE_AUTHOR("Intrinsyc Software Inc.");
3679389b RJ	336	MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
9e2697ff RK	337	MODULE_LICENSE("GPL");
	338	module_init(pxa_cpu_init);
	339	module_exit(pxa_cpu_exit);