cpufreq: CPPC: Migrate to ->exit() callback instead of ->stop_cpu()
[linux-block.git] / drivers / cpufreq / powernv-cpufreq.c
CommitLineData
3e0a4e85 1// SPDX-License-Identifier: GPL-2.0-or-later
b3d627a5
VS
2/*
3 * POWERNV cpufreq driver for the IBM POWER processors
4 *
5 * (C) Copyright IBM 2014
6 *
7 * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
b3d627a5
VS
8 */
9
10#define pr_fmt(fmt) "powernv-cpufreq: " fmt
11
12#include <linux/kernel.h>
13#include <linux/sysfs.h>
14#include <linux/cpumask.h>
15#include <linux/module.h>
16#include <linux/cpufreq.h>
17#include <linux/smp.h>
18#include <linux/of.h>
cf30af76 19#include <linux/reboot.h>
053819e0 20#include <linux/slab.h>
6d167a44 21#include <linux/cpu.h>
332f0a01 22#include <linux/hashtable.h>
c89f2682 23#include <trace/events/power.h>
b3d627a5
VS
24
25#include <asm/cputhreads.h>
6174bac8 26#include <asm/firmware.h>
b3d627a5 27#include <asm/reg.h>
f3cae355 28#include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
cb166fa9 29#include <asm/opal.h>
eaa2c3ae 30#include <linux/timer.h>
b3d627a5 31
332f0a01
GS
32#define POWERNV_MAX_PSTATES_ORDER 8
33#define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER))
09a972d1
SB
34#define PMSR_PSAFE_ENABLE (1UL << 30)
35#define PMSR_SPR_EM_DISABLE (1UL << 31)
ee1f4a7d 36#define MAX_PSTATE_SHIFT 32
20b15b76
AA
37#define LPSTATE_SHIFT 48
38#define GPSTATE_SHIFT 56
b3d627a5 39
eaa2c3ae
AA
40#define MAX_RAMP_DOWN_TIME 5120
41/*
42 * On an idle system we want the global pstate to ramp-down from max value to
43 * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
44 * then ramp-down rapidly later on.
45 *
46 * This gives a percentage rampdown for time elapsed in milliseconds.
47 * ramp_down_percentage = ((ms * ms) >> 18)
48 * ~= 3.8 * (sec * sec)
49 *
50 * At 0 ms ramp_down_percent = 0
51 * At 5120 ms ramp_down_percent = 100
52 */
53#define ramp_down_percent(time) ((time * time) >> 18)
54
55/* Interval after which the timer is queued to bring down global pstate */
56#define GPSTATE_TIMER_INTERVAL 2000
57
58/**
59 * struct global_pstate_info - Per policy data structure to maintain history of
60 * global pstates
09ca4c9b
AA
61 * @highest_lpstate_idx: The local pstate index from which we are
62 * ramping down
eaa2c3ae 63 * @elapsed_time: Time in ms spent in ramping down from
09ca4c9b 64 * highest_lpstate_idx
eaa2c3ae
AA
65 * @last_sampled_time: Time from boot in ms when global pstates were
66 * last set
44bd9a30
LJ
67 * @last_lpstate_idx: Last set value of local pstate and global
68 * @last_gpstate_idx: pstate in terms of cpufreq table index
eaa2c3ae
AA
69 * @timer: Is used for ramping down if cpu goes idle for
70 * a long time with global pstate held high
71 * @gpstate_lock: A spinlock to maintain synchronization between
72 * routines called by the timer handler and
73 * governer's target_index calls
44bd9a30 74 * @policy: Associated CPUFreq policy
eaa2c3ae
AA
75 */
76struct global_pstate_info {
09ca4c9b 77 int highest_lpstate_idx;
eaa2c3ae
AA
78 unsigned int elapsed_time;
79 unsigned int last_sampled_time;
09ca4c9b
AA
80 int last_lpstate_idx;
81 int last_gpstate_idx;
eaa2c3ae
AA
82 spinlock_t gpstate_lock;
83 struct timer_list timer;
1d1fe902 84 struct cpufreq_policy *policy;
eaa2c3ae
AA
85};
86
b3d627a5 87static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
332f0a01 88
133c6c84 89static DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER);
332f0a01
GS
90/**
91 * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap
92 * indexed by a function of pstate id.
93 *
94 * @pstate_id: pstate id for this entry.
95 *
96 * @cpufreq_table_idx: Index into the powernv_freqs
97 * cpufreq_frequency_table for frequency
98 * corresponding to pstate_id.
99 *
100 * @hentry: hlist_node that hooks this entry into the pstate_revmap
101 * hashtable
102 */
103struct pstate_idx_revmap_data {
967b87fd 104 u8 pstate_id;
332f0a01
GS
105 unsigned int cpufreq_table_idx;
106 struct hlist_node hentry;
107};
108
cb166fa9 109static bool rebooting, throttled, occ_reset;
b3d627a5 110
c89f2682
SB
111static const char * const throttle_reason[] = {
112 "No throttling",
113 "Power Cap",
114 "Processor Over Temperature",
115 "Power Supply Failure",
116 "Over Current",
117 "OCC Reset"
118};
119
1b028984
SB
120enum throttle_reason_type {
121 NO_THROTTLE = 0,
122 POWERCAP,
123 CPU_OVERTEMP,
124 POWER_SUPPLY_FAILURE,
125 OVERCURRENT,
126 OCC_RESET_THROTTLE,
127 OCC_MAX_REASON
128};
129
053819e0
SB
130static struct chip {
131 unsigned int id;
132 bool throttled;
c89f2682
SB
133 bool restore;
134 u8 throttle_reason;
735366fc
SB
135 cpumask_t mask;
136 struct work_struct throttle;
1b028984
SB
137 int throttle_turbo;
138 int throttle_sub_turbo;
139 int reason[OCC_MAX_REASON];
053819e0
SB
140} *chips;
141
142static int nr_chips;
3e5963bc 143static DEFINE_PER_CPU(struct chip *, chip_info);
053819e0 144
b3d627a5 145/*
09ca4c9b
AA
146 * Note:
147 * The set of pstates consists of contiguous integers.
148 * powernv_pstate_info stores the index of the frequency table for
149 * max, min and nominal frequencies. It also stores number of
150 * available frequencies.
b3d627a5 151 *
09ca4c9b
AA
152 * powernv_pstate_info.nominal indicates the index to the highest
153 * non-turbo frequency.
b3d627a5
VS
154 */
155static struct powernv_pstate_info {
09ca4c9b
AA
156 unsigned int min;
157 unsigned int max;
158 unsigned int nominal;
159 unsigned int nr_pstates;
b12f7a2b 160 bool wof_enabled;
b3d627a5
VS
161} powernv_pstate_info;
162
967b87fd 163static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift)
ee1f4a7d 164{
967b87fd 165 return ((pmsr_val >> shift) & 0xFF);
ee1f4a7d
GS
166}
167
168#define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT)
169#define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT)
170#define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT)
171
332f0a01
GS
172/* Use following functions for conversions between pstate_id and index */
173
44bd9a30 174/*
332f0a01
GS
175 * idx_to_pstate : Returns the pstate id corresponding to the
176 * frequency in the cpufreq frequency table
177 * powernv_freqs indexed by @i.
178 *
179 * If @i is out of bound, this will return the pstate
180 * corresponding to the nominal frequency.
181 */
967b87fd 182static inline u8 idx_to_pstate(unsigned int i)
09ca4c9b 183{
8e859467 184 if (unlikely(i >= powernv_pstate_info.nr_pstates)) {
332f0a01 185 pr_warn_once("idx_to_pstate: index %u is out of bound\n", i);
8e859467
AA
186 return powernv_freqs[powernv_pstate_info.nominal].driver_data;
187 }
188
09ca4c9b
AA
189 return powernv_freqs[i].driver_data;
190}
191
44bd9a30 192/*
332f0a01
GS
193 * pstate_to_idx : Returns the index in the cpufreq frequencytable
194 * powernv_freqs for the frequency whose corresponding
195 * pstate id is @pstate.
196 *
197 * If no frequency corresponding to @pstate is found,
198 * this will return the index of the nominal
199 * frequency.
200 */
967b87fd 201static unsigned int pstate_to_idx(u8 pstate)
09ca4c9b 202{
332f0a01
GS
203 unsigned int key = pstate % POWERNV_MAX_PSTATES;
204 struct pstate_idx_revmap_data *revmap_data;
8e859467 205
332f0a01
GS
206 hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) {
207 if (revmap_data->pstate_id == pstate)
208 return revmap_data->cpufreq_table_idx;
8e859467 209 }
332f0a01 210
967b87fd 211 pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate);
332f0a01 212 return powernv_pstate_info.nominal;
09ca4c9b
AA
213}
214
eaa2c3ae
AA
215static inline void reset_gpstates(struct cpufreq_policy *policy)
216{
217 struct global_pstate_info *gpstates = policy->driver_data;
218
09ca4c9b 219 gpstates->highest_lpstate_idx = 0;
eaa2c3ae
AA
220 gpstates->elapsed_time = 0;
221 gpstates->last_sampled_time = 0;
09ca4c9b
AA
222 gpstates->last_lpstate_idx = 0;
223 gpstates->last_gpstate_idx = 0;
eaa2c3ae
AA
224}
225
b3d627a5
VS
226/*
227 * Initialize the freq table based on data obtained
228 * from the firmware passed via device-tree
229 */
230static int init_powernv_pstates(void)
231{
232 struct device_node *power_mgt;
09ca4c9b 233 int i, nr_pstates = 0;
b3d627a5
VS
234 const __be32 *pstate_ids, *pstate_freqs;
235 u32 len_ids, len_freqs;
09ca4c9b 236 u32 pstate_min, pstate_max, pstate_nominal;
b12f7a2b 237 u32 pstate_turbo, pstate_ultra_turbo;
5ae06c23 238 int rc = -ENODEV;
b3d627a5
VS
239
240 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
241 if (!power_mgt) {
242 pr_warn("power-mgt node not found\n");
243 return -ENODEV;
244 }
245
246 if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
247 pr_warn("ibm,pstate-min node not found\n");
3be466d6 248 goto out;
b3d627a5
VS
249 }
250
251 if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
252 pr_warn("ibm,pstate-max node not found\n");
3be466d6 253 goto out;
b3d627a5
VS
254 }
255
256 if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
257 &pstate_nominal)) {
258 pr_warn("ibm,pstate-nominal not found\n");
3be466d6 259 goto out;
b3d627a5 260 }
b12f7a2b
SB
261
262 if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo",
263 &pstate_ultra_turbo)) {
264 powernv_pstate_info.wof_enabled = false;
265 goto next;
266 }
267
268 if (of_property_read_u32(power_mgt, "ibm,pstate-turbo",
269 &pstate_turbo)) {
270 powernv_pstate_info.wof_enabled = false;
271 goto next;
272 }
273
274 if (pstate_turbo == pstate_ultra_turbo)
275 powernv_pstate_info.wof_enabled = false;
276 else
277 powernv_pstate_info.wof_enabled = true;
278
279next:
967b87fd 280 pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min,
b3d627a5 281 pstate_nominal, pstate_max);
b12f7a2b
SB
282 pr_info("Workload Optimized Frequency is %s in the platform\n",
283 (powernv_pstate_info.wof_enabled) ? "enabled" : "disabled");
b3d627a5
VS
284
285 pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
286 if (!pstate_ids) {
287 pr_warn("ibm,pstate-ids not found\n");
3be466d6 288 goto out;
b3d627a5
VS
289 }
290
291 pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
292 &len_freqs);
293 if (!pstate_freqs) {
294 pr_warn("ibm,pstate-frequencies-mhz not found\n");
3be466d6 295 goto out;
b3d627a5
VS
296 }
297
6174bac8
VS
298 if (len_ids != len_freqs) {
299 pr_warn("Entries in ibm,pstate-ids and "
300 "ibm,pstate-frequencies-mhz does not match\n");
301 }
302
b3d627a5
VS
303 nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
304 if (!nr_pstates) {
305 pr_warn("No PStates found\n");
3be466d6 306 goto out;
b3d627a5
VS
307 }
308
09ca4c9b 309 powernv_pstate_info.nr_pstates = nr_pstates;
b3d627a5 310 pr_debug("NR PStates %d\n", nr_pstates);
ee1f4a7d 311
b3d627a5
VS
312 for (i = 0; i < nr_pstates; i++) {
313 u32 id = be32_to_cpu(pstate_ids[i]);
314 u32 freq = be32_to_cpu(pstate_freqs[i]);
332f0a01
GS
315 struct pstate_idx_revmap_data *revmap_data;
316 unsigned int key;
b3d627a5
VS
317
318 pr_debug("PState id %d freq %d MHz\n", id, freq);
319 powernv_freqs[i].frequency = freq * 1000; /* kHz */
967b87fd 320 powernv_freqs[i].driver_data = id & 0xFF;
09ca4c9b 321
5ae06c23
YL
322 revmap_data = kmalloc(sizeof(*revmap_data), GFP_KERNEL);
323 if (!revmap_data) {
324 rc = -ENOMEM;
325 goto out;
326 }
332f0a01 327
967b87fd 328 revmap_data->pstate_id = id & 0xFF;
332f0a01 329 revmap_data->cpufreq_table_idx = i;
967b87fd 330 key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES;
332f0a01
GS
331 hash_add(pstate_revmap, &revmap_data->hentry, key);
332
09ca4c9b
AA
333 if (id == pstate_max)
334 powernv_pstate_info.max = i;
3fa4680b 335 if (id == pstate_nominal)
09ca4c9b 336 powernv_pstate_info.nominal = i;
3fa4680b 337 if (id == pstate_min)
09ca4c9b 338 powernv_pstate_info.min = i;
b12f7a2b
SB
339
340 if (powernv_pstate_info.wof_enabled && id == pstate_turbo) {
341 int j;
342
343 for (j = i - 1; j >= (int)powernv_pstate_info.max; j--)
344 powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ;
345 }
b3d627a5 346 }
09ca4c9b 347
b3d627a5
VS
348 /* End of list marker entry */
349 powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
3be466d6
YL
350
351 of_node_put(power_mgt);
b3d627a5 352 return 0;
3be466d6
YL
353out:
354 of_node_put(power_mgt);
5ae06c23 355 return rc;
b3d627a5
VS
356}
357
358/* Returns the CPU frequency corresponding to the pstate_id. */
967b87fd 359static unsigned int pstate_id_to_freq(u8 pstate_id)
b3d627a5
VS
360{
361 int i;
362
09ca4c9b 363 i = pstate_to_idx(pstate_id);
6174bac8 364 if (i >= powernv_pstate_info.nr_pstates || i < 0) {
967b87fd 365 pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n",
09ca4c9b
AA
366 pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
367 i = powernv_pstate_info.nominal;
6174bac8 368 }
b3d627a5
VS
369
370 return powernv_freqs[i].frequency;
371}
372
373/*
374 * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
375 * the firmware
376 */
377static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
378 char *buf)
379{
380 return sprintf(buf, "%u\n",
09ca4c9b 381 powernv_freqs[powernv_pstate_info.nominal].frequency);
b3d627a5
VS
382}
383
133c6c84 384static struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
b3d627a5
VS
385 __ATTR_RO(cpuinfo_nominal_freq);
386
b12f7a2b
SB
387#define SCALING_BOOST_FREQS_ATTR_INDEX 2
388
b3d627a5
VS
389static struct freq_attr *powernv_cpu_freq_attr[] = {
390 &cpufreq_freq_attr_scaling_available_freqs,
391 &cpufreq_freq_attr_cpuinfo_nominal_freq,
b12f7a2b 392 &cpufreq_freq_attr_scaling_boost_freqs,
b3d627a5
VS
393 NULL,
394};
395
1b028984
SB
396#define throttle_attr(name, member) \
397static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
398{ \
399 struct chip *chip = per_cpu(chip_info, policy->cpu); \
400 \
401 return sprintf(buf, "%u\n", chip->member); \
402} \
403 \
404static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
405
406throttle_attr(unthrottle, reason[NO_THROTTLE]);
407throttle_attr(powercap, reason[POWERCAP]);
408throttle_attr(overtemp, reason[CPU_OVERTEMP]);
409throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
410throttle_attr(overcurrent, reason[OVERCURRENT]);
411throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
412throttle_attr(turbo_stat, throttle_turbo);
413throttle_attr(sub_turbo_stat, throttle_sub_turbo);
414
415static struct attribute *throttle_attrs[] = {
416 &throttle_attr_unthrottle.attr,
417 &throttle_attr_powercap.attr,
418 &throttle_attr_overtemp.attr,
419 &throttle_attr_supply_fault.attr,
420 &throttle_attr_overcurrent.attr,
421 &throttle_attr_occ_reset.attr,
422 &throttle_attr_turbo_stat.attr,
423 &throttle_attr_sub_turbo_stat.attr,
424 NULL,
425};
426
427static const struct attribute_group throttle_attr_grp = {
428 .name = "throttle_stats",
429 .attrs = throttle_attrs,
430};
431
b3d627a5
VS
432/* Helper routines */
433
434/* Access helpers to power mgt SPR */
435
436static inline unsigned long get_pmspr(unsigned long sprn)
437{
438 switch (sprn) {
439 case SPRN_PMCR:
440 return mfspr(SPRN_PMCR);
441
442 case SPRN_PMICR:
443 return mfspr(SPRN_PMICR);
444
445 case SPRN_PMSR:
446 return mfspr(SPRN_PMSR);
447 }
448 BUG();
449}
450
451static inline void set_pmspr(unsigned long sprn, unsigned long val)
452{
453 switch (sprn) {
454 case SPRN_PMCR:
455 mtspr(SPRN_PMCR, val);
456 return;
457
458 case SPRN_PMICR:
459 mtspr(SPRN_PMICR, val);
460 return;
461 }
462 BUG();
463}
464
465/*
466 * Use objects of this type to query/update
467 * pstates on a remote CPU via smp_call_function.
468 */
469struct powernv_smp_call_data {
470 unsigned int freq;
967b87fd
GS
471 u8 pstate_id;
472 u8 gpstate_id;
b3d627a5
VS
473};
474
475/*
476 * powernv_read_cpu_freq: Reads the current frequency on this CPU.
477 *
478 * Called via smp_call_function.
479 *
480 * Note: The caller of the smp_call_function should pass an argument of
481 * the type 'struct powernv_smp_call_data *' along with this function.
482 *
483 * The current frequency on this CPU will be returned via
484 * ((struct powernv_smp_call_data *)arg)->freq;
485 */
486static void powernv_read_cpu_freq(void *arg)
487{
488 unsigned long pmspr_val;
b3d627a5
VS
489 struct powernv_smp_call_data *freq_data = arg;
490
491 pmspr_val = get_pmspr(SPRN_PMSR);
ee1f4a7d 492 freq_data->pstate_id = extract_local_pstate(pmspr_val);
b3d627a5
VS
493 freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
494
967b87fd
GS
495 pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n",
496 raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
497 freq_data->freq);
b3d627a5
VS
498}
499
500/*
501 * powernv_cpufreq_get: Returns the CPU frequency as reported by the
502 * firmware for CPU 'cpu'. This value is reported through the sysfs
503 * file cpuinfo_cur_freq.
504 */
60d1ea4e 505static unsigned int powernv_cpufreq_get(unsigned int cpu)
b3d627a5
VS
506{
507 struct powernv_smp_call_data freq_data;
508
509 smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
510 &freq_data, 1);
511
512 return freq_data.freq;
513}
514
515/*
516 * set_pstate: Sets the pstate on this CPU.
517 *
518 * This is called via an smp_call_function.
519 *
520 * The caller must ensure that freq_data is of the type
521 * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
522 * on this CPU should be present in freq_data->pstate_id.
523 */
eaa2c3ae 524static void set_pstate(void *data)
b3d627a5
VS
525{
526 unsigned long val;
eaa2c3ae
AA
527 struct powernv_smp_call_data *freq_data = data;
528 unsigned long pstate_ul = freq_data->pstate_id;
529 unsigned long gpstate_ul = freq_data->gpstate_id;
b3d627a5
VS
530
531 val = get_pmspr(SPRN_PMCR);
532 val = val & 0x0000FFFFFFFFFFFFULL;
533
534 pstate_ul = pstate_ul & 0xFF;
eaa2c3ae 535 gpstate_ul = gpstate_ul & 0xFF;
b3d627a5
VS
536
537 /* Set both global(bits 56..63) and local(bits 48..55) PStates */
eaa2c3ae 538 val = val | (gpstate_ul << 56) | (pstate_ul << 48);
b3d627a5
VS
539
540 pr_debug("Setting cpu %d pmcr to %016lX\n",
541 raw_smp_processor_id(), val);
542 set_pmspr(SPRN_PMCR, val);
543}
544
cf30af76
SB
545/*
546 * get_nominal_index: Returns the index corresponding to the nominal
547 * pstate in the cpufreq table
548 */
549static inline unsigned int get_nominal_index(void)
550{
09ca4c9b 551 return powernv_pstate_info.nominal;
cf30af76
SB
552}
553
735366fc 554static void powernv_cpufreq_throttle_check(void *data)
09a972d1 555{
3e5963bc 556 struct chip *chip;
735366fc 557 unsigned int cpu = smp_processor_id();
09a972d1 558 unsigned long pmsr;
967b87fd 559 u8 pmsr_pmax;
09ca4c9b 560 unsigned int pmsr_pmax_idx;
09a972d1
SB
561
562 pmsr = get_pmspr(SPRN_PMSR);
3e5963bc 563 chip = this_cpu_read(chip_info);
053819e0 564
09a972d1 565 /* Check for Pmax Capping */
ee1f4a7d 566 pmsr_pmax = extract_max_pstate(pmsr);
09ca4c9b
AA
567 pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
568 if (pmsr_pmax_idx != powernv_pstate_info.max) {
3e5963bc 569 if (chip->throttled)
053819e0 570 goto next;
3e5963bc 571 chip->throttled = true;
09ca4c9b 572 if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
967b87fd 573 pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n",
3e5963bc 574 cpu, chip->id, pmsr_pmax,
09ca4c9b 575 idx_to_pstate(powernv_pstate_info.nominal));
1b028984
SB
576 chip->throttle_sub_turbo++;
577 } else {
578 chip->throttle_turbo++;
579 }
3e5963bc
MN
580 trace_powernv_throttle(chip->id,
581 throttle_reason[chip->throttle_reason],
c89f2682 582 pmsr_pmax);
3e5963bc
MN
583 } else if (chip->throttled) {
584 chip->throttled = false;
585 trace_powernv_throttle(chip->id,
586 throttle_reason[chip->throttle_reason],
c89f2682 587 pmsr_pmax);
09a972d1
SB
588 }
589
3dd3ebe5 590 /* Check if Psafe_mode_active is set in PMSR. */
053819e0 591next:
3dd3ebe5 592 if (pmsr & PMSR_PSAFE_ENABLE) {
09a972d1
SB
593 throttled = true;
594 pr_info("Pstate set to safe frequency\n");
595 }
596
597 /* Check if SPR_EM_DISABLE is set in PMSR */
598 if (pmsr & PMSR_SPR_EM_DISABLE) {
599 throttled = true;
600 pr_info("Frequency Control disabled from OS\n");
601 }
602
603 if (throttled) {
604 pr_info("PMSR = %16lx\n", pmsr);
c89f2682 605 pr_warn("CPU Frequency could be throttled\n");
09a972d1
SB
606 }
607}
608
eaa2c3ae
AA
609/**
610 * calc_global_pstate - Calculate global pstate
09ca4c9b
AA
611 * @elapsed_time: Elapsed time in milliseconds
612 * @local_pstate_idx: New local pstate
613 * @highest_lpstate_idx: pstate from which its ramping down
eaa2c3ae
AA
614 *
615 * Finds the appropriate global pstate based on the pstate from which its
616 * ramping down and the time elapsed in ramping down. It follows a quadratic
617 * equation which ensures that it reaches ramping down to pmin in 5sec.
618 */
619static inline int calc_global_pstate(unsigned int elapsed_time,
09ca4c9b
AA
620 int highest_lpstate_idx,
621 int local_pstate_idx)
eaa2c3ae 622{
09ca4c9b 623 int index_diff;
eaa2c3ae
AA
624
625 /*
626 * Using ramp_down_percent we get the percentage of rampdown
627 * that we are expecting to be dropping. Difference between
09ca4c9b 628 * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
eaa2c3ae
AA
629 * number of how many pstates we will drop eventually by the end of
630 * 5 seconds, then just scale it get the number pstates to be dropped.
631 */
09ca4c9b
AA
632 index_diff = ((int)ramp_down_percent(elapsed_time) *
633 (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
eaa2c3ae
AA
634
635 /* Ensure that global pstate is >= to local pstate */
09ca4c9b
AA
636 if (highest_lpstate_idx + index_diff >= local_pstate_idx)
637 return local_pstate_idx;
eaa2c3ae 638 else
09ca4c9b 639 return highest_lpstate_idx + index_diff;
eaa2c3ae
AA
640}
641
642static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
643{
644 unsigned int timer_interval;
645
646 /*
647 * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
648 * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
649 * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
650 * seconds of ramp down time.
651 */
652 if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
653 > MAX_RAMP_DOWN_TIME)
654 timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
655 else
656 timer_interval = GPSTATE_TIMER_INTERVAL;
657
7bc54b65 658 mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
eaa2c3ae
AA
659}
660
661/**
662 * gpstate_timer_handler
663 *
44bd9a30 664 * @t: Timer context used to fetch global pstate info struct
eaa2c3ae
AA
665 *
666 * This handler brings down the global pstate closer to the local pstate
667 * according quadratic equation. Queues a new timer if it is still not equal
668 * to local pstate
669 */
133c6c84 670static void gpstate_timer_handler(struct timer_list *t)
eaa2c3ae 671{
1d1fe902
KC
672 struct global_pstate_info *gpstates = from_timer(gpstates, t, timer);
673 struct cpufreq_policy *policy = gpstates->policy;
20b15b76
AA
674 int gpstate_idx, lpstate_idx;
675 unsigned long val;
eaa2c3ae
AA
676 unsigned int time_diff = jiffies_to_msecs(jiffies)
677 - gpstates->last_sampled_time;
678 struct powernv_smp_call_data freq_data;
679
680 if (!spin_trylock(&gpstates->gpstate_lock))
681 return;
c0f7f5b6
SB
682 /*
683 * If the timer has migrated to the different cpu then bring
684 * it back to one of the policy->cpus
685 */
686 if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) {
687 gpstates->timer.expires = jiffies + msecs_to_jiffies(1);
688 add_timer_on(&gpstates->timer, cpumask_first(policy->cpus));
689 spin_unlock(&gpstates->gpstate_lock);
690 return;
691 }
eaa2c3ae 692
20b15b76
AA
693 /*
694 * If PMCR was last updated was using fast_swtich then
695 * We may have wrong in gpstate->last_lpstate_idx
696 * value. Hence, read from PMCR to get correct data.
697 */
698 val = get_pmspr(SPRN_PMCR);
ee1f4a7d
GS
699 freq_data.gpstate_id = extract_global_pstate(val);
700 freq_data.pstate_id = extract_local_pstate(val);
20b15b76
AA
701 if (freq_data.gpstate_id == freq_data.pstate_id) {
702 reset_gpstates(policy);
703 spin_unlock(&gpstates->gpstate_lock);
704 return;
705 }
706
eaa2c3ae
AA
707 gpstates->last_sampled_time += time_diff;
708 gpstates->elapsed_time += time_diff;
eaa2c3ae 709
20b15b76 710 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
09ca4c9b 711 gpstate_idx = pstate_to_idx(freq_data.pstate_id);
c9a81e68 712 lpstate_idx = gpstate_idx;
eaa2c3ae 713 reset_gpstates(policy);
09ca4c9b 714 gpstates->highest_lpstate_idx = gpstate_idx;
eaa2c3ae 715 } else {
20b15b76 716 lpstate_idx = pstate_to_idx(freq_data.pstate_id);
09ca4c9b
AA
717 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
718 gpstates->highest_lpstate_idx,
20b15b76 719 lpstate_idx);
eaa2c3ae 720 }
20b15b76
AA
721 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
722 gpstates->last_gpstate_idx = gpstate_idx;
723 gpstates->last_lpstate_idx = lpstate_idx;
eaa2c3ae
AA
724 /*
725 * If local pstate is equal to global pstate, rampdown is over
726 * So timer is not required to be queued.
727 */
09ca4c9b 728 if (gpstate_idx != gpstates->last_lpstate_idx)
eaa2c3ae
AA
729 queue_gpstate_timer(gpstates);
730
c0f7f5b6 731 set_pstate(&freq_data);
1fd3ff28 732 spin_unlock(&gpstates->gpstate_lock);
eaa2c3ae
AA
733}
734
b3d627a5
VS
735/*
736 * powernv_cpufreq_target_index: Sets the frequency corresponding to
737 * the cpufreq table entry indexed by new_index on the cpus in the
738 * mask policy->cpus
739 */
740static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
741 unsigned int new_index)
742{
743 struct powernv_smp_call_data freq_data;
09ca4c9b 744 unsigned int cur_msec, gpstate_idx;
eaa2c3ae 745 struct global_pstate_info *gpstates = policy->driver_data;
b3d627a5 746
cf30af76
SB
747 if (unlikely(rebooting) && new_index != get_nominal_index())
748 return 0;
749
8a10c06a
DK
750 if (!throttled) {
751 /* we don't want to be preempted while
752 * checking if the CPU frequency has been throttled
753 */
754 preempt_disable();
735366fc 755 powernv_cpufreq_throttle_check(NULL);
8a10c06a
DK
756 preempt_enable();
757 }
09a972d1 758
eaa2c3ae
AA
759 cur_msec = jiffies_to_msecs(get_jiffies_64());
760
09ca4c9b 761 freq_data.pstate_id = idx_to_pstate(new_index);
dcb14337
SB
762 if (!gpstates) {
763 freq_data.gpstate_id = freq_data.pstate_id;
764 goto no_gpstate;
765 }
766
767 spin_lock(&gpstates->gpstate_lock);
b3d627a5 768
eaa2c3ae 769 if (!gpstates->last_sampled_time) {
09ca4c9b
AA
770 gpstate_idx = new_index;
771 gpstates->highest_lpstate_idx = new_index;
eaa2c3ae
AA
772 goto gpstates_done;
773 }
774
09ca4c9b 775 if (gpstates->last_gpstate_idx < new_index) {
eaa2c3ae
AA
776 gpstates->elapsed_time += cur_msec -
777 gpstates->last_sampled_time;
778
779 /*
780 * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
781 * we should be resetting all global pstate related data. Set it
782 * equal to local pstate to start fresh.
783 */
784 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
785 reset_gpstates(policy);
09ca4c9b
AA
786 gpstates->highest_lpstate_idx = new_index;
787 gpstate_idx = new_index;
eaa2c3ae
AA
788 } else {
789 /* Elaspsed_time is less than 5 seconds, continue to rampdown */
09ca4c9b
AA
790 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
791 gpstates->highest_lpstate_idx,
792 new_index);
eaa2c3ae
AA
793 }
794 } else {
795 reset_gpstates(policy);
09ca4c9b
AA
796 gpstates->highest_lpstate_idx = new_index;
797 gpstate_idx = new_index;
eaa2c3ae
AA
798 }
799
800 /*
801 * If local pstate is equal to global pstate, rampdown is over
802 * So timer is not required to be queued.
803 */
09ca4c9b 804 if (gpstate_idx != new_index)
eaa2c3ae 805 queue_gpstate_timer(gpstates);
0bc10b93
AA
806 else
807 del_timer_sync(&gpstates->timer);
eaa2c3ae
AA
808
809gpstates_done:
09ca4c9b 810 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
eaa2c3ae 811 gpstates->last_sampled_time = cur_msec;
09ca4c9b
AA
812 gpstates->last_gpstate_idx = gpstate_idx;
813 gpstates->last_lpstate_idx = new_index;
eaa2c3ae 814
1fd3ff28
AA
815 spin_unlock(&gpstates->gpstate_lock);
816
dcb14337 817no_gpstate:
b3d627a5
VS
818 /*
819 * Use smp_call_function to send IPI and execute the
820 * mtspr on target CPU. We could do that without IPI
821 * if current CPU is within policy->cpus (core)
822 */
823 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
b3d627a5
VS
824 return 0;
825}
826
827static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
828{
bf14721c 829 int base, i;
2920e9ce 830 struct kernfs_node *kn;
eaa2c3ae 831 struct global_pstate_info *gpstates;
b3d627a5
VS
832
833 base = cpu_first_thread_sibling(policy->cpu);
834
835 for (i = 0; i < threads_per_core; i++)
836 cpumask_set_cpu(base + i, policy->cpus);
837
2920e9ce
SB
838 kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
839 if (!kn) {
1b028984
SB
840 int ret;
841
842 ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
843 if (ret) {
844 pr_info("Failed to create throttle stats directory for cpu %d\n",
845 policy->cpu);
846 return ret;
847 }
2920e9ce
SB
848 } else {
849 kernfs_put(kn);
1b028984 850 }
eaa2c3ae 851
dcb14337
SB
852 policy->freq_table = powernv_freqs;
853 policy->fast_switch_possible = true;
854
855 if (pvr_version_is(PVR_POWER9))
856 return 0;
857
858 /* Initialise Gpstate ramp-down timer only on POWER8 */
eaa2c3ae
AA
859 gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL);
860 if (!gpstates)
861 return -ENOMEM;
862
863 policy->driver_data = gpstates;
864
865 /* initialize timer */
1d1fe902
KC
866 gpstates->policy = policy;
867 timer_setup(&gpstates->timer, gpstate_timer_handler,
868 TIMER_PINNED | TIMER_DEFERRABLE);
eaa2c3ae
AA
869 gpstates->timer.expires = jiffies +
870 msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
871 spin_lock_init(&gpstates->gpstate_lock);
eaa2c3ae 872
bf14721c 873 return 0;
eaa2c3ae
AA
874}
875
876static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
877{
878 /* timer is deleted in cpufreq_cpu_stop() */
879 kfree(policy->driver_data);
880
881 return 0;
b3d627a5
VS
882}
883
cf30af76
SB
884static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
885 unsigned long action, void *unused)
886{
887 int cpu;
a2d0230b 888 struct cpufreq_policy *cpu_policy;
cf30af76
SB
889
890 rebooting = true;
891 for_each_online_cpu(cpu) {
a2d0230b
SD
892 cpu_policy = cpufreq_cpu_get(cpu);
893 if (!cpu_policy)
894 continue;
895 powernv_cpufreq_target_index(cpu_policy, get_nominal_index());
896 cpufreq_cpu_put(cpu_policy);
cf30af76
SB
897 }
898
899 return NOTIFY_DONE;
900}
901
902static struct notifier_block powernv_cpufreq_reboot_nb = {
903 .notifier_call = powernv_cpufreq_reboot_notifier,
904};
905
133c6c84 906static void powernv_cpufreq_work_fn(struct work_struct *work)
735366fc
SB
907{
908 struct chip *chip = container_of(work, struct chip, throttle);
d95fe371 909 struct cpufreq_policy *policy;
22794280 910 unsigned int cpu;
6d167a44 911 cpumask_t mask;
735366fc 912
6d167a44
SB
913 get_online_cpus();
914 cpumask_and(&mask, &chip->mask, cpu_online_mask);
915 smp_call_function_any(&mask,
735366fc 916 powernv_cpufreq_throttle_check, NULL, 0);
22794280
SB
917
918 if (!chip->restore)
6d167a44 919 goto out;
22794280
SB
920
921 chip->restore = false;
6d167a44
SB
922 for_each_cpu(cpu, &mask) {
923 int index;
22794280 924
d95fe371
PRS
925 policy = cpufreq_cpu_get(cpu);
926 if (!policy)
927 continue;
928 index = cpufreq_table_find_index_c(policy, policy->cur);
929 powernv_cpufreq_target_index(policy, index);
930 cpumask_andnot(&mask, &mask, policy->cpus);
931 cpufreq_cpu_put(policy);
22794280 932 }
6d167a44
SB
933out:
934 put_online_cpus();
735366fc
SB
935}
936
cb166fa9
SB
937static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
938 unsigned long msg_type, void *_msg)
939{
940 struct opal_msg *msg = _msg;
941 struct opal_occ_msg omsg;
735366fc 942 int i;
cb166fa9
SB
943
944 if (msg_type != OPAL_MSG_OCC)
945 return 0;
946
947 omsg.type = be64_to_cpu(msg->params[0]);
948
949 switch (omsg.type) {
950 case OCC_RESET:
951 occ_reset = true;
309d0631 952 pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
cb166fa9
SB
953 /*
954 * powernv_cpufreq_throttle_check() is called in
955 * target() callback which can detect the throttle state
956 * for governors like ondemand.
957 * But static governors will not call target() often thus
958 * report throttling here.
959 */
960 if (!throttled) {
961 throttled = true;
c89f2682 962 pr_warn("CPU frequency is throttled for duration\n");
cb166fa9 963 }
309d0631 964
cb166fa9
SB
965 break;
966 case OCC_LOAD:
309d0631 967 pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
cb166fa9
SB
968 break;
969 case OCC_THROTTLE:
970 omsg.chip = be64_to_cpu(msg->params[1]);
971 omsg.throttle_status = be64_to_cpu(msg->params[2]);
972
973 if (occ_reset) {
974 occ_reset = false;
975 throttled = false;
309d0631 976 pr_info("OCC Active, CPU frequency is no longer throttled\n");
735366fc 977
22794280
SB
978 for (i = 0; i < nr_chips; i++) {
979 chips[i].restore = true;
735366fc 980 schedule_work(&chips[i].throttle);
22794280 981 }
735366fc 982
cb166fa9
SB
983 return 0;
984 }
985
c89f2682
SB
986 for (i = 0; i < nr_chips; i++)
987 if (chips[i].id == omsg.chip)
988 break;
989
990 if (omsg.throttle_status >= 0 &&
1b028984 991 omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
c89f2682 992 chips[i].throttle_reason = omsg.throttle_status;
1b028984
SB
993 chips[i].reason[omsg.throttle_status]++;
994 }
735366fc 995
c89f2682
SB
996 if (!omsg.throttle_status)
997 chips[i].restore = true;
998
999 schedule_work(&chips[i].throttle);
cb166fa9
SB
1000 }
1001 return 0;
1002}
1003
1004static struct notifier_block powernv_cpufreq_opal_nb = {
1005 .notifier_call = powernv_cpufreq_occ_msg,
1006 .next = NULL,
1007 .priority = 0,
1008};
1009
b120339c
PM
1010static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1011{
1012 struct powernv_smp_call_data freq_data;
eaa2c3ae 1013 struct global_pstate_info *gpstates = policy->driver_data;
b120339c 1014
09ca4c9b
AA
1015 freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
1016 freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
b120339c 1017 smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
dcb14337
SB
1018 if (gpstates)
1019 del_timer_sync(&gpstates->timer);
b120339c
PM
1020}
1021
60c9efb8
AA
1022static unsigned int powernv_fast_switch(struct cpufreq_policy *policy,
1023 unsigned int target_freq)
1024{
1025 int index;
1026 struct powernv_smp_call_data freq_data;
1027
1028 index = cpufreq_table_find_index_dl(policy, target_freq);
1029 freq_data.pstate_id = powernv_freqs[index].driver_data;
1030 freq_data.gpstate_id = powernv_freqs[index].driver_data;
1031 set_pstate(&freq_data);
1032
1033 return powernv_freqs[index].frequency;
1034}
1035
b3d627a5
VS
1036static struct cpufreq_driver powernv_cpufreq_driver = {
1037 .name = "powernv-cpufreq",
1038 .flags = CPUFREQ_CONST_LOOPS,
1039 .init = powernv_cpufreq_cpu_init,
eaa2c3ae 1040 .exit = powernv_cpufreq_cpu_exit,
b3d627a5
VS
1041 .verify = cpufreq_generic_frequency_table_verify,
1042 .target_index = powernv_cpufreq_target_index,
60c9efb8 1043 .fast_switch = powernv_fast_switch,
b3d627a5 1044 .get = powernv_cpufreq_get,
b120339c 1045 .stop_cpu = powernv_cpufreq_stop_cpu,
b3d627a5
VS
1046 .attr = powernv_cpu_freq_attr,
1047};
1048
053819e0
SB
1049static int init_chip_info(void)
1050{
db0d32d8 1051 unsigned int *chip;
053819e0
SB
1052 unsigned int cpu, i;
1053 unsigned int prev_chip_id = UINT_MAX;
db0d32d8
JH
1054 int ret = 0;
1055
1056 chip = kcalloc(num_possible_cpus(), sizeof(*chip), GFP_KERNEL);
1057 if (!chip)
1058 return -ENOMEM;
96c4726f 1059
3e5963bc 1060 for_each_possible_cpu(cpu) {
053819e0
SB
1061 unsigned int id = cpu_to_chip_id(cpu);
1062
1063 if (prev_chip_id != id) {
1064 prev_chip_id = id;
1065 chip[nr_chips++] = id;
1066 }
1067 }
1068
c89f2682 1069 chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
db0d32d8
JH
1070 if (!chips) {
1071 ret = -ENOMEM;
1072 goto free_and_return;
1073 }
053819e0
SB
1074
1075 for (i = 0; i < nr_chips; i++) {
1076 chips[i].id = chip[i];
735366fc
SB
1077 cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
1078 INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
3e5963bc
MN
1079 for_each_cpu(cpu, &chips[i].mask)
1080 per_cpu(chip_info, cpu) = &chips[i];
053819e0
SB
1081 }
1082
db0d32d8
JH
1083free_and_return:
1084 kfree(chip);
1085 return ret;
053819e0
SB
1086}
1087
c5e29ea7
SB
1088static inline void clean_chip_info(void)
1089{
d0a72efa
OH
1090 int i;
1091
1092 /* flush any pending work items */
1093 if (chips)
1094 for (i = 0; i < nr_chips; i++)
1095 cancel_work_sync(&chips[i].throttle);
c5e29ea7 1096 kfree(chips);
c5e29ea7
SB
1097}
1098
1099static inline void unregister_all_notifiers(void)
1100{
1101 opal_message_notifier_unregister(OPAL_MSG_OCC,
1102 &powernv_cpufreq_opal_nb);
1103 unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
1104}
1105
b3d627a5
VS
1106static int __init powernv_cpufreq_init(void)
1107{
1108 int rc = 0;
1109
6174bac8 1110 /* Don't probe on pseries (guest) platforms */
e4d54f71 1111 if (!firmware_has_feature(FW_FEATURE_OPAL))
6174bac8
VS
1112 return -ENODEV;
1113
b3d627a5
VS
1114 /* Discover pstates from device tree and init */
1115 rc = init_powernv_pstates();
c5e29ea7
SB
1116 if (rc)
1117 goto out;
b3d627a5 1118
053819e0
SB
1119 /* Populate chip info */
1120 rc = init_chip_info();
1121 if (rc)
c5e29ea7 1122 goto out;
053819e0 1123
b12f7a2b
SB
1124 if (powernv_pstate_info.wof_enabled)
1125 powernv_cpufreq_driver.boost_enabled = true;
1126 else
1127 powernv_cpu_freq_attr[SCALING_BOOST_FREQS_ATTR_INDEX] = NULL;
1128
c5e29ea7 1129 rc = cpufreq_register_driver(&powernv_cpufreq_driver);
b12f7a2b
SB
1130 if (rc) {
1131 pr_info("Failed to register the cpufreq driver (%d)\n", rc);
966c08de 1132 goto cleanup;
b12f7a2b 1133 }
c5e29ea7 1134
b12f7a2b
SB
1135 if (powernv_pstate_info.wof_enabled)
1136 cpufreq_enable_boost_support();
1137
966c08de
OH
1138 register_reboot_notifier(&powernv_cpufreq_reboot_nb);
1139 opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
1140
b12f7a2b 1141 return 0;
966c08de 1142cleanup:
c5e29ea7
SB
1143 clean_chip_info();
1144out:
1145 pr_info("Platform driver disabled. System does not support PState control\n");
1146 return rc;
b3d627a5
VS
1147}
1148module_init(powernv_cpufreq_init);
1149
1150static void __exit powernv_cpufreq_exit(void)
1151{
1152 cpufreq_unregister_driver(&powernv_cpufreq_driver);
c5e29ea7
SB
1153 unregister_all_notifiers();
1154 clean_chip_info();
b3d627a5
VS
1155}
1156module_exit(powernv_cpufreq_exit);
1157
1158MODULE_LICENSE("GPL");
1159MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");