Commit | Line | Data |
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b3d627a5 VS |
1 | /* |
2 | * POWERNV cpufreq driver for the IBM POWER processors | |
3 | * | |
4 | * (C) Copyright IBM 2014 | |
5 | * | |
6 | * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) "powernv-cpufreq: " fmt | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/sysfs.h> | |
24 | #include <linux/cpumask.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/cpufreq.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/of.h> | |
cf30af76 | 29 | #include <linux/reboot.h> |
053819e0 | 30 | #include <linux/slab.h> |
6d167a44 | 31 | #include <linux/cpu.h> |
332f0a01 | 32 | #include <linux/hashtable.h> |
c89f2682 | 33 | #include <trace/events/power.h> |
b3d627a5 VS |
34 | |
35 | #include <asm/cputhreads.h> | |
6174bac8 | 36 | #include <asm/firmware.h> |
b3d627a5 | 37 | #include <asm/reg.h> |
f3cae355 | 38 | #include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */ |
cb166fa9 | 39 | #include <asm/opal.h> |
eaa2c3ae | 40 | #include <linux/timer.h> |
b3d627a5 | 41 | |
332f0a01 GS |
42 | #define POWERNV_MAX_PSTATES_ORDER 8 |
43 | #define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER)) | |
09a972d1 SB |
44 | #define PMSR_PSAFE_ENABLE (1UL << 30) |
45 | #define PMSR_SPR_EM_DISABLE (1UL << 31) | |
ee1f4a7d | 46 | #define MAX_PSTATE_SHIFT 32 |
20b15b76 AA |
47 | #define LPSTATE_SHIFT 48 |
48 | #define GPSTATE_SHIFT 56 | |
b3d627a5 | 49 | |
eaa2c3ae AA |
50 | #define MAX_RAMP_DOWN_TIME 5120 |
51 | /* | |
52 | * On an idle system we want the global pstate to ramp-down from max value to | |
53 | * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and | |
54 | * then ramp-down rapidly later on. | |
55 | * | |
56 | * This gives a percentage rampdown for time elapsed in milliseconds. | |
57 | * ramp_down_percentage = ((ms * ms) >> 18) | |
58 | * ~= 3.8 * (sec * sec) | |
59 | * | |
60 | * At 0 ms ramp_down_percent = 0 | |
61 | * At 5120 ms ramp_down_percent = 100 | |
62 | */ | |
63 | #define ramp_down_percent(time) ((time * time) >> 18) | |
64 | ||
65 | /* Interval after which the timer is queued to bring down global pstate */ | |
66 | #define GPSTATE_TIMER_INTERVAL 2000 | |
67 | ||
68 | /** | |
69 | * struct global_pstate_info - Per policy data structure to maintain history of | |
70 | * global pstates | |
09ca4c9b AA |
71 | * @highest_lpstate_idx: The local pstate index from which we are |
72 | * ramping down | |
eaa2c3ae | 73 | * @elapsed_time: Time in ms spent in ramping down from |
09ca4c9b | 74 | * highest_lpstate_idx |
eaa2c3ae AA |
75 | * @last_sampled_time: Time from boot in ms when global pstates were |
76 | * last set | |
09ca4c9b AA |
77 | * @last_lpstate_idx, Last set value of local pstate and global |
78 | * last_gpstate_idx pstate in terms of cpufreq table index | |
eaa2c3ae AA |
79 | * @timer: Is used for ramping down if cpu goes idle for |
80 | * a long time with global pstate held high | |
81 | * @gpstate_lock: A spinlock to maintain synchronization between | |
82 | * routines called by the timer handler and | |
83 | * governer's target_index calls | |
84 | */ | |
85 | struct global_pstate_info { | |
09ca4c9b | 86 | int highest_lpstate_idx; |
eaa2c3ae AA |
87 | unsigned int elapsed_time; |
88 | unsigned int last_sampled_time; | |
09ca4c9b AA |
89 | int last_lpstate_idx; |
90 | int last_gpstate_idx; | |
eaa2c3ae AA |
91 | spinlock_t gpstate_lock; |
92 | struct timer_list timer; | |
1d1fe902 | 93 | struct cpufreq_policy *policy; |
eaa2c3ae AA |
94 | }; |
95 | ||
b3d627a5 | 96 | static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1]; |
332f0a01 GS |
97 | |
98 | DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER); | |
99 | /** | |
100 | * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap | |
101 | * indexed by a function of pstate id. | |
102 | * | |
103 | * @pstate_id: pstate id for this entry. | |
104 | * | |
105 | * @cpufreq_table_idx: Index into the powernv_freqs | |
106 | * cpufreq_frequency_table for frequency | |
107 | * corresponding to pstate_id. | |
108 | * | |
109 | * @hentry: hlist_node that hooks this entry into the pstate_revmap | |
110 | * hashtable | |
111 | */ | |
112 | struct pstate_idx_revmap_data { | |
967b87fd | 113 | u8 pstate_id; |
332f0a01 GS |
114 | unsigned int cpufreq_table_idx; |
115 | struct hlist_node hentry; | |
116 | }; | |
117 | ||
cb166fa9 | 118 | static bool rebooting, throttled, occ_reset; |
b3d627a5 | 119 | |
c89f2682 SB |
120 | static const char * const throttle_reason[] = { |
121 | "No throttling", | |
122 | "Power Cap", | |
123 | "Processor Over Temperature", | |
124 | "Power Supply Failure", | |
125 | "Over Current", | |
126 | "OCC Reset" | |
127 | }; | |
128 | ||
1b028984 SB |
129 | enum throttle_reason_type { |
130 | NO_THROTTLE = 0, | |
131 | POWERCAP, | |
132 | CPU_OVERTEMP, | |
133 | POWER_SUPPLY_FAILURE, | |
134 | OVERCURRENT, | |
135 | OCC_RESET_THROTTLE, | |
136 | OCC_MAX_REASON | |
137 | }; | |
138 | ||
053819e0 SB |
139 | static struct chip { |
140 | unsigned int id; | |
141 | bool throttled; | |
c89f2682 SB |
142 | bool restore; |
143 | u8 throttle_reason; | |
735366fc SB |
144 | cpumask_t mask; |
145 | struct work_struct throttle; | |
1b028984 SB |
146 | int throttle_turbo; |
147 | int throttle_sub_turbo; | |
148 | int reason[OCC_MAX_REASON]; | |
053819e0 SB |
149 | } *chips; |
150 | ||
151 | static int nr_chips; | |
3e5963bc | 152 | static DEFINE_PER_CPU(struct chip *, chip_info); |
053819e0 | 153 | |
b3d627a5 | 154 | /* |
09ca4c9b AA |
155 | * Note: |
156 | * The set of pstates consists of contiguous integers. | |
157 | * powernv_pstate_info stores the index of the frequency table for | |
158 | * max, min and nominal frequencies. It also stores number of | |
159 | * available frequencies. | |
b3d627a5 | 160 | * |
09ca4c9b AA |
161 | * powernv_pstate_info.nominal indicates the index to the highest |
162 | * non-turbo frequency. | |
b3d627a5 VS |
163 | */ |
164 | static struct powernv_pstate_info { | |
09ca4c9b AA |
165 | unsigned int min; |
166 | unsigned int max; | |
167 | unsigned int nominal; | |
168 | unsigned int nr_pstates; | |
b12f7a2b | 169 | bool wof_enabled; |
b3d627a5 VS |
170 | } powernv_pstate_info; |
171 | ||
967b87fd | 172 | static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift) |
ee1f4a7d | 173 | { |
967b87fd | 174 | return ((pmsr_val >> shift) & 0xFF); |
ee1f4a7d GS |
175 | } |
176 | ||
177 | #define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT) | |
178 | #define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT) | |
179 | #define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT) | |
180 | ||
332f0a01 GS |
181 | /* Use following functions for conversions between pstate_id and index */ |
182 | ||
183 | /** | |
184 | * idx_to_pstate : Returns the pstate id corresponding to the | |
185 | * frequency in the cpufreq frequency table | |
186 | * powernv_freqs indexed by @i. | |
187 | * | |
188 | * If @i is out of bound, this will return the pstate | |
189 | * corresponding to the nominal frequency. | |
190 | */ | |
967b87fd | 191 | static inline u8 idx_to_pstate(unsigned int i) |
09ca4c9b | 192 | { |
8e859467 | 193 | if (unlikely(i >= powernv_pstate_info.nr_pstates)) { |
332f0a01 | 194 | pr_warn_once("idx_to_pstate: index %u is out of bound\n", i); |
8e859467 AA |
195 | return powernv_freqs[powernv_pstate_info.nominal].driver_data; |
196 | } | |
197 | ||
09ca4c9b AA |
198 | return powernv_freqs[i].driver_data; |
199 | } | |
200 | ||
332f0a01 GS |
201 | /** |
202 | * pstate_to_idx : Returns the index in the cpufreq frequencytable | |
203 | * powernv_freqs for the frequency whose corresponding | |
204 | * pstate id is @pstate. | |
205 | * | |
206 | * If no frequency corresponding to @pstate is found, | |
207 | * this will return the index of the nominal | |
208 | * frequency. | |
209 | */ | |
967b87fd | 210 | static unsigned int pstate_to_idx(u8 pstate) |
09ca4c9b | 211 | { |
332f0a01 GS |
212 | unsigned int key = pstate % POWERNV_MAX_PSTATES; |
213 | struct pstate_idx_revmap_data *revmap_data; | |
8e859467 | 214 | |
332f0a01 GS |
215 | hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) { |
216 | if (revmap_data->pstate_id == pstate) | |
217 | return revmap_data->cpufreq_table_idx; | |
8e859467 | 218 | } |
332f0a01 | 219 | |
967b87fd | 220 | pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate); |
332f0a01 | 221 | return powernv_pstate_info.nominal; |
09ca4c9b AA |
222 | } |
223 | ||
eaa2c3ae AA |
224 | static inline void reset_gpstates(struct cpufreq_policy *policy) |
225 | { | |
226 | struct global_pstate_info *gpstates = policy->driver_data; | |
227 | ||
09ca4c9b | 228 | gpstates->highest_lpstate_idx = 0; |
eaa2c3ae AA |
229 | gpstates->elapsed_time = 0; |
230 | gpstates->last_sampled_time = 0; | |
09ca4c9b AA |
231 | gpstates->last_lpstate_idx = 0; |
232 | gpstates->last_gpstate_idx = 0; | |
eaa2c3ae AA |
233 | } |
234 | ||
b3d627a5 VS |
235 | /* |
236 | * Initialize the freq table based on data obtained | |
237 | * from the firmware passed via device-tree | |
238 | */ | |
239 | static int init_powernv_pstates(void) | |
240 | { | |
241 | struct device_node *power_mgt; | |
09ca4c9b | 242 | int i, nr_pstates = 0; |
b3d627a5 VS |
243 | const __be32 *pstate_ids, *pstate_freqs; |
244 | u32 len_ids, len_freqs; | |
09ca4c9b | 245 | u32 pstate_min, pstate_max, pstate_nominal; |
b12f7a2b | 246 | u32 pstate_turbo, pstate_ultra_turbo; |
b3d627a5 VS |
247 | |
248 | power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); | |
249 | if (!power_mgt) { | |
250 | pr_warn("power-mgt node not found\n"); | |
251 | return -ENODEV; | |
252 | } | |
253 | ||
254 | if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) { | |
255 | pr_warn("ibm,pstate-min node not found\n"); | |
3be466d6 | 256 | goto out; |
b3d627a5 VS |
257 | } |
258 | ||
259 | if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) { | |
260 | pr_warn("ibm,pstate-max node not found\n"); | |
3be466d6 | 261 | goto out; |
b3d627a5 VS |
262 | } |
263 | ||
264 | if (of_property_read_u32(power_mgt, "ibm,pstate-nominal", | |
265 | &pstate_nominal)) { | |
266 | pr_warn("ibm,pstate-nominal not found\n"); | |
3be466d6 | 267 | goto out; |
b3d627a5 | 268 | } |
b12f7a2b SB |
269 | |
270 | if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo", | |
271 | &pstate_ultra_turbo)) { | |
272 | powernv_pstate_info.wof_enabled = false; | |
273 | goto next; | |
274 | } | |
275 | ||
276 | if (of_property_read_u32(power_mgt, "ibm,pstate-turbo", | |
277 | &pstate_turbo)) { | |
278 | powernv_pstate_info.wof_enabled = false; | |
279 | goto next; | |
280 | } | |
281 | ||
282 | if (pstate_turbo == pstate_ultra_turbo) | |
283 | powernv_pstate_info.wof_enabled = false; | |
284 | else | |
285 | powernv_pstate_info.wof_enabled = true; | |
286 | ||
287 | next: | |
967b87fd | 288 | pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min, |
b3d627a5 | 289 | pstate_nominal, pstate_max); |
b12f7a2b SB |
290 | pr_info("Workload Optimized Frequency is %s in the platform\n", |
291 | (powernv_pstate_info.wof_enabled) ? "enabled" : "disabled"); | |
b3d627a5 VS |
292 | |
293 | pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids); | |
294 | if (!pstate_ids) { | |
295 | pr_warn("ibm,pstate-ids not found\n"); | |
3be466d6 | 296 | goto out; |
b3d627a5 VS |
297 | } |
298 | ||
299 | pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz", | |
300 | &len_freqs); | |
301 | if (!pstate_freqs) { | |
302 | pr_warn("ibm,pstate-frequencies-mhz not found\n"); | |
3be466d6 | 303 | goto out; |
b3d627a5 VS |
304 | } |
305 | ||
6174bac8 VS |
306 | if (len_ids != len_freqs) { |
307 | pr_warn("Entries in ibm,pstate-ids and " | |
308 | "ibm,pstate-frequencies-mhz does not match\n"); | |
309 | } | |
310 | ||
b3d627a5 VS |
311 | nr_pstates = min(len_ids, len_freqs) / sizeof(u32); |
312 | if (!nr_pstates) { | |
313 | pr_warn("No PStates found\n"); | |
3be466d6 | 314 | goto out; |
b3d627a5 VS |
315 | } |
316 | ||
09ca4c9b | 317 | powernv_pstate_info.nr_pstates = nr_pstates; |
b3d627a5 | 318 | pr_debug("NR PStates %d\n", nr_pstates); |
ee1f4a7d | 319 | |
b3d627a5 VS |
320 | for (i = 0; i < nr_pstates; i++) { |
321 | u32 id = be32_to_cpu(pstate_ids[i]); | |
322 | u32 freq = be32_to_cpu(pstate_freqs[i]); | |
332f0a01 GS |
323 | struct pstate_idx_revmap_data *revmap_data; |
324 | unsigned int key; | |
b3d627a5 VS |
325 | |
326 | pr_debug("PState id %d freq %d MHz\n", id, freq); | |
327 | powernv_freqs[i].frequency = freq * 1000; /* kHz */ | |
967b87fd | 328 | powernv_freqs[i].driver_data = id & 0xFF; |
09ca4c9b | 329 | |
332f0a01 GS |
330 | revmap_data = (struct pstate_idx_revmap_data *) |
331 | kmalloc(sizeof(*revmap_data), GFP_KERNEL); | |
332 | ||
967b87fd | 333 | revmap_data->pstate_id = id & 0xFF; |
332f0a01 | 334 | revmap_data->cpufreq_table_idx = i; |
967b87fd | 335 | key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES; |
332f0a01 GS |
336 | hash_add(pstate_revmap, &revmap_data->hentry, key); |
337 | ||
09ca4c9b AA |
338 | if (id == pstate_max) |
339 | powernv_pstate_info.max = i; | |
3fa4680b | 340 | if (id == pstate_nominal) |
09ca4c9b | 341 | powernv_pstate_info.nominal = i; |
3fa4680b | 342 | if (id == pstate_min) |
09ca4c9b | 343 | powernv_pstate_info.min = i; |
b12f7a2b SB |
344 | |
345 | if (powernv_pstate_info.wof_enabled && id == pstate_turbo) { | |
346 | int j; | |
347 | ||
348 | for (j = i - 1; j >= (int)powernv_pstate_info.max; j--) | |
349 | powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ; | |
350 | } | |
b3d627a5 | 351 | } |
09ca4c9b | 352 | |
b3d627a5 VS |
353 | /* End of list marker entry */ |
354 | powernv_freqs[i].frequency = CPUFREQ_TABLE_END; | |
3be466d6 YL |
355 | |
356 | of_node_put(power_mgt); | |
b3d627a5 | 357 | return 0; |
3be466d6 YL |
358 | out: |
359 | of_node_put(power_mgt); | |
360 | return -ENODEV; | |
b3d627a5 VS |
361 | } |
362 | ||
363 | /* Returns the CPU frequency corresponding to the pstate_id. */ | |
967b87fd | 364 | static unsigned int pstate_id_to_freq(u8 pstate_id) |
b3d627a5 VS |
365 | { |
366 | int i; | |
367 | ||
09ca4c9b | 368 | i = pstate_to_idx(pstate_id); |
6174bac8 | 369 | if (i >= powernv_pstate_info.nr_pstates || i < 0) { |
967b87fd | 370 | pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n", |
09ca4c9b AA |
371 | pstate_id, idx_to_pstate(powernv_pstate_info.nominal)); |
372 | i = powernv_pstate_info.nominal; | |
6174bac8 | 373 | } |
b3d627a5 VS |
374 | |
375 | return powernv_freqs[i].frequency; | |
376 | } | |
377 | ||
378 | /* | |
379 | * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by | |
380 | * the firmware | |
381 | */ | |
382 | static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy, | |
383 | char *buf) | |
384 | { | |
385 | return sprintf(buf, "%u\n", | |
09ca4c9b | 386 | powernv_freqs[powernv_pstate_info.nominal].frequency); |
b3d627a5 VS |
387 | } |
388 | ||
389 | struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq = | |
390 | __ATTR_RO(cpuinfo_nominal_freq); | |
391 | ||
b12f7a2b SB |
392 | #define SCALING_BOOST_FREQS_ATTR_INDEX 2 |
393 | ||
b3d627a5 VS |
394 | static struct freq_attr *powernv_cpu_freq_attr[] = { |
395 | &cpufreq_freq_attr_scaling_available_freqs, | |
396 | &cpufreq_freq_attr_cpuinfo_nominal_freq, | |
b12f7a2b | 397 | &cpufreq_freq_attr_scaling_boost_freqs, |
b3d627a5 VS |
398 | NULL, |
399 | }; | |
400 | ||
1b028984 SB |
401 | #define throttle_attr(name, member) \ |
402 | static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \ | |
403 | { \ | |
404 | struct chip *chip = per_cpu(chip_info, policy->cpu); \ | |
405 | \ | |
406 | return sprintf(buf, "%u\n", chip->member); \ | |
407 | } \ | |
408 | \ | |
409 | static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \ | |
410 | ||
411 | throttle_attr(unthrottle, reason[NO_THROTTLE]); | |
412 | throttle_attr(powercap, reason[POWERCAP]); | |
413 | throttle_attr(overtemp, reason[CPU_OVERTEMP]); | |
414 | throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]); | |
415 | throttle_attr(overcurrent, reason[OVERCURRENT]); | |
416 | throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]); | |
417 | throttle_attr(turbo_stat, throttle_turbo); | |
418 | throttle_attr(sub_turbo_stat, throttle_sub_turbo); | |
419 | ||
420 | static struct attribute *throttle_attrs[] = { | |
421 | &throttle_attr_unthrottle.attr, | |
422 | &throttle_attr_powercap.attr, | |
423 | &throttle_attr_overtemp.attr, | |
424 | &throttle_attr_supply_fault.attr, | |
425 | &throttle_attr_overcurrent.attr, | |
426 | &throttle_attr_occ_reset.attr, | |
427 | &throttle_attr_turbo_stat.attr, | |
428 | &throttle_attr_sub_turbo_stat.attr, | |
429 | NULL, | |
430 | }; | |
431 | ||
432 | static const struct attribute_group throttle_attr_grp = { | |
433 | .name = "throttle_stats", | |
434 | .attrs = throttle_attrs, | |
435 | }; | |
436 | ||
b3d627a5 VS |
437 | /* Helper routines */ |
438 | ||
439 | /* Access helpers to power mgt SPR */ | |
440 | ||
441 | static inline unsigned long get_pmspr(unsigned long sprn) | |
442 | { | |
443 | switch (sprn) { | |
444 | case SPRN_PMCR: | |
445 | return mfspr(SPRN_PMCR); | |
446 | ||
447 | case SPRN_PMICR: | |
448 | return mfspr(SPRN_PMICR); | |
449 | ||
450 | case SPRN_PMSR: | |
451 | return mfspr(SPRN_PMSR); | |
452 | } | |
453 | BUG(); | |
454 | } | |
455 | ||
456 | static inline void set_pmspr(unsigned long sprn, unsigned long val) | |
457 | { | |
458 | switch (sprn) { | |
459 | case SPRN_PMCR: | |
460 | mtspr(SPRN_PMCR, val); | |
461 | return; | |
462 | ||
463 | case SPRN_PMICR: | |
464 | mtspr(SPRN_PMICR, val); | |
465 | return; | |
466 | } | |
467 | BUG(); | |
468 | } | |
469 | ||
470 | /* | |
471 | * Use objects of this type to query/update | |
472 | * pstates on a remote CPU via smp_call_function. | |
473 | */ | |
474 | struct powernv_smp_call_data { | |
475 | unsigned int freq; | |
967b87fd GS |
476 | u8 pstate_id; |
477 | u8 gpstate_id; | |
b3d627a5 VS |
478 | }; |
479 | ||
480 | /* | |
481 | * powernv_read_cpu_freq: Reads the current frequency on this CPU. | |
482 | * | |
483 | * Called via smp_call_function. | |
484 | * | |
485 | * Note: The caller of the smp_call_function should pass an argument of | |
486 | * the type 'struct powernv_smp_call_data *' along with this function. | |
487 | * | |
488 | * The current frequency on this CPU will be returned via | |
489 | * ((struct powernv_smp_call_data *)arg)->freq; | |
490 | */ | |
491 | static void powernv_read_cpu_freq(void *arg) | |
492 | { | |
493 | unsigned long pmspr_val; | |
b3d627a5 VS |
494 | struct powernv_smp_call_data *freq_data = arg; |
495 | ||
496 | pmspr_val = get_pmspr(SPRN_PMSR); | |
ee1f4a7d | 497 | freq_data->pstate_id = extract_local_pstate(pmspr_val); |
b3d627a5 VS |
498 | freq_data->freq = pstate_id_to_freq(freq_data->pstate_id); |
499 | ||
967b87fd GS |
500 | pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n", |
501 | raw_smp_processor_id(), pmspr_val, freq_data->pstate_id, | |
502 | freq_data->freq); | |
b3d627a5 VS |
503 | } |
504 | ||
505 | /* | |
506 | * powernv_cpufreq_get: Returns the CPU frequency as reported by the | |
507 | * firmware for CPU 'cpu'. This value is reported through the sysfs | |
508 | * file cpuinfo_cur_freq. | |
509 | */ | |
60d1ea4e | 510 | static unsigned int powernv_cpufreq_get(unsigned int cpu) |
b3d627a5 VS |
511 | { |
512 | struct powernv_smp_call_data freq_data; | |
513 | ||
514 | smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq, | |
515 | &freq_data, 1); | |
516 | ||
517 | return freq_data.freq; | |
518 | } | |
519 | ||
520 | /* | |
521 | * set_pstate: Sets the pstate on this CPU. | |
522 | * | |
523 | * This is called via an smp_call_function. | |
524 | * | |
525 | * The caller must ensure that freq_data is of the type | |
526 | * (struct powernv_smp_call_data *) and the pstate_id which needs to be set | |
527 | * on this CPU should be present in freq_data->pstate_id. | |
528 | */ | |
eaa2c3ae | 529 | static void set_pstate(void *data) |
b3d627a5 VS |
530 | { |
531 | unsigned long val; | |
eaa2c3ae AA |
532 | struct powernv_smp_call_data *freq_data = data; |
533 | unsigned long pstate_ul = freq_data->pstate_id; | |
534 | unsigned long gpstate_ul = freq_data->gpstate_id; | |
b3d627a5 VS |
535 | |
536 | val = get_pmspr(SPRN_PMCR); | |
537 | val = val & 0x0000FFFFFFFFFFFFULL; | |
538 | ||
539 | pstate_ul = pstate_ul & 0xFF; | |
eaa2c3ae | 540 | gpstate_ul = gpstate_ul & 0xFF; |
b3d627a5 VS |
541 | |
542 | /* Set both global(bits 56..63) and local(bits 48..55) PStates */ | |
eaa2c3ae | 543 | val = val | (gpstate_ul << 56) | (pstate_ul << 48); |
b3d627a5 VS |
544 | |
545 | pr_debug("Setting cpu %d pmcr to %016lX\n", | |
546 | raw_smp_processor_id(), val); | |
547 | set_pmspr(SPRN_PMCR, val); | |
548 | } | |
549 | ||
cf30af76 SB |
550 | /* |
551 | * get_nominal_index: Returns the index corresponding to the nominal | |
552 | * pstate in the cpufreq table | |
553 | */ | |
554 | static inline unsigned int get_nominal_index(void) | |
555 | { | |
09ca4c9b | 556 | return powernv_pstate_info.nominal; |
cf30af76 SB |
557 | } |
558 | ||
735366fc | 559 | static void powernv_cpufreq_throttle_check(void *data) |
09a972d1 | 560 | { |
3e5963bc | 561 | struct chip *chip; |
735366fc | 562 | unsigned int cpu = smp_processor_id(); |
09a972d1 | 563 | unsigned long pmsr; |
967b87fd | 564 | u8 pmsr_pmax; |
09ca4c9b | 565 | unsigned int pmsr_pmax_idx; |
09a972d1 SB |
566 | |
567 | pmsr = get_pmspr(SPRN_PMSR); | |
3e5963bc | 568 | chip = this_cpu_read(chip_info); |
053819e0 | 569 | |
09a972d1 | 570 | /* Check for Pmax Capping */ |
ee1f4a7d | 571 | pmsr_pmax = extract_max_pstate(pmsr); |
09ca4c9b AA |
572 | pmsr_pmax_idx = pstate_to_idx(pmsr_pmax); |
573 | if (pmsr_pmax_idx != powernv_pstate_info.max) { | |
3e5963bc | 574 | if (chip->throttled) |
053819e0 | 575 | goto next; |
3e5963bc | 576 | chip->throttled = true; |
09ca4c9b | 577 | if (pmsr_pmax_idx > powernv_pstate_info.nominal) { |
967b87fd | 578 | pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n", |
3e5963bc | 579 | cpu, chip->id, pmsr_pmax, |
09ca4c9b | 580 | idx_to_pstate(powernv_pstate_info.nominal)); |
1b028984 SB |
581 | chip->throttle_sub_turbo++; |
582 | } else { | |
583 | chip->throttle_turbo++; | |
584 | } | |
3e5963bc MN |
585 | trace_powernv_throttle(chip->id, |
586 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 587 | pmsr_pmax); |
3e5963bc MN |
588 | } else if (chip->throttled) { |
589 | chip->throttled = false; | |
590 | trace_powernv_throttle(chip->id, | |
591 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 592 | pmsr_pmax); |
09a972d1 SB |
593 | } |
594 | ||
3dd3ebe5 | 595 | /* Check if Psafe_mode_active is set in PMSR. */ |
053819e0 | 596 | next: |
3dd3ebe5 | 597 | if (pmsr & PMSR_PSAFE_ENABLE) { |
09a972d1 SB |
598 | throttled = true; |
599 | pr_info("Pstate set to safe frequency\n"); | |
600 | } | |
601 | ||
602 | /* Check if SPR_EM_DISABLE is set in PMSR */ | |
603 | if (pmsr & PMSR_SPR_EM_DISABLE) { | |
604 | throttled = true; | |
605 | pr_info("Frequency Control disabled from OS\n"); | |
606 | } | |
607 | ||
608 | if (throttled) { | |
609 | pr_info("PMSR = %16lx\n", pmsr); | |
c89f2682 | 610 | pr_warn("CPU Frequency could be throttled\n"); |
09a972d1 SB |
611 | } |
612 | } | |
613 | ||
eaa2c3ae AA |
614 | /** |
615 | * calc_global_pstate - Calculate global pstate | |
09ca4c9b AA |
616 | * @elapsed_time: Elapsed time in milliseconds |
617 | * @local_pstate_idx: New local pstate | |
618 | * @highest_lpstate_idx: pstate from which its ramping down | |
eaa2c3ae AA |
619 | * |
620 | * Finds the appropriate global pstate based on the pstate from which its | |
621 | * ramping down and the time elapsed in ramping down. It follows a quadratic | |
622 | * equation which ensures that it reaches ramping down to pmin in 5sec. | |
623 | */ | |
624 | static inline int calc_global_pstate(unsigned int elapsed_time, | |
09ca4c9b AA |
625 | int highest_lpstate_idx, |
626 | int local_pstate_idx) | |
eaa2c3ae | 627 | { |
09ca4c9b | 628 | int index_diff; |
eaa2c3ae AA |
629 | |
630 | /* | |
631 | * Using ramp_down_percent we get the percentage of rampdown | |
632 | * that we are expecting to be dropping. Difference between | |
09ca4c9b | 633 | * highest_lpstate_idx and powernv_pstate_info.min will give a absolute |
eaa2c3ae AA |
634 | * number of how many pstates we will drop eventually by the end of |
635 | * 5 seconds, then just scale it get the number pstates to be dropped. | |
636 | */ | |
09ca4c9b AA |
637 | index_diff = ((int)ramp_down_percent(elapsed_time) * |
638 | (powernv_pstate_info.min - highest_lpstate_idx)) / 100; | |
eaa2c3ae AA |
639 | |
640 | /* Ensure that global pstate is >= to local pstate */ | |
09ca4c9b AA |
641 | if (highest_lpstate_idx + index_diff >= local_pstate_idx) |
642 | return local_pstate_idx; | |
eaa2c3ae | 643 | else |
09ca4c9b | 644 | return highest_lpstate_idx + index_diff; |
eaa2c3ae AA |
645 | } |
646 | ||
647 | static inline void queue_gpstate_timer(struct global_pstate_info *gpstates) | |
648 | { | |
649 | unsigned int timer_interval; | |
650 | ||
651 | /* | |
652 | * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But | |
653 | * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time. | |
654 | * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME | |
655 | * seconds of ramp down time. | |
656 | */ | |
657 | if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL) | |
658 | > MAX_RAMP_DOWN_TIME) | |
659 | timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time; | |
660 | else | |
661 | timer_interval = GPSTATE_TIMER_INTERVAL; | |
662 | ||
7bc54b65 | 663 | mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval)); |
eaa2c3ae AA |
664 | } |
665 | ||
666 | /** | |
667 | * gpstate_timer_handler | |
668 | * | |
669 | * @data: pointer to cpufreq_policy on which timer was queued | |
670 | * | |
671 | * This handler brings down the global pstate closer to the local pstate | |
672 | * according quadratic equation. Queues a new timer if it is still not equal | |
673 | * to local pstate | |
674 | */ | |
1d1fe902 | 675 | void gpstate_timer_handler(struct timer_list *t) |
eaa2c3ae | 676 | { |
1d1fe902 KC |
677 | struct global_pstate_info *gpstates = from_timer(gpstates, t, timer); |
678 | struct cpufreq_policy *policy = gpstates->policy; | |
20b15b76 AA |
679 | int gpstate_idx, lpstate_idx; |
680 | unsigned long val; | |
eaa2c3ae AA |
681 | unsigned int time_diff = jiffies_to_msecs(jiffies) |
682 | - gpstates->last_sampled_time; | |
683 | struct powernv_smp_call_data freq_data; | |
684 | ||
685 | if (!spin_trylock(&gpstates->gpstate_lock)) | |
686 | return; | |
c0f7f5b6 SB |
687 | /* |
688 | * If the timer has migrated to the different cpu then bring | |
689 | * it back to one of the policy->cpus | |
690 | */ | |
691 | if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) { | |
692 | gpstates->timer.expires = jiffies + msecs_to_jiffies(1); | |
693 | add_timer_on(&gpstates->timer, cpumask_first(policy->cpus)); | |
694 | spin_unlock(&gpstates->gpstate_lock); | |
695 | return; | |
696 | } | |
eaa2c3ae | 697 | |
20b15b76 AA |
698 | /* |
699 | * If PMCR was last updated was using fast_swtich then | |
700 | * We may have wrong in gpstate->last_lpstate_idx | |
701 | * value. Hence, read from PMCR to get correct data. | |
702 | */ | |
703 | val = get_pmspr(SPRN_PMCR); | |
ee1f4a7d GS |
704 | freq_data.gpstate_id = extract_global_pstate(val); |
705 | freq_data.pstate_id = extract_local_pstate(val); | |
20b15b76 AA |
706 | if (freq_data.gpstate_id == freq_data.pstate_id) { |
707 | reset_gpstates(policy); | |
708 | spin_unlock(&gpstates->gpstate_lock); | |
709 | return; | |
710 | } | |
711 | ||
eaa2c3ae AA |
712 | gpstates->last_sampled_time += time_diff; |
713 | gpstates->elapsed_time += time_diff; | |
eaa2c3ae | 714 | |
20b15b76 | 715 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { |
09ca4c9b | 716 | gpstate_idx = pstate_to_idx(freq_data.pstate_id); |
c9a81e68 | 717 | lpstate_idx = gpstate_idx; |
eaa2c3ae | 718 | reset_gpstates(policy); |
09ca4c9b | 719 | gpstates->highest_lpstate_idx = gpstate_idx; |
eaa2c3ae | 720 | } else { |
20b15b76 | 721 | lpstate_idx = pstate_to_idx(freq_data.pstate_id); |
09ca4c9b AA |
722 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
723 | gpstates->highest_lpstate_idx, | |
20b15b76 | 724 | lpstate_idx); |
eaa2c3ae | 725 | } |
20b15b76 AA |
726 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
727 | gpstates->last_gpstate_idx = gpstate_idx; | |
728 | gpstates->last_lpstate_idx = lpstate_idx; | |
eaa2c3ae AA |
729 | /* |
730 | * If local pstate is equal to global pstate, rampdown is over | |
731 | * So timer is not required to be queued. | |
732 | */ | |
09ca4c9b | 733 | if (gpstate_idx != gpstates->last_lpstate_idx) |
eaa2c3ae AA |
734 | queue_gpstate_timer(gpstates); |
735 | ||
c0f7f5b6 | 736 | set_pstate(&freq_data); |
1fd3ff28 | 737 | spin_unlock(&gpstates->gpstate_lock); |
eaa2c3ae AA |
738 | } |
739 | ||
b3d627a5 VS |
740 | /* |
741 | * powernv_cpufreq_target_index: Sets the frequency corresponding to | |
742 | * the cpufreq table entry indexed by new_index on the cpus in the | |
743 | * mask policy->cpus | |
744 | */ | |
745 | static int powernv_cpufreq_target_index(struct cpufreq_policy *policy, | |
746 | unsigned int new_index) | |
747 | { | |
748 | struct powernv_smp_call_data freq_data; | |
09ca4c9b | 749 | unsigned int cur_msec, gpstate_idx; |
eaa2c3ae | 750 | struct global_pstate_info *gpstates = policy->driver_data; |
b3d627a5 | 751 | |
cf30af76 SB |
752 | if (unlikely(rebooting) && new_index != get_nominal_index()) |
753 | return 0; | |
754 | ||
8a10c06a DK |
755 | if (!throttled) { |
756 | /* we don't want to be preempted while | |
757 | * checking if the CPU frequency has been throttled | |
758 | */ | |
759 | preempt_disable(); | |
735366fc | 760 | powernv_cpufreq_throttle_check(NULL); |
8a10c06a DK |
761 | preempt_enable(); |
762 | } | |
09a972d1 | 763 | |
eaa2c3ae AA |
764 | cur_msec = jiffies_to_msecs(get_jiffies_64()); |
765 | ||
09ca4c9b | 766 | freq_data.pstate_id = idx_to_pstate(new_index); |
dcb14337 SB |
767 | if (!gpstates) { |
768 | freq_data.gpstate_id = freq_data.pstate_id; | |
769 | goto no_gpstate; | |
770 | } | |
771 | ||
772 | spin_lock(&gpstates->gpstate_lock); | |
b3d627a5 | 773 | |
eaa2c3ae | 774 | if (!gpstates->last_sampled_time) { |
09ca4c9b AA |
775 | gpstate_idx = new_index; |
776 | gpstates->highest_lpstate_idx = new_index; | |
eaa2c3ae AA |
777 | goto gpstates_done; |
778 | } | |
779 | ||
09ca4c9b | 780 | if (gpstates->last_gpstate_idx < new_index) { |
eaa2c3ae AA |
781 | gpstates->elapsed_time += cur_msec - |
782 | gpstates->last_sampled_time; | |
783 | ||
784 | /* | |
785 | * If its has been ramping down for more than MAX_RAMP_DOWN_TIME | |
786 | * we should be resetting all global pstate related data. Set it | |
787 | * equal to local pstate to start fresh. | |
788 | */ | |
789 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { | |
790 | reset_gpstates(policy); | |
09ca4c9b AA |
791 | gpstates->highest_lpstate_idx = new_index; |
792 | gpstate_idx = new_index; | |
eaa2c3ae AA |
793 | } else { |
794 | /* Elaspsed_time is less than 5 seconds, continue to rampdown */ | |
09ca4c9b AA |
795 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
796 | gpstates->highest_lpstate_idx, | |
797 | new_index); | |
eaa2c3ae AA |
798 | } |
799 | } else { | |
800 | reset_gpstates(policy); | |
09ca4c9b AA |
801 | gpstates->highest_lpstate_idx = new_index; |
802 | gpstate_idx = new_index; | |
eaa2c3ae AA |
803 | } |
804 | ||
805 | /* | |
806 | * If local pstate is equal to global pstate, rampdown is over | |
807 | * So timer is not required to be queued. | |
808 | */ | |
09ca4c9b | 809 | if (gpstate_idx != new_index) |
eaa2c3ae | 810 | queue_gpstate_timer(gpstates); |
0bc10b93 AA |
811 | else |
812 | del_timer_sync(&gpstates->timer); | |
eaa2c3ae AA |
813 | |
814 | gpstates_done: | |
09ca4c9b | 815 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
eaa2c3ae | 816 | gpstates->last_sampled_time = cur_msec; |
09ca4c9b AA |
817 | gpstates->last_gpstate_idx = gpstate_idx; |
818 | gpstates->last_lpstate_idx = new_index; | |
eaa2c3ae | 819 | |
1fd3ff28 AA |
820 | spin_unlock(&gpstates->gpstate_lock); |
821 | ||
dcb14337 | 822 | no_gpstate: |
b3d627a5 VS |
823 | /* |
824 | * Use smp_call_function to send IPI and execute the | |
825 | * mtspr on target CPU. We could do that without IPI | |
826 | * if current CPU is within policy->cpus (core) | |
827 | */ | |
828 | smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1); | |
b3d627a5 VS |
829 | return 0; |
830 | } | |
831 | ||
832 | static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
833 | { | |
bf14721c | 834 | int base, i; |
2920e9ce | 835 | struct kernfs_node *kn; |
eaa2c3ae | 836 | struct global_pstate_info *gpstates; |
b3d627a5 VS |
837 | |
838 | base = cpu_first_thread_sibling(policy->cpu); | |
839 | ||
840 | for (i = 0; i < threads_per_core; i++) | |
841 | cpumask_set_cpu(base + i, policy->cpus); | |
842 | ||
2920e9ce SB |
843 | kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name); |
844 | if (!kn) { | |
1b028984 SB |
845 | int ret; |
846 | ||
847 | ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp); | |
848 | if (ret) { | |
849 | pr_info("Failed to create throttle stats directory for cpu %d\n", | |
850 | policy->cpu); | |
851 | return ret; | |
852 | } | |
2920e9ce SB |
853 | } else { |
854 | kernfs_put(kn); | |
1b028984 | 855 | } |
eaa2c3ae | 856 | |
dcb14337 SB |
857 | policy->freq_table = powernv_freqs; |
858 | policy->fast_switch_possible = true; | |
859 | ||
860 | if (pvr_version_is(PVR_POWER9)) | |
861 | return 0; | |
862 | ||
863 | /* Initialise Gpstate ramp-down timer only on POWER8 */ | |
eaa2c3ae AA |
864 | gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL); |
865 | if (!gpstates) | |
866 | return -ENOMEM; | |
867 | ||
868 | policy->driver_data = gpstates; | |
869 | ||
870 | /* initialize timer */ | |
1d1fe902 KC |
871 | gpstates->policy = policy; |
872 | timer_setup(&gpstates->timer, gpstate_timer_handler, | |
873 | TIMER_PINNED | TIMER_DEFERRABLE); | |
eaa2c3ae AA |
874 | gpstates->timer.expires = jiffies + |
875 | msecs_to_jiffies(GPSTATE_TIMER_INTERVAL); | |
876 | spin_lock_init(&gpstates->gpstate_lock); | |
eaa2c3ae | 877 | |
bf14721c | 878 | return 0; |
eaa2c3ae AA |
879 | } |
880 | ||
881 | static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy) | |
882 | { | |
883 | /* timer is deleted in cpufreq_cpu_stop() */ | |
884 | kfree(policy->driver_data); | |
885 | ||
886 | return 0; | |
b3d627a5 VS |
887 | } |
888 | ||
cf30af76 SB |
889 | static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb, |
890 | unsigned long action, void *unused) | |
891 | { | |
892 | int cpu; | |
893 | struct cpufreq_policy cpu_policy; | |
894 | ||
895 | rebooting = true; | |
896 | for_each_online_cpu(cpu) { | |
897 | cpufreq_get_policy(&cpu_policy, cpu); | |
898 | powernv_cpufreq_target_index(&cpu_policy, get_nominal_index()); | |
899 | } | |
900 | ||
901 | return NOTIFY_DONE; | |
902 | } | |
903 | ||
904 | static struct notifier_block powernv_cpufreq_reboot_nb = { | |
905 | .notifier_call = powernv_cpufreq_reboot_notifier, | |
906 | }; | |
907 | ||
735366fc SB |
908 | void powernv_cpufreq_work_fn(struct work_struct *work) |
909 | { | |
910 | struct chip *chip = container_of(work, struct chip, throttle); | |
22794280 | 911 | unsigned int cpu; |
6d167a44 | 912 | cpumask_t mask; |
735366fc | 913 | |
6d167a44 SB |
914 | get_online_cpus(); |
915 | cpumask_and(&mask, &chip->mask, cpu_online_mask); | |
916 | smp_call_function_any(&mask, | |
735366fc | 917 | powernv_cpufreq_throttle_check, NULL, 0); |
22794280 SB |
918 | |
919 | if (!chip->restore) | |
6d167a44 | 920 | goto out; |
22794280 SB |
921 | |
922 | chip->restore = false; | |
6d167a44 SB |
923 | for_each_cpu(cpu, &mask) { |
924 | int index; | |
22794280 SB |
925 | struct cpufreq_policy policy; |
926 | ||
927 | cpufreq_get_policy(&policy, cpu); | |
82577360 | 928 | index = cpufreq_table_find_index_c(&policy, policy.cur); |
22794280 | 929 | powernv_cpufreq_target_index(&policy, index); |
6d167a44 | 930 | cpumask_andnot(&mask, &mask, policy.cpus); |
22794280 | 931 | } |
6d167a44 SB |
932 | out: |
933 | put_online_cpus(); | |
735366fc SB |
934 | } |
935 | ||
cb166fa9 SB |
936 | static int powernv_cpufreq_occ_msg(struct notifier_block *nb, |
937 | unsigned long msg_type, void *_msg) | |
938 | { | |
939 | struct opal_msg *msg = _msg; | |
940 | struct opal_occ_msg omsg; | |
735366fc | 941 | int i; |
cb166fa9 SB |
942 | |
943 | if (msg_type != OPAL_MSG_OCC) | |
944 | return 0; | |
945 | ||
946 | omsg.type = be64_to_cpu(msg->params[0]); | |
947 | ||
948 | switch (omsg.type) { | |
949 | case OCC_RESET: | |
950 | occ_reset = true; | |
309d0631 | 951 | pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n"); |
cb166fa9 SB |
952 | /* |
953 | * powernv_cpufreq_throttle_check() is called in | |
954 | * target() callback which can detect the throttle state | |
955 | * for governors like ondemand. | |
956 | * But static governors will not call target() often thus | |
957 | * report throttling here. | |
958 | */ | |
959 | if (!throttled) { | |
960 | throttled = true; | |
c89f2682 | 961 | pr_warn("CPU frequency is throttled for duration\n"); |
cb166fa9 | 962 | } |
309d0631 | 963 | |
cb166fa9 SB |
964 | break; |
965 | case OCC_LOAD: | |
309d0631 | 966 | pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n"); |
cb166fa9 SB |
967 | break; |
968 | case OCC_THROTTLE: | |
969 | omsg.chip = be64_to_cpu(msg->params[1]); | |
970 | omsg.throttle_status = be64_to_cpu(msg->params[2]); | |
971 | ||
972 | if (occ_reset) { | |
973 | occ_reset = false; | |
974 | throttled = false; | |
309d0631 | 975 | pr_info("OCC Active, CPU frequency is no longer throttled\n"); |
735366fc | 976 | |
22794280 SB |
977 | for (i = 0; i < nr_chips; i++) { |
978 | chips[i].restore = true; | |
735366fc | 979 | schedule_work(&chips[i].throttle); |
22794280 | 980 | } |
735366fc | 981 | |
cb166fa9 SB |
982 | return 0; |
983 | } | |
984 | ||
c89f2682 SB |
985 | for (i = 0; i < nr_chips; i++) |
986 | if (chips[i].id == omsg.chip) | |
987 | break; | |
988 | ||
989 | if (omsg.throttle_status >= 0 && | |
1b028984 | 990 | omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) { |
c89f2682 | 991 | chips[i].throttle_reason = omsg.throttle_status; |
1b028984 SB |
992 | chips[i].reason[omsg.throttle_status]++; |
993 | } | |
735366fc | 994 | |
c89f2682 SB |
995 | if (!omsg.throttle_status) |
996 | chips[i].restore = true; | |
997 | ||
998 | schedule_work(&chips[i].throttle); | |
cb166fa9 SB |
999 | } |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static struct notifier_block powernv_cpufreq_opal_nb = { | |
1004 | .notifier_call = powernv_cpufreq_occ_msg, | |
1005 | .next = NULL, | |
1006 | .priority = 0, | |
1007 | }; | |
1008 | ||
b120339c PM |
1009 | static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
1010 | { | |
1011 | struct powernv_smp_call_data freq_data; | |
eaa2c3ae | 1012 | struct global_pstate_info *gpstates = policy->driver_data; |
b120339c | 1013 | |
09ca4c9b AA |
1014 | freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min); |
1015 | freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min); | |
b120339c | 1016 | smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1); |
dcb14337 SB |
1017 | if (gpstates) |
1018 | del_timer_sync(&gpstates->timer); | |
b120339c PM |
1019 | } |
1020 | ||
60c9efb8 AA |
1021 | static unsigned int powernv_fast_switch(struct cpufreq_policy *policy, |
1022 | unsigned int target_freq) | |
1023 | { | |
1024 | int index; | |
1025 | struct powernv_smp_call_data freq_data; | |
1026 | ||
1027 | index = cpufreq_table_find_index_dl(policy, target_freq); | |
1028 | freq_data.pstate_id = powernv_freqs[index].driver_data; | |
1029 | freq_data.gpstate_id = powernv_freqs[index].driver_data; | |
1030 | set_pstate(&freq_data); | |
1031 | ||
1032 | return powernv_freqs[index].frequency; | |
1033 | } | |
1034 | ||
b3d627a5 VS |
1035 | static struct cpufreq_driver powernv_cpufreq_driver = { |
1036 | .name = "powernv-cpufreq", | |
1037 | .flags = CPUFREQ_CONST_LOOPS, | |
1038 | .init = powernv_cpufreq_cpu_init, | |
eaa2c3ae | 1039 | .exit = powernv_cpufreq_cpu_exit, |
b3d627a5 VS |
1040 | .verify = cpufreq_generic_frequency_table_verify, |
1041 | .target_index = powernv_cpufreq_target_index, | |
60c9efb8 | 1042 | .fast_switch = powernv_fast_switch, |
b3d627a5 | 1043 | .get = powernv_cpufreq_get, |
b120339c | 1044 | .stop_cpu = powernv_cpufreq_stop_cpu, |
b3d627a5 VS |
1045 | .attr = powernv_cpu_freq_attr, |
1046 | }; | |
1047 | ||
053819e0 SB |
1048 | static int init_chip_info(void) |
1049 | { | |
1050 | unsigned int chip[256]; | |
1051 | unsigned int cpu, i; | |
1052 | unsigned int prev_chip_id = UINT_MAX; | |
96c4726f | 1053 | |
3e5963bc | 1054 | for_each_possible_cpu(cpu) { |
053819e0 SB |
1055 | unsigned int id = cpu_to_chip_id(cpu); |
1056 | ||
1057 | if (prev_chip_id != id) { | |
1058 | prev_chip_id = id; | |
1059 | chip[nr_chips++] = id; | |
1060 | } | |
1061 | } | |
1062 | ||
c89f2682 | 1063 | chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL); |
053819e0 | 1064 | if (!chips) |
3e5963bc | 1065 | return -ENOMEM; |
053819e0 SB |
1066 | |
1067 | for (i = 0; i < nr_chips; i++) { | |
1068 | chips[i].id = chip[i]; | |
735366fc SB |
1069 | cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i])); |
1070 | INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn); | |
3e5963bc MN |
1071 | for_each_cpu(cpu, &chips[i].mask) |
1072 | per_cpu(chip_info, cpu) = &chips[i]; | |
053819e0 SB |
1073 | } |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
c5e29ea7 SB |
1078 | static inline void clean_chip_info(void) |
1079 | { | |
1080 | kfree(chips); | |
c5e29ea7 SB |
1081 | } |
1082 | ||
1083 | static inline void unregister_all_notifiers(void) | |
1084 | { | |
1085 | opal_message_notifier_unregister(OPAL_MSG_OCC, | |
1086 | &powernv_cpufreq_opal_nb); | |
1087 | unregister_reboot_notifier(&powernv_cpufreq_reboot_nb); | |
1088 | } | |
1089 | ||
b3d627a5 VS |
1090 | static int __init powernv_cpufreq_init(void) |
1091 | { | |
1092 | int rc = 0; | |
1093 | ||
6174bac8 | 1094 | /* Don't probe on pseries (guest) platforms */ |
e4d54f71 | 1095 | if (!firmware_has_feature(FW_FEATURE_OPAL)) |
6174bac8 VS |
1096 | return -ENODEV; |
1097 | ||
b3d627a5 VS |
1098 | /* Discover pstates from device tree and init */ |
1099 | rc = init_powernv_pstates(); | |
c5e29ea7 SB |
1100 | if (rc) |
1101 | goto out; | |
b3d627a5 | 1102 | |
053819e0 SB |
1103 | /* Populate chip info */ |
1104 | rc = init_chip_info(); | |
1105 | if (rc) | |
c5e29ea7 | 1106 | goto out; |
053819e0 | 1107 | |
cf30af76 | 1108 | register_reboot_notifier(&powernv_cpufreq_reboot_nb); |
cb166fa9 | 1109 | opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb); |
c5e29ea7 | 1110 | |
b12f7a2b SB |
1111 | if (powernv_pstate_info.wof_enabled) |
1112 | powernv_cpufreq_driver.boost_enabled = true; | |
1113 | else | |
1114 | powernv_cpu_freq_attr[SCALING_BOOST_FREQS_ATTR_INDEX] = NULL; | |
1115 | ||
c5e29ea7 | 1116 | rc = cpufreq_register_driver(&powernv_cpufreq_driver); |
b12f7a2b SB |
1117 | if (rc) { |
1118 | pr_info("Failed to register the cpufreq driver (%d)\n", rc); | |
1119 | goto cleanup_notifiers; | |
1120 | } | |
c5e29ea7 | 1121 | |
b12f7a2b SB |
1122 | if (powernv_pstate_info.wof_enabled) |
1123 | cpufreq_enable_boost_support(); | |
1124 | ||
1125 | return 0; | |
1126 | cleanup_notifiers: | |
c5e29ea7 SB |
1127 | unregister_all_notifiers(); |
1128 | clean_chip_info(); | |
1129 | out: | |
1130 | pr_info("Platform driver disabled. System does not support PState control\n"); | |
1131 | return rc; | |
b3d627a5 VS |
1132 | } |
1133 | module_init(powernv_cpufreq_init); | |
1134 | ||
1135 | static void __exit powernv_cpufreq_exit(void) | |
1136 | { | |
1137 | cpufreq_unregister_driver(&powernv_cpufreq_driver); | |
c5e29ea7 SB |
1138 | unregister_all_notifiers(); |
1139 | clean_chip_info(); | |
b3d627a5 VS |
1140 | } |
1141 | module_exit(powernv_cpufreq_exit); | |
1142 | ||
1143 | MODULE_LICENSE("GPL"); | |
1144 | MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>"); |