Commit | Line | Data |
---|---|---|
3e0a4e85 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b3d627a5 VS |
2 | /* |
3 | * POWERNV cpufreq driver for the IBM POWER processors | |
4 | * | |
5 | * (C) Copyright IBM 2014 | |
6 | * | |
7 | * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com> | |
b3d627a5 VS |
8 | */ |
9 | ||
10 | #define pr_fmt(fmt) "powernv-cpufreq: " fmt | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/sysfs.h> | |
14 | #include <linux/cpumask.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/cpufreq.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/of.h> | |
cf30af76 | 19 | #include <linux/reboot.h> |
053819e0 | 20 | #include <linux/slab.h> |
6d167a44 | 21 | #include <linux/cpu.h> |
332f0a01 | 22 | #include <linux/hashtable.h> |
c89f2682 | 23 | #include <trace/events/power.h> |
b3d627a5 VS |
24 | |
25 | #include <asm/cputhreads.h> | |
6174bac8 | 26 | #include <asm/firmware.h> |
b3d627a5 | 27 | #include <asm/reg.h> |
f3cae355 | 28 | #include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */ |
cb166fa9 | 29 | #include <asm/opal.h> |
eaa2c3ae | 30 | #include <linux/timer.h> |
b3d627a5 | 31 | |
332f0a01 GS |
32 | #define POWERNV_MAX_PSTATES_ORDER 8 |
33 | #define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER)) | |
09a972d1 SB |
34 | #define PMSR_PSAFE_ENABLE (1UL << 30) |
35 | #define PMSR_SPR_EM_DISABLE (1UL << 31) | |
ee1f4a7d | 36 | #define MAX_PSTATE_SHIFT 32 |
20b15b76 AA |
37 | #define LPSTATE_SHIFT 48 |
38 | #define GPSTATE_SHIFT 56 | |
f34ee9cb | 39 | #define MAX_NR_CHIPS 32 |
b3d627a5 | 40 | |
eaa2c3ae AA |
41 | #define MAX_RAMP_DOWN_TIME 5120 |
42 | /* | |
43 | * On an idle system we want the global pstate to ramp-down from max value to | |
44 | * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and | |
45 | * then ramp-down rapidly later on. | |
46 | * | |
47 | * This gives a percentage rampdown for time elapsed in milliseconds. | |
48 | * ramp_down_percentage = ((ms * ms) >> 18) | |
49 | * ~= 3.8 * (sec * sec) | |
50 | * | |
51 | * At 0 ms ramp_down_percent = 0 | |
52 | * At 5120 ms ramp_down_percent = 100 | |
53 | */ | |
54 | #define ramp_down_percent(time) ((time * time) >> 18) | |
55 | ||
56 | /* Interval after which the timer is queued to bring down global pstate */ | |
57 | #define GPSTATE_TIMER_INTERVAL 2000 | |
58 | ||
59 | /** | |
60 | * struct global_pstate_info - Per policy data structure to maintain history of | |
61 | * global pstates | |
09ca4c9b AA |
62 | * @highest_lpstate_idx: The local pstate index from which we are |
63 | * ramping down | |
eaa2c3ae | 64 | * @elapsed_time: Time in ms spent in ramping down from |
09ca4c9b | 65 | * highest_lpstate_idx |
eaa2c3ae AA |
66 | * @last_sampled_time: Time from boot in ms when global pstates were |
67 | * last set | |
44bd9a30 LJ |
68 | * @last_lpstate_idx: Last set value of local pstate and global |
69 | * @last_gpstate_idx: pstate in terms of cpufreq table index | |
eaa2c3ae AA |
70 | * @timer: Is used for ramping down if cpu goes idle for |
71 | * a long time with global pstate held high | |
72 | * @gpstate_lock: A spinlock to maintain synchronization between | |
73 | * routines called by the timer handler and | |
74 | * governer's target_index calls | |
44bd9a30 | 75 | * @policy: Associated CPUFreq policy |
eaa2c3ae AA |
76 | */ |
77 | struct global_pstate_info { | |
09ca4c9b | 78 | int highest_lpstate_idx; |
eaa2c3ae AA |
79 | unsigned int elapsed_time; |
80 | unsigned int last_sampled_time; | |
09ca4c9b AA |
81 | int last_lpstate_idx; |
82 | int last_gpstate_idx; | |
eaa2c3ae AA |
83 | spinlock_t gpstate_lock; |
84 | struct timer_list timer; | |
1d1fe902 | 85 | struct cpufreq_policy *policy; |
eaa2c3ae AA |
86 | }; |
87 | ||
b3d627a5 | 88 | static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1]; |
332f0a01 | 89 | |
133c6c84 | 90 | static DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER); |
332f0a01 GS |
91 | /** |
92 | * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap | |
93 | * indexed by a function of pstate id. | |
94 | * | |
95 | * @pstate_id: pstate id for this entry. | |
96 | * | |
97 | * @cpufreq_table_idx: Index into the powernv_freqs | |
98 | * cpufreq_frequency_table for frequency | |
99 | * corresponding to pstate_id. | |
100 | * | |
101 | * @hentry: hlist_node that hooks this entry into the pstate_revmap | |
102 | * hashtable | |
103 | */ | |
104 | struct pstate_idx_revmap_data { | |
967b87fd | 105 | u8 pstate_id; |
332f0a01 GS |
106 | unsigned int cpufreq_table_idx; |
107 | struct hlist_node hentry; | |
108 | }; | |
109 | ||
cb166fa9 | 110 | static bool rebooting, throttled, occ_reset; |
b3d627a5 | 111 | |
c89f2682 SB |
112 | static const char * const throttle_reason[] = { |
113 | "No throttling", | |
114 | "Power Cap", | |
115 | "Processor Over Temperature", | |
116 | "Power Supply Failure", | |
117 | "Over Current", | |
118 | "OCC Reset" | |
119 | }; | |
120 | ||
1b028984 SB |
121 | enum throttle_reason_type { |
122 | NO_THROTTLE = 0, | |
123 | POWERCAP, | |
124 | CPU_OVERTEMP, | |
125 | POWER_SUPPLY_FAILURE, | |
126 | OVERCURRENT, | |
127 | OCC_RESET_THROTTLE, | |
128 | OCC_MAX_REASON | |
129 | }; | |
130 | ||
053819e0 SB |
131 | static struct chip { |
132 | unsigned int id; | |
133 | bool throttled; | |
c89f2682 SB |
134 | bool restore; |
135 | u8 throttle_reason; | |
735366fc SB |
136 | cpumask_t mask; |
137 | struct work_struct throttle; | |
1b028984 SB |
138 | int throttle_turbo; |
139 | int throttle_sub_turbo; | |
140 | int reason[OCC_MAX_REASON]; | |
053819e0 SB |
141 | } *chips; |
142 | ||
143 | static int nr_chips; | |
3e5963bc | 144 | static DEFINE_PER_CPU(struct chip *, chip_info); |
053819e0 | 145 | |
b3d627a5 | 146 | /* |
09ca4c9b AA |
147 | * Note: |
148 | * The set of pstates consists of contiguous integers. | |
149 | * powernv_pstate_info stores the index of the frequency table for | |
150 | * max, min and nominal frequencies. It also stores number of | |
151 | * available frequencies. | |
b3d627a5 | 152 | * |
09ca4c9b AA |
153 | * powernv_pstate_info.nominal indicates the index to the highest |
154 | * non-turbo frequency. | |
b3d627a5 VS |
155 | */ |
156 | static struct powernv_pstate_info { | |
09ca4c9b AA |
157 | unsigned int min; |
158 | unsigned int max; | |
159 | unsigned int nominal; | |
160 | unsigned int nr_pstates; | |
b12f7a2b | 161 | bool wof_enabled; |
b3d627a5 VS |
162 | } powernv_pstate_info; |
163 | ||
967b87fd | 164 | static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift) |
ee1f4a7d | 165 | { |
967b87fd | 166 | return ((pmsr_val >> shift) & 0xFF); |
ee1f4a7d GS |
167 | } |
168 | ||
169 | #define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT) | |
170 | #define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT) | |
171 | #define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT) | |
172 | ||
332f0a01 GS |
173 | /* Use following functions for conversions between pstate_id and index */ |
174 | ||
44bd9a30 | 175 | /* |
332f0a01 GS |
176 | * idx_to_pstate : Returns the pstate id corresponding to the |
177 | * frequency in the cpufreq frequency table | |
178 | * powernv_freqs indexed by @i. | |
179 | * | |
180 | * If @i is out of bound, this will return the pstate | |
181 | * corresponding to the nominal frequency. | |
182 | */ | |
967b87fd | 183 | static inline u8 idx_to_pstate(unsigned int i) |
09ca4c9b | 184 | { |
8e859467 | 185 | if (unlikely(i >= powernv_pstate_info.nr_pstates)) { |
332f0a01 | 186 | pr_warn_once("idx_to_pstate: index %u is out of bound\n", i); |
8e859467 AA |
187 | return powernv_freqs[powernv_pstate_info.nominal].driver_data; |
188 | } | |
189 | ||
09ca4c9b AA |
190 | return powernv_freqs[i].driver_data; |
191 | } | |
192 | ||
44bd9a30 | 193 | /* |
332f0a01 GS |
194 | * pstate_to_idx : Returns the index in the cpufreq frequencytable |
195 | * powernv_freqs for the frequency whose corresponding | |
196 | * pstate id is @pstate. | |
197 | * | |
198 | * If no frequency corresponding to @pstate is found, | |
199 | * this will return the index of the nominal | |
200 | * frequency. | |
201 | */ | |
967b87fd | 202 | static unsigned int pstate_to_idx(u8 pstate) |
09ca4c9b | 203 | { |
332f0a01 GS |
204 | unsigned int key = pstate % POWERNV_MAX_PSTATES; |
205 | struct pstate_idx_revmap_data *revmap_data; | |
8e859467 | 206 | |
332f0a01 GS |
207 | hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) { |
208 | if (revmap_data->pstate_id == pstate) | |
209 | return revmap_data->cpufreq_table_idx; | |
8e859467 | 210 | } |
332f0a01 | 211 | |
967b87fd | 212 | pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate); |
332f0a01 | 213 | return powernv_pstate_info.nominal; |
09ca4c9b AA |
214 | } |
215 | ||
eaa2c3ae AA |
216 | static inline void reset_gpstates(struct cpufreq_policy *policy) |
217 | { | |
218 | struct global_pstate_info *gpstates = policy->driver_data; | |
219 | ||
09ca4c9b | 220 | gpstates->highest_lpstate_idx = 0; |
eaa2c3ae AA |
221 | gpstates->elapsed_time = 0; |
222 | gpstates->last_sampled_time = 0; | |
09ca4c9b AA |
223 | gpstates->last_lpstate_idx = 0; |
224 | gpstates->last_gpstate_idx = 0; | |
eaa2c3ae AA |
225 | } |
226 | ||
b3d627a5 VS |
227 | /* |
228 | * Initialize the freq table based on data obtained | |
229 | * from the firmware passed via device-tree | |
230 | */ | |
231 | static int init_powernv_pstates(void) | |
232 | { | |
233 | struct device_node *power_mgt; | |
09ca4c9b | 234 | int i, nr_pstates = 0; |
b3d627a5 VS |
235 | const __be32 *pstate_ids, *pstate_freqs; |
236 | u32 len_ids, len_freqs; | |
09ca4c9b | 237 | u32 pstate_min, pstate_max, pstate_nominal; |
b12f7a2b | 238 | u32 pstate_turbo, pstate_ultra_turbo; |
5ae06c23 | 239 | int rc = -ENODEV; |
b3d627a5 VS |
240 | |
241 | power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); | |
242 | if (!power_mgt) { | |
243 | pr_warn("power-mgt node not found\n"); | |
244 | return -ENODEV; | |
245 | } | |
246 | ||
247 | if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) { | |
248 | pr_warn("ibm,pstate-min node not found\n"); | |
3be466d6 | 249 | goto out; |
b3d627a5 VS |
250 | } |
251 | ||
252 | if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) { | |
253 | pr_warn("ibm,pstate-max node not found\n"); | |
3be466d6 | 254 | goto out; |
b3d627a5 VS |
255 | } |
256 | ||
257 | if (of_property_read_u32(power_mgt, "ibm,pstate-nominal", | |
258 | &pstate_nominal)) { | |
259 | pr_warn("ibm,pstate-nominal not found\n"); | |
3be466d6 | 260 | goto out; |
b3d627a5 | 261 | } |
b12f7a2b SB |
262 | |
263 | if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo", | |
264 | &pstate_ultra_turbo)) { | |
265 | powernv_pstate_info.wof_enabled = false; | |
266 | goto next; | |
267 | } | |
268 | ||
269 | if (of_property_read_u32(power_mgt, "ibm,pstate-turbo", | |
270 | &pstate_turbo)) { | |
271 | powernv_pstate_info.wof_enabled = false; | |
272 | goto next; | |
273 | } | |
274 | ||
275 | if (pstate_turbo == pstate_ultra_turbo) | |
276 | powernv_pstate_info.wof_enabled = false; | |
277 | else | |
278 | powernv_pstate_info.wof_enabled = true; | |
279 | ||
280 | next: | |
967b87fd | 281 | pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min, |
b3d627a5 | 282 | pstate_nominal, pstate_max); |
b12f7a2b SB |
283 | pr_info("Workload Optimized Frequency is %s in the platform\n", |
284 | (powernv_pstate_info.wof_enabled) ? "enabled" : "disabled"); | |
b3d627a5 VS |
285 | |
286 | pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids); | |
287 | if (!pstate_ids) { | |
288 | pr_warn("ibm,pstate-ids not found\n"); | |
3be466d6 | 289 | goto out; |
b3d627a5 VS |
290 | } |
291 | ||
292 | pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz", | |
293 | &len_freqs); | |
294 | if (!pstate_freqs) { | |
295 | pr_warn("ibm,pstate-frequencies-mhz not found\n"); | |
3be466d6 | 296 | goto out; |
b3d627a5 VS |
297 | } |
298 | ||
6174bac8 VS |
299 | if (len_ids != len_freqs) { |
300 | pr_warn("Entries in ibm,pstate-ids and " | |
301 | "ibm,pstate-frequencies-mhz does not match\n"); | |
302 | } | |
303 | ||
b3d627a5 VS |
304 | nr_pstates = min(len_ids, len_freqs) / sizeof(u32); |
305 | if (!nr_pstates) { | |
306 | pr_warn("No PStates found\n"); | |
3be466d6 | 307 | goto out; |
b3d627a5 VS |
308 | } |
309 | ||
09ca4c9b | 310 | powernv_pstate_info.nr_pstates = nr_pstates; |
b3d627a5 | 311 | pr_debug("NR PStates %d\n", nr_pstates); |
ee1f4a7d | 312 | |
b3d627a5 VS |
313 | for (i = 0; i < nr_pstates; i++) { |
314 | u32 id = be32_to_cpu(pstate_ids[i]); | |
315 | u32 freq = be32_to_cpu(pstate_freqs[i]); | |
332f0a01 GS |
316 | struct pstate_idx_revmap_data *revmap_data; |
317 | unsigned int key; | |
b3d627a5 VS |
318 | |
319 | pr_debug("PState id %d freq %d MHz\n", id, freq); | |
320 | powernv_freqs[i].frequency = freq * 1000; /* kHz */ | |
967b87fd | 321 | powernv_freqs[i].driver_data = id & 0xFF; |
09ca4c9b | 322 | |
5ae06c23 YL |
323 | revmap_data = kmalloc(sizeof(*revmap_data), GFP_KERNEL); |
324 | if (!revmap_data) { | |
325 | rc = -ENOMEM; | |
326 | goto out; | |
327 | } | |
332f0a01 | 328 | |
967b87fd | 329 | revmap_data->pstate_id = id & 0xFF; |
332f0a01 | 330 | revmap_data->cpufreq_table_idx = i; |
967b87fd | 331 | key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES; |
332f0a01 GS |
332 | hash_add(pstate_revmap, &revmap_data->hentry, key); |
333 | ||
09ca4c9b AA |
334 | if (id == pstate_max) |
335 | powernv_pstate_info.max = i; | |
3fa4680b | 336 | if (id == pstate_nominal) |
09ca4c9b | 337 | powernv_pstate_info.nominal = i; |
3fa4680b | 338 | if (id == pstate_min) |
09ca4c9b | 339 | powernv_pstate_info.min = i; |
b12f7a2b SB |
340 | |
341 | if (powernv_pstate_info.wof_enabled && id == pstate_turbo) { | |
342 | int j; | |
343 | ||
344 | for (j = i - 1; j >= (int)powernv_pstate_info.max; j--) | |
345 | powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ; | |
346 | } | |
b3d627a5 | 347 | } |
09ca4c9b | 348 | |
b3d627a5 VS |
349 | /* End of list marker entry */ |
350 | powernv_freqs[i].frequency = CPUFREQ_TABLE_END; | |
3be466d6 YL |
351 | |
352 | of_node_put(power_mgt); | |
b3d627a5 | 353 | return 0; |
3be466d6 YL |
354 | out: |
355 | of_node_put(power_mgt); | |
5ae06c23 | 356 | return rc; |
b3d627a5 VS |
357 | } |
358 | ||
359 | /* Returns the CPU frequency corresponding to the pstate_id. */ | |
967b87fd | 360 | static unsigned int pstate_id_to_freq(u8 pstate_id) |
b3d627a5 VS |
361 | { |
362 | int i; | |
363 | ||
09ca4c9b | 364 | i = pstate_to_idx(pstate_id); |
6174bac8 | 365 | if (i >= powernv_pstate_info.nr_pstates || i < 0) { |
967b87fd | 366 | pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n", |
09ca4c9b AA |
367 | pstate_id, idx_to_pstate(powernv_pstate_info.nominal)); |
368 | i = powernv_pstate_info.nominal; | |
6174bac8 | 369 | } |
b3d627a5 VS |
370 | |
371 | return powernv_freqs[i].frequency; | |
372 | } | |
373 | ||
374 | /* | |
375 | * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by | |
376 | * the firmware | |
377 | */ | |
378 | static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy, | |
379 | char *buf) | |
380 | { | |
381 | return sprintf(buf, "%u\n", | |
09ca4c9b | 382 | powernv_freqs[powernv_pstate_info.nominal].frequency); |
b3d627a5 VS |
383 | } |
384 | ||
133c6c84 | 385 | static struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq = |
b3d627a5 VS |
386 | __ATTR_RO(cpuinfo_nominal_freq); |
387 | ||
b12f7a2b SB |
388 | #define SCALING_BOOST_FREQS_ATTR_INDEX 2 |
389 | ||
b3d627a5 VS |
390 | static struct freq_attr *powernv_cpu_freq_attr[] = { |
391 | &cpufreq_freq_attr_scaling_available_freqs, | |
392 | &cpufreq_freq_attr_cpuinfo_nominal_freq, | |
b12f7a2b | 393 | &cpufreq_freq_attr_scaling_boost_freqs, |
b3d627a5 VS |
394 | NULL, |
395 | }; | |
396 | ||
1b028984 SB |
397 | #define throttle_attr(name, member) \ |
398 | static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \ | |
399 | { \ | |
400 | struct chip *chip = per_cpu(chip_info, policy->cpu); \ | |
401 | \ | |
402 | return sprintf(buf, "%u\n", chip->member); \ | |
403 | } \ | |
404 | \ | |
405 | static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \ | |
406 | ||
407 | throttle_attr(unthrottle, reason[NO_THROTTLE]); | |
408 | throttle_attr(powercap, reason[POWERCAP]); | |
409 | throttle_attr(overtemp, reason[CPU_OVERTEMP]); | |
410 | throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]); | |
411 | throttle_attr(overcurrent, reason[OVERCURRENT]); | |
412 | throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]); | |
413 | throttle_attr(turbo_stat, throttle_turbo); | |
414 | throttle_attr(sub_turbo_stat, throttle_sub_turbo); | |
415 | ||
416 | static struct attribute *throttle_attrs[] = { | |
417 | &throttle_attr_unthrottle.attr, | |
418 | &throttle_attr_powercap.attr, | |
419 | &throttle_attr_overtemp.attr, | |
420 | &throttle_attr_supply_fault.attr, | |
421 | &throttle_attr_overcurrent.attr, | |
422 | &throttle_attr_occ_reset.attr, | |
423 | &throttle_attr_turbo_stat.attr, | |
424 | &throttle_attr_sub_turbo_stat.attr, | |
425 | NULL, | |
426 | }; | |
427 | ||
428 | static const struct attribute_group throttle_attr_grp = { | |
429 | .name = "throttle_stats", | |
430 | .attrs = throttle_attrs, | |
431 | }; | |
432 | ||
b3d627a5 VS |
433 | /* Helper routines */ |
434 | ||
435 | /* Access helpers to power mgt SPR */ | |
436 | ||
437 | static inline unsigned long get_pmspr(unsigned long sprn) | |
438 | { | |
439 | switch (sprn) { | |
440 | case SPRN_PMCR: | |
441 | return mfspr(SPRN_PMCR); | |
442 | ||
443 | case SPRN_PMICR: | |
444 | return mfspr(SPRN_PMICR); | |
445 | ||
446 | case SPRN_PMSR: | |
447 | return mfspr(SPRN_PMSR); | |
448 | } | |
449 | BUG(); | |
450 | } | |
451 | ||
452 | static inline void set_pmspr(unsigned long sprn, unsigned long val) | |
453 | { | |
454 | switch (sprn) { | |
455 | case SPRN_PMCR: | |
456 | mtspr(SPRN_PMCR, val); | |
457 | return; | |
458 | ||
459 | case SPRN_PMICR: | |
460 | mtspr(SPRN_PMICR, val); | |
461 | return; | |
462 | } | |
463 | BUG(); | |
464 | } | |
465 | ||
466 | /* | |
467 | * Use objects of this type to query/update | |
468 | * pstates on a remote CPU via smp_call_function. | |
469 | */ | |
470 | struct powernv_smp_call_data { | |
471 | unsigned int freq; | |
967b87fd GS |
472 | u8 pstate_id; |
473 | u8 gpstate_id; | |
b3d627a5 VS |
474 | }; |
475 | ||
476 | /* | |
477 | * powernv_read_cpu_freq: Reads the current frequency on this CPU. | |
478 | * | |
479 | * Called via smp_call_function. | |
480 | * | |
481 | * Note: The caller of the smp_call_function should pass an argument of | |
482 | * the type 'struct powernv_smp_call_data *' along with this function. | |
483 | * | |
484 | * The current frequency on this CPU will be returned via | |
485 | * ((struct powernv_smp_call_data *)arg)->freq; | |
486 | */ | |
487 | static void powernv_read_cpu_freq(void *arg) | |
488 | { | |
489 | unsigned long pmspr_val; | |
b3d627a5 VS |
490 | struct powernv_smp_call_data *freq_data = arg; |
491 | ||
492 | pmspr_val = get_pmspr(SPRN_PMSR); | |
ee1f4a7d | 493 | freq_data->pstate_id = extract_local_pstate(pmspr_val); |
b3d627a5 VS |
494 | freq_data->freq = pstate_id_to_freq(freq_data->pstate_id); |
495 | ||
967b87fd GS |
496 | pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n", |
497 | raw_smp_processor_id(), pmspr_val, freq_data->pstate_id, | |
498 | freq_data->freq); | |
b3d627a5 VS |
499 | } |
500 | ||
501 | /* | |
502 | * powernv_cpufreq_get: Returns the CPU frequency as reported by the | |
503 | * firmware for CPU 'cpu'. This value is reported through the sysfs | |
504 | * file cpuinfo_cur_freq. | |
505 | */ | |
60d1ea4e | 506 | static unsigned int powernv_cpufreq_get(unsigned int cpu) |
b3d627a5 VS |
507 | { |
508 | struct powernv_smp_call_data freq_data; | |
509 | ||
510 | smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq, | |
511 | &freq_data, 1); | |
512 | ||
513 | return freq_data.freq; | |
514 | } | |
515 | ||
516 | /* | |
517 | * set_pstate: Sets the pstate on this CPU. | |
518 | * | |
519 | * This is called via an smp_call_function. | |
520 | * | |
521 | * The caller must ensure that freq_data is of the type | |
522 | * (struct powernv_smp_call_data *) and the pstate_id which needs to be set | |
523 | * on this CPU should be present in freq_data->pstate_id. | |
524 | */ | |
eaa2c3ae | 525 | static void set_pstate(void *data) |
b3d627a5 VS |
526 | { |
527 | unsigned long val; | |
eaa2c3ae AA |
528 | struct powernv_smp_call_data *freq_data = data; |
529 | unsigned long pstate_ul = freq_data->pstate_id; | |
530 | unsigned long gpstate_ul = freq_data->gpstate_id; | |
b3d627a5 VS |
531 | |
532 | val = get_pmspr(SPRN_PMCR); | |
533 | val = val & 0x0000FFFFFFFFFFFFULL; | |
534 | ||
535 | pstate_ul = pstate_ul & 0xFF; | |
eaa2c3ae | 536 | gpstate_ul = gpstate_ul & 0xFF; |
b3d627a5 VS |
537 | |
538 | /* Set both global(bits 56..63) and local(bits 48..55) PStates */ | |
eaa2c3ae | 539 | val = val | (gpstate_ul << 56) | (pstate_ul << 48); |
b3d627a5 VS |
540 | |
541 | pr_debug("Setting cpu %d pmcr to %016lX\n", | |
542 | raw_smp_processor_id(), val); | |
543 | set_pmspr(SPRN_PMCR, val); | |
544 | } | |
545 | ||
cf30af76 SB |
546 | /* |
547 | * get_nominal_index: Returns the index corresponding to the nominal | |
548 | * pstate in the cpufreq table | |
549 | */ | |
550 | static inline unsigned int get_nominal_index(void) | |
551 | { | |
09ca4c9b | 552 | return powernv_pstate_info.nominal; |
cf30af76 SB |
553 | } |
554 | ||
735366fc | 555 | static void powernv_cpufreq_throttle_check(void *data) |
09a972d1 | 556 | { |
3e5963bc | 557 | struct chip *chip; |
735366fc | 558 | unsigned int cpu = smp_processor_id(); |
09a972d1 | 559 | unsigned long pmsr; |
967b87fd | 560 | u8 pmsr_pmax; |
09ca4c9b | 561 | unsigned int pmsr_pmax_idx; |
09a972d1 SB |
562 | |
563 | pmsr = get_pmspr(SPRN_PMSR); | |
3e5963bc | 564 | chip = this_cpu_read(chip_info); |
053819e0 | 565 | |
09a972d1 | 566 | /* Check for Pmax Capping */ |
ee1f4a7d | 567 | pmsr_pmax = extract_max_pstate(pmsr); |
09ca4c9b AA |
568 | pmsr_pmax_idx = pstate_to_idx(pmsr_pmax); |
569 | if (pmsr_pmax_idx != powernv_pstate_info.max) { | |
3e5963bc | 570 | if (chip->throttled) |
053819e0 | 571 | goto next; |
3e5963bc | 572 | chip->throttled = true; |
09ca4c9b | 573 | if (pmsr_pmax_idx > powernv_pstate_info.nominal) { |
967b87fd | 574 | pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n", |
3e5963bc | 575 | cpu, chip->id, pmsr_pmax, |
09ca4c9b | 576 | idx_to_pstate(powernv_pstate_info.nominal)); |
1b028984 SB |
577 | chip->throttle_sub_turbo++; |
578 | } else { | |
579 | chip->throttle_turbo++; | |
580 | } | |
3e5963bc MN |
581 | trace_powernv_throttle(chip->id, |
582 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 583 | pmsr_pmax); |
3e5963bc MN |
584 | } else if (chip->throttled) { |
585 | chip->throttled = false; | |
586 | trace_powernv_throttle(chip->id, | |
587 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 588 | pmsr_pmax); |
09a972d1 SB |
589 | } |
590 | ||
3dd3ebe5 | 591 | /* Check if Psafe_mode_active is set in PMSR. */ |
053819e0 | 592 | next: |
3dd3ebe5 | 593 | if (pmsr & PMSR_PSAFE_ENABLE) { |
09a972d1 SB |
594 | throttled = true; |
595 | pr_info("Pstate set to safe frequency\n"); | |
596 | } | |
597 | ||
598 | /* Check if SPR_EM_DISABLE is set in PMSR */ | |
599 | if (pmsr & PMSR_SPR_EM_DISABLE) { | |
600 | throttled = true; | |
601 | pr_info("Frequency Control disabled from OS\n"); | |
602 | } | |
603 | ||
604 | if (throttled) { | |
605 | pr_info("PMSR = %16lx\n", pmsr); | |
c89f2682 | 606 | pr_warn("CPU Frequency could be throttled\n"); |
09a972d1 SB |
607 | } |
608 | } | |
609 | ||
eaa2c3ae AA |
610 | /** |
611 | * calc_global_pstate - Calculate global pstate | |
09ca4c9b AA |
612 | * @elapsed_time: Elapsed time in milliseconds |
613 | * @local_pstate_idx: New local pstate | |
614 | * @highest_lpstate_idx: pstate from which its ramping down | |
eaa2c3ae AA |
615 | * |
616 | * Finds the appropriate global pstate based on the pstate from which its | |
617 | * ramping down and the time elapsed in ramping down. It follows a quadratic | |
618 | * equation which ensures that it reaches ramping down to pmin in 5sec. | |
619 | */ | |
620 | static inline int calc_global_pstate(unsigned int elapsed_time, | |
09ca4c9b AA |
621 | int highest_lpstate_idx, |
622 | int local_pstate_idx) | |
eaa2c3ae | 623 | { |
09ca4c9b | 624 | int index_diff; |
eaa2c3ae AA |
625 | |
626 | /* | |
627 | * Using ramp_down_percent we get the percentage of rampdown | |
628 | * that we are expecting to be dropping. Difference between | |
09ca4c9b | 629 | * highest_lpstate_idx and powernv_pstate_info.min will give a absolute |
eaa2c3ae AA |
630 | * number of how many pstates we will drop eventually by the end of |
631 | * 5 seconds, then just scale it get the number pstates to be dropped. | |
632 | */ | |
09ca4c9b AA |
633 | index_diff = ((int)ramp_down_percent(elapsed_time) * |
634 | (powernv_pstate_info.min - highest_lpstate_idx)) / 100; | |
eaa2c3ae AA |
635 | |
636 | /* Ensure that global pstate is >= to local pstate */ | |
09ca4c9b AA |
637 | if (highest_lpstate_idx + index_diff >= local_pstate_idx) |
638 | return local_pstate_idx; | |
eaa2c3ae | 639 | else |
09ca4c9b | 640 | return highest_lpstate_idx + index_diff; |
eaa2c3ae AA |
641 | } |
642 | ||
643 | static inline void queue_gpstate_timer(struct global_pstate_info *gpstates) | |
644 | { | |
645 | unsigned int timer_interval; | |
646 | ||
647 | /* | |
648 | * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But | |
649 | * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time. | |
650 | * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME | |
651 | * seconds of ramp down time. | |
652 | */ | |
653 | if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL) | |
654 | > MAX_RAMP_DOWN_TIME) | |
655 | timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time; | |
656 | else | |
657 | timer_interval = GPSTATE_TIMER_INTERVAL; | |
658 | ||
7bc54b65 | 659 | mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval)); |
eaa2c3ae AA |
660 | } |
661 | ||
662 | /** | |
663 | * gpstate_timer_handler | |
664 | * | |
44bd9a30 | 665 | * @t: Timer context used to fetch global pstate info struct |
eaa2c3ae AA |
666 | * |
667 | * This handler brings down the global pstate closer to the local pstate | |
668 | * according quadratic equation. Queues a new timer if it is still not equal | |
669 | * to local pstate | |
670 | */ | |
133c6c84 | 671 | static void gpstate_timer_handler(struct timer_list *t) |
eaa2c3ae | 672 | { |
1d1fe902 KC |
673 | struct global_pstate_info *gpstates = from_timer(gpstates, t, timer); |
674 | struct cpufreq_policy *policy = gpstates->policy; | |
20b15b76 AA |
675 | int gpstate_idx, lpstate_idx; |
676 | unsigned long val; | |
eaa2c3ae AA |
677 | unsigned int time_diff = jiffies_to_msecs(jiffies) |
678 | - gpstates->last_sampled_time; | |
679 | struct powernv_smp_call_data freq_data; | |
680 | ||
681 | if (!spin_trylock(&gpstates->gpstate_lock)) | |
682 | return; | |
c0f7f5b6 SB |
683 | /* |
684 | * If the timer has migrated to the different cpu then bring | |
685 | * it back to one of the policy->cpus | |
686 | */ | |
687 | if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) { | |
688 | gpstates->timer.expires = jiffies + msecs_to_jiffies(1); | |
689 | add_timer_on(&gpstates->timer, cpumask_first(policy->cpus)); | |
690 | spin_unlock(&gpstates->gpstate_lock); | |
691 | return; | |
692 | } | |
eaa2c3ae | 693 | |
20b15b76 AA |
694 | /* |
695 | * If PMCR was last updated was using fast_swtich then | |
696 | * We may have wrong in gpstate->last_lpstate_idx | |
697 | * value. Hence, read from PMCR to get correct data. | |
698 | */ | |
699 | val = get_pmspr(SPRN_PMCR); | |
ee1f4a7d GS |
700 | freq_data.gpstate_id = extract_global_pstate(val); |
701 | freq_data.pstate_id = extract_local_pstate(val); | |
20b15b76 AA |
702 | if (freq_data.gpstate_id == freq_data.pstate_id) { |
703 | reset_gpstates(policy); | |
704 | spin_unlock(&gpstates->gpstate_lock); | |
705 | return; | |
706 | } | |
707 | ||
eaa2c3ae AA |
708 | gpstates->last_sampled_time += time_diff; |
709 | gpstates->elapsed_time += time_diff; | |
eaa2c3ae | 710 | |
20b15b76 | 711 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { |
09ca4c9b | 712 | gpstate_idx = pstate_to_idx(freq_data.pstate_id); |
c9a81e68 | 713 | lpstate_idx = gpstate_idx; |
eaa2c3ae | 714 | reset_gpstates(policy); |
09ca4c9b | 715 | gpstates->highest_lpstate_idx = gpstate_idx; |
eaa2c3ae | 716 | } else { |
20b15b76 | 717 | lpstate_idx = pstate_to_idx(freq_data.pstate_id); |
09ca4c9b AA |
718 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
719 | gpstates->highest_lpstate_idx, | |
20b15b76 | 720 | lpstate_idx); |
eaa2c3ae | 721 | } |
20b15b76 AA |
722 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
723 | gpstates->last_gpstate_idx = gpstate_idx; | |
724 | gpstates->last_lpstate_idx = lpstate_idx; | |
eaa2c3ae AA |
725 | /* |
726 | * If local pstate is equal to global pstate, rampdown is over | |
727 | * So timer is not required to be queued. | |
728 | */ | |
09ca4c9b | 729 | if (gpstate_idx != gpstates->last_lpstate_idx) |
eaa2c3ae AA |
730 | queue_gpstate_timer(gpstates); |
731 | ||
c0f7f5b6 | 732 | set_pstate(&freq_data); |
1fd3ff28 | 733 | spin_unlock(&gpstates->gpstate_lock); |
eaa2c3ae AA |
734 | } |
735 | ||
b3d627a5 VS |
736 | /* |
737 | * powernv_cpufreq_target_index: Sets the frequency corresponding to | |
738 | * the cpufreq table entry indexed by new_index on the cpus in the | |
739 | * mask policy->cpus | |
740 | */ | |
741 | static int powernv_cpufreq_target_index(struct cpufreq_policy *policy, | |
742 | unsigned int new_index) | |
743 | { | |
744 | struct powernv_smp_call_data freq_data; | |
09ca4c9b | 745 | unsigned int cur_msec, gpstate_idx; |
eaa2c3ae | 746 | struct global_pstate_info *gpstates = policy->driver_data; |
b3d627a5 | 747 | |
cf30af76 SB |
748 | if (unlikely(rebooting) && new_index != get_nominal_index()) |
749 | return 0; | |
750 | ||
8a10c06a DK |
751 | if (!throttled) { |
752 | /* we don't want to be preempted while | |
753 | * checking if the CPU frequency has been throttled | |
754 | */ | |
755 | preempt_disable(); | |
735366fc | 756 | powernv_cpufreq_throttle_check(NULL); |
8a10c06a DK |
757 | preempt_enable(); |
758 | } | |
09a972d1 | 759 | |
eaa2c3ae AA |
760 | cur_msec = jiffies_to_msecs(get_jiffies_64()); |
761 | ||
09ca4c9b | 762 | freq_data.pstate_id = idx_to_pstate(new_index); |
dcb14337 SB |
763 | if (!gpstates) { |
764 | freq_data.gpstate_id = freq_data.pstate_id; | |
765 | goto no_gpstate; | |
766 | } | |
767 | ||
768 | spin_lock(&gpstates->gpstate_lock); | |
b3d627a5 | 769 | |
eaa2c3ae | 770 | if (!gpstates->last_sampled_time) { |
09ca4c9b AA |
771 | gpstate_idx = new_index; |
772 | gpstates->highest_lpstate_idx = new_index; | |
eaa2c3ae AA |
773 | goto gpstates_done; |
774 | } | |
775 | ||
09ca4c9b | 776 | if (gpstates->last_gpstate_idx < new_index) { |
eaa2c3ae AA |
777 | gpstates->elapsed_time += cur_msec - |
778 | gpstates->last_sampled_time; | |
779 | ||
780 | /* | |
781 | * If its has been ramping down for more than MAX_RAMP_DOWN_TIME | |
782 | * we should be resetting all global pstate related data. Set it | |
783 | * equal to local pstate to start fresh. | |
784 | */ | |
785 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { | |
786 | reset_gpstates(policy); | |
09ca4c9b AA |
787 | gpstates->highest_lpstate_idx = new_index; |
788 | gpstate_idx = new_index; | |
eaa2c3ae AA |
789 | } else { |
790 | /* Elaspsed_time is less than 5 seconds, continue to rampdown */ | |
09ca4c9b AA |
791 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
792 | gpstates->highest_lpstate_idx, | |
793 | new_index); | |
eaa2c3ae AA |
794 | } |
795 | } else { | |
796 | reset_gpstates(policy); | |
09ca4c9b AA |
797 | gpstates->highest_lpstate_idx = new_index; |
798 | gpstate_idx = new_index; | |
eaa2c3ae AA |
799 | } |
800 | ||
801 | /* | |
802 | * If local pstate is equal to global pstate, rampdown is over | |
803 | * So timer is not required to be queued. | |
804 | */ | |
09ca4c9b | 805 | if (gpstate_idx != new_index) |
eaa2c3ae | 806 | queue_gpstate_timer(gpstates); |
0bc10b93 AA |
807 | else |
808 | del_timer_sync(&gpstates->timer); | |
eaa2c3ae AA |
809 | |
810 | gpstates_done: | |
09ca4c9b | 811 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
eaa2c3ae | 812 | gpstates->last_sampled_time = cur_msec; |
09ca4c9b AA |
813 | gpstates->last_gpstate_idx = gpstate_idx; |
814 | gpstates->last_lpstate_idx = new_index; | |
eaa2c3ae | 815 | |
1fd3ff28 AA |
816 | spin_unlock(&gpstates->gpstate_lock); |
817 | ||
dcb14337 | 818 | no_gpstate: |
b3d627a5 VS |
819 | /* |
820 | * Use smp_call_function to send IPI and execute the | |
821 | * mtspr on target CPU. We could do that without IPI | |
822 | * if current CPU is within policy->cpus (core) | |
823 | */ | |
824 | smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1); | |
b3d627a5 VS |
825 | return 0; |
826 | } | |
827 | ||
828 | static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
829 | { | |
bf14721c | 830 | int base, i; |
2920e9ce | 831 | struct kernfs_node *kn; |
eaa2c3ae | 832 | struct global_pstate_info *gpstates; |
b3d627a5 VS |
833 | |
834 | base = cpu_first_thread_sibling(policy->cpu); | |
835 | ||
836 | for (i = 0; i < threads_per_core; i++) | |
837 | cpumask_set_cpu(base + i, policy->cpus); | |
838 | ||
2920e9ce SB |
839 | kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name); |
840 | if (!kn) { | |
1b028984 SB |
841 | int ret; |
842 | ||
843 | ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp); | |
844 | if (ret) { | |
845 | pr_info("Failed to create throttle stats directory for cpu %d\n", | |
846 | policy->cpu); | |
847 | return ret; | |
848 | } | |
2920e9ce SB |
849 | } else { |
850 | kernfs_put(kn); | |
1b028984 | 851 | } |
eaa2c3ae | 852 | |
dcb14337 SB |
853 | policy->freq_table = powernv_freqs; |
854 | policy->fast_switch_possible = true; | |
855 | ||
856 | if (pvr_version_is(PVR_POWER9)) | |
857 | return 0; | |
858 | ||
859 | /* Initialise Gpstate ramp-down timer only on POWER8 */ | |
eaa2c3ae AA |
860 | gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL); |
861 | if (!gpstates) | |
862 | return -ENOMEM; | |
863 | ||
864 | policy->driver_data = gpstates; | |
865 | ||
866 | /* initialize timer */ | |
1d1fe902 KC |
867 | gpstates->policy = policy; |
868 | timer_setup(&gpstates->timer, gpstate_timer_handler, | |
869 | TIMER_PINNED | TIMER_DEFERRABLE); | |
eaa2c3ae AA |
870 | gpstates->timer.expires = jiffies + |
871 | msecs_to_jiffies(GPSTATE_TIMER_INTERVAL); | |
872 | spin_lock_init(&gpstates->gpstate_lock); | |
eaa2c3ae | 873 | |
bf14721c | 874 | return 0; |
eaa2c3ae AA |
875 | } |
876 | ||
877 | static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy) | |
878 | { | |
952da0c9 VK |
879 | struct powernv_smp_call_data freq_data; |
880 | struct global_pstate_info *gpstates = policy->driver_data; | |
881 | ||
882 | freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min); | |
883 | freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min); | |
884 | smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1); | |
885 | if (gpstates) | |
886 | del_timer_sync(&gpstates->timer); | |
887 | ||
eaa2c3ae AA |
888 | kfree(policy->driver_data); |
889 | ||
890 | return 0; | |
b3d627a5 VS |
891 | } |
892 | ||
cf30af76 SB |
893 | static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb, |
894 | unsigned long action, void *unused) | |
895 | { | |
896 | int cpu; | |
a2d0230b | 897 | struct cpufreq_policy *cpu_policy; |
cf30af76 SB |
898 | |
899 | rebooting = true; | |
900 | for_each_online_cpu(cpu) { | |
a2d0230b SD |
901 | cpu_policy = cpufreq_cpu_get(cpu); |
902 | if (!cpu_policy) | |
903 | continue; | |
904 | powernv_cpufreq_target_index(cpu_policy, get_nominal_index()); | |
905 | cpufreq_cpu_put(cpu_policy); | |
cf30af76 SB |
906 | } |
907 | ||
908 | return NOTIFY_DONE; | |
909 | } | |
910 | ||
911 | static struct notifier_block powernv_cpufreq_reboot_nb = { | |
912 | .notifier_call = powernv_cpufreq_reboot_notifier, | |
913 | }; | |
914 | ||
133c6c84 | 915 | static void powernv_cpufreq_work_fn(struct work_struct *work) |
735366fc SB |
916 | { |
917 | struct chip *chip = container_of(work, struct chip, throttle); | |
d95fe371 | 918 | struct cpufreq_policy *policy; |
22794280 | 919 | unsigned int cpu; |
6d167a44 | 920 | cpumask_t mask; |
735366fc | 921 | |
09681a07 | 922 | cpus_read_lock(); |
6d167a44 SB |
923 | cpumask_and(&mask, &chip->mask, cpu_online_mask); |
924 | smp_call_function_any(&mask, | |
735366fc | 925 | powernv_cpufreq_throttle_check, NULL, 0); |
22794280 SB |
926 | |
927 | if (!chip->restore) | |
6d167a44 | 928 | goto out; |
22794280 SB |
929 | |
930 | chip->restore = false; | |
6d167a44 SB |
931 | for_each_cpu(cpu, &mask) { |
932 | int index; | |
22794280 | 933 | |
d95fe371 PRS |
934 | policy = cpufreq_cpu_get(cpu); |
935 | if (!policy) | |
936 | continue; | |
1f39fa0d | 937 | index = cpufreq_table_find_index_c(policy, policy->cur, false); |
d95fe371 PRS |
938 | powernv_cpufreq_target_index(policy, index); |
939 | cpumask_andnot(&mask, &mask, policy->cpus); | |
940 | cpufreq_cpu_put(policy); | |
22794280 | 941 | } |
6d167a44 | 942 | out: |
09681a07 | 943 | cpus_read_unlock(); |
735366fc SB |
944 | } |
945 | ||
cb166fa9 SB |
946 | static int powernv_cpufreq_occ_msg(struct notifier_block *nb, |
947 | unsigned long msg_type, void *_msg) | |
948 | { | |
949 | struct opal_msg *msg = _msg; | |
950 | struct opal_occ_msg omsg; | |
735366fc | 951 | int i; |
cb166fa9 SB |
952 | |
953 | if (msg_type != OPAL_MSG_OCC) | |
954 | return 0; | |
955 | ||
956 | omsg.type = be64_to_cpu(msg->params[0]); | |
957 | ||
958 | switch (omsg.type) { | |
959 | case OCC_RESET: | |
960 | occ_reset = true; | |
309d0631 | 961 | pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n"); |
cb166fa9 SB |
962 | /* |
963 | * powernv_cpufreq_throttle_check() is called in | |
964 | * target() callback which can detect the throttle state | |
965 | * for governors like ondemand. | |
966 | * But static governors will not call target() often thus | |
967 | * report throttling here. | |
968 | */ | |
969 | if (!throttled) { | |
970 | throttled = true; | |
c89f2682 | 971 | pr_warn("CPU frequency is throttled for duration\n"); |
cb166fa9 | 972 | } |
309d0631 | 973 | |
cb166fa9 SB |
974 | break; |
975 | case OCC_LOAD: | |
309d0631 | 976 | pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n"); |
cb166fa9 SB |
977 | break; |
978 | case OCC_THROTTLE: | |
979 | omsg.chip = be64_to_cpu(msg->params[1]); | |
980 | omsg.throttle_status = be64_to_cpu(msg->params[2]); | |
981 | ||
982 | if (occ_reset) { | |
983 | occ_reset = false; | |
984 | throttled = false; | |
309d0631 | 985 | pr_info("OCC Active, CPU frequency is no longer throttled\n"); |
735366fc | 986 | |
22794280 SB |
987 | for (i = 0; i < nr_chips; i++) { |
988 | chips[i].restore = true; | |
735366fc | 989 | schedule_work(&chips[i].throttle); |
22794280 | 990 | } |
735366fc | 991 | |
cb166fa9 SB |
992 | return 0; |
993 | } | |
994 | ||
c89f2682 SB |
995 | for (i = 0; i < nr_chips; i++) |
996 | if (chips[i].id == omsg.chip) | |
997 | break; | |
998 | ||
999 | if (omsg.throttle_status >= 0 && | |
1b028984 | 1000 | omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) { |
c89f2682 | 1001 | chips[i].throttle_reason = omsg.throttle_status; |
1b028984 SB |
1002 | chips[i].reason[omsg.throttle_status]++; |
1003 | } | |
735366fc | 1004 | |
c89f2682 SB |
1005 | if (!omsg.throttle_status) |
1006 | chips[i].restore = true; | |
1007 | ||
1008 | schedule_work(&chips[i].throttle); | |
cb166fa9 SB |
1009 | } |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | static struct notifier_block powernv_cpufreq_opal_nb = { | |
1014 | .notifier_call = powernv_cpufreq_occ_msg, | |
1015 | .next = NULL, | |
1016 | .priority = 0, | |
1017 | }; | |
1018 | ||
60c9efb8 AA |
1019 | static unsigned int powernv_fast_switch(struct cpufreq_policy *policy, |
1020 | unsigned int target_freq) | |
1021 | { | |
1022 | int index; | |
1023 | struct powernv_smp_call_data freq_data; | |
1024 | ||
1f39fa0d | 1025 | index = cpufreq_table_find_index_dl(policy, target_freq, false); |
60c9efb8 AA |
1026 | freq_data.pstate_id = powernv_freqs[index].driver_data; |
1027 | freq_data.gpstate_id = powernv_freqs[index].driver_data; | |
1028 | set_pstate(&freq_data); | |
1029 | ||
1030 | return powernv_freqs[index].frequency; | |
1031 | } | |
1032 | ||
b3d627a5 VS |
1033 | static struct cpufreq_driver powernv_cpufreq_driver = { |
1034 | .name = "powernv-cpufreq", | |
1035 | .flags = CPUFREQ_CONST_LOOPS, | |
1036 | .init = powernv_cpufreq_cpu_init, | |
eaa2c3ae | 1037 | .exit = powernv_cpufreq_cpu_exit, |
b3d627a5 VS |
1038 | .verify = cpufreq_generic_frequency_table_verify, |
1039 | .target_index = powernv_cpufreq_target_index, | |
60c9efb8 | 1040 | .fast_switch = powernv_fast_switch, |
b3d627a5 VS |
1041 | .get = powernv_cpufreq_get, |
1042 | .attr = powernv_cpu_freq_attr, | |
1043 | }; | |
1044 | ||
053819e0 SB |
1045 | static int init_chip_info(void) |
1046 | { | |
db0d32d8 | 1047 | unsigned int *chip; |
053819e0 SB |
1048 | unsigned int cpu, i; |
1049 | unsigned int prev_chip_id = UINT_MAX; | |
f34ee9cb | 1050 | cpumask_t *chip_cpu_mask; |
db0d32d8 JH |
1051 | int ret = 0; |
1052 | ||
1053 | chip = kcalloc(num_possible_cpus(), sizeof(*chip), GFP_KERNEL); | |
1054 | if (!chip) | |
1055 | return -ENOMEM; | |
96c4726f | 1056 | |
f34ee9cb PS |
1057 | /* Allocate a chip cpu mask large enough to fit mask for all chips */ |
1058 | chip_cpu_mask = kcalloc(MAX_NR_CHIPS, sizeof(cpumask_t), GFP_KERNEL); | |
1059 | if (!chip_cpu_mask) { | |
1060 | ret = -ENOMEM; | |
1061 | goto free_and_return; | |
1062 | } | |
1063 | ||
3e5963bc | 1064 | for_each_possible_cpu(cpu) { |
053819e0 SB |
1065 | unsigned int id = cpu_to_chip_id(cpu); |
1066 | ||
1067 | if (prev_chip_id != id) { | |
1068 | prev_chip_id = id; | |
1069 | chip[nr_chips++] = id; | |
1070 | } | |
f34ee9cb | 1071 | cpumask_set_cpu(cpu, &chip_cpu_mask[nr_chips-1]); |
053819e0 SB |
1072 | } |
1073 | ||
c89f2682 | 1074 | chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL); |
db0d32d8 JH |
1075 | if (!chips) { |
1076 | ret = -ENOMEM; | |
f34ee9cb | 1077 | goto out_free_chip_cpu_mask; |
db0d32d8 | 1078 | } |
053819e0 SB |
1079 | |
1080 | for (i = 0; i < nr_chips; i++) { | |
1081 | chips[i].id = chip[i]; | |
f34ee9cb | 1082 | cpumask_copy(&chips[i].mask, &chip_cpu_mask[i]); |
735366fc | 1083 | INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn); |
3e5963bc MN |
1084 | for_each_cpu(cpu, &chips[i].mask) |
1085 | per_cpu(chip_info, cpu) = &chips[i]; | |
053819e0 SB |
1086 | } |
1087 | ||
f34ee9cb PS |
1088 | out_free_chip_cpu_mask: |
1089 | kfree(chip_cpu_mask); | |
db0d32d8 JH |
1090 | free_and_return: |
1091 | kfree(chip); | |
1092 | return ret; | |
053819e0 SB |
1093 | } |
1094 | ||
c5e29ea7 SB |
1095 | static inline void clean_chip_info(void) |
1096 | { | |
d0a72efa OH |
1097 | int i; |
1098 | ||
1099 | /* flush any pending work items */ | |
1100 | if (chips) | |
1101 | for (i = 0; i < nr_chips; i++) | |
1102 | cancel_work_sync(&chips[i].throttle); | |
c5e29ea7 | 1103 | kfree(chips); |
c5e29ea7 SB |
1104 | } |
1105 | ||
1106 | static inline void unregister_all_notifiers(void) | |
1107 | { | |
1108 | opal_message_notifier_unregister(OPAL_MSG_OCC, | |
1109 | &powernv_cpufreq_opal_nb); | |
1110 | unregister_reboot_notifier(&powernv_cpufreq_reboot_nb); | |
1111 | } | |
1112 | ||
b3d627a5 VS |
1113 | static int __init powernv_cpufreq_init(void) |
1114 | { | |
1115 | int rc = 0; | |
1116 | ||
6174bac8 | 1117 | /* Don't probe on pseries (guest) platforms */ |
e4d54f71 | 1118 | if (!firmware_has_feature(FW_FEATURE_OPAL)) |
6174bac8 VS |
1119 | return -ENODEV; |
1120 | ||
b3d627a5 VS |
1121 | /* Discover pstates from device tree and init */ |
1122 | rc = init_powernv_pstates(); | |
c5e29ea7 SB |
1123 | if (rc) |
1124 | goto out; | |
b3d627a5 | 1125 | |
053819e0 SB |
1126 | /* Populate chip info */ |
1127 | rc = init_chip_info(); | |
1128 | if (rc) | |
c5e29ea7 | 1129 | goto out; |
053819e0 | 1130 | |
b12f7a2b SB |
1131 | if (powernv_pstate_info.wof_enabled) |
1132 | powernv_cpufreq_driver.boost_enabled = true; | |
1133 | else | |
1134 | powernv_cpu_freq_attr[SCALING_BOOST_FREQS_ATTR_INDEX] = NULL; | |
1135 | ||
c5e29ea7 | 1136 | rc = cpufreq_register_driver(&powernv_cpufreq_driver); |
b12f7a2b SB |
1137 | if (rc) { |
1138 | pr_info("Failed to register the cpufreq driver (%d)\n", rc); | |
966c08de | 1139 | goto cleanup; |
b12f7a2b | 1140 | } |
c5e29ea7 | 1141 | |
b12f7a2b SB |
1142 | if (powernv_pstate_info.wof_enabled) |
1143 | cpufreq_enable_boost_support(); | |
1144 | ||
966c08de OH |
1145 | register_reboot_notifier(&powernv_cpufreq_reboot_nb); |
1146 | opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb); | |
1147 | ||
b12f7a2b | 1148 | return 0; |
966c08de | 1149 | cleanup: |
c5e29ea7 SB |
1150 | clean_chip_info(); |
1151 | out: | |
1152 | pr_info("Platform driver disabled. System does not support PState control\n"); | |
1153 | return rc; | |
b3d627a5 VS |
1154 | } |
1155 | module_init(powernv_cpufreq_init); | |
1156 | ||
1157 | static void __exit powernv_cpufreq_exit(void) | |
1158 | { | |
1159 | cpufreq_unregister_driver(&powernv_cpufreq_driver); | |
c5e29ea7 SB |
1160 | unregister_all_notifiers(); |
1161 | clean_chip_info(); | |
b3d627a5 VS |
1162 | } |
1163 | module_exit(powernv_cpufreq_exit); | |
1164 | ||
1165 | MODULE_LICENSE("GPL"); | |
1166 | MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>"); |