Merge tag 'driver-core-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / cpufreq / powernv-cpufreq.c
CommitLineData
b3d627a5
VS
1/*
2 * POWERNV cpufreq driver for the IBM POWER processors
3 *
4 * (C) Copyright IBM 2014
5 *
6 * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#define pr_fmt(fmt) "powernv-cpufreq: " fmt
21
22#include <linux/kernel.h>
23#include <linux/sysfs.h>
24#include <linux/cpumask.h>
25#include <linux/module.h>
26#include <linux/cpufreq.h>
27#include <linux/smp.h>
28#include <linux/of.h>
cf30af76 29#include <linux/reboot.h>
053819e0 30#include <linux/slab.h>
6d167a44 31#include <linux/cpu.h>
332f0a01 32#include <linux/hashtable.h>
c89f2682 33#include <trace/events/power.h>
b3d627a5
VS
34
35#include <asm/cputhreads.h>
6174bac8 36#include <asm/firmware.h>
b3d627a5 37#include <asm/reg.h>
f3cae355 38#include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
cb166fa9 39#include <asm/opal.h>
eaa2c3ae 40#include <linux/timer.h>
b3d627a5 41
332f0a01
GS
42#define POWERNV_MAX_PSTATES_ORDER 8
43#define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER))
09a972d1
SB
44#define PMSR_PSAFE_ENABLE (1UL << 30)
45#define PMSR_SPR_EM_DISABLE (1UL << 31)
ee1f4a7d 46#define MAX_PSTATE_SHIFT 32
20b15b76
AA
47#define LPSTATE_SHIFT 48
48#define GPSTATE_SHIFT 56
b3d627a5 49
eaa2c3ae
AA
50#define MAX_RAMP_DOWN_TIME 5120
51/*
52 * On an idle system we want the global pstate to ramp-down from max value to
53 * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
54 * then ramp-down rapidly later on.
55 *
56 * This gives a percentage rampdown for time elapsed in milliseconds.
57 * ramp_down_percentage = ((ms * ms) >> 18)
58 * ~= 3.8 * (sec * sec)
59 *
60 * At 0 ms ramp_down_percent = 0
61 * At 5120 ms ramp_down_percent = 100
62 */
63#define ramp_down_percent(time) ((time * time) >> 18)
64
65/* Interval after which the timer is queued to bring down global pstate */
66#define GPSTATE_TIMER_INTERVAL 2000
67
68/**
69 * struct global_pstate_info - Per policy data structure to maintain history of
70 * global pstates
09ca4c9b
AA
71 * @highest_lpstate_idx: The local pstate index from which we are
72 * ramping down
eaa2c3ae 73 * @elapsed_time: Time in ms spent in ramping down from
09ca4c9b 74 * highest_lpstate_idx
eaa2c3ae
AA
75 * @last_sampled_time: Time from boot in ms when global pstates were
76 * last set
09ca4c9b
AA
77 * @last_lpstate_idx, Last set value of local pstate and global
78 * last_gpstate_idx pstate in terms of cpufreq table index
eaa2c3ae
AA
79 * @timer: Is used for ramping down if cpu goes idle for
80 * a long time with global pstate held high
81 * @gpstate_lock: A spinlock to maintain synchronization between
82 * routines called by the timer handler and
83 * governer's target_index calls
84 */
85struct global_pstate_info {
09ca4c9b 86 int highest_lpstate_idx;
eaa2c3ae
AA
87 unsigned int elapsed_time;
88 unsigned int last_sampled_time;
09ca4c9b
AA
89 int last_lpstate_idx;
90 int last_gpstate_idx;
eaa2c3ae
AA
91 spinlock_t gpstate_lock;
92 struct timer_list timer;
1d1fe902 93 struct cpufreq_policy *policy;
eaa2c3ae
AA
94};
95
b3d627a5 96static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
332f0a01
GS
97
98DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER);
99/**
100 * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap
101 * indexed by a function of pstate id.
102 *
103 * @pstate_id: pstate id for this entry.
104 *
105 * @cpufreq_table_idx: Index into the powernv_freqs
106 * cpufreq_frequency_table for frequency
107 * corresponding to pstate_id.
108 *
109 * @hentry: hlist_node that hooks this entry into the pstate_revmap
110 * hashtable
111 */
112struct pstate_idx_revmap_data {
967b87fd 113 u8 pstate_id;
332f0a01
GS
114 unsigned int cpufreq_table_idx;
115 struct hlist_node hentry;
116};
117
cb166fa9 118static bool rebooting, throttled, occ_reset;
b3d627a5 119
c89f2682
SB
120static const char * const throttle_reason[] = {
121 "No throttling",
122 "Power Cap",
123 "Processor Over Temperature",
124 "Power Supply Failure",
125 "Over Current",
126 "OCC Reset"
127};
128
1b028984
SB
129enum throttle_reason_type {
130 NO_THROTTLE = 0,
131 POWERCAP,
132 CPU_OVERTEMP,
133 POWER_SUPPLY_FAILURE,
134 OVERCURRENT,
135 OCC_RESET_THROTTLE,
136 OCC_MAX_REASON
137};
138
053819e0
SB
139static struct chip {
140 unsigned int id;
141 bool throttled;
c89f2682
SB
142 bool restore;
143 u8 throttle_reason;
735366fc
SB
144 cpumask_t mask;
145 struct work_struct throttle;
1b028984
SB
146 int throttle_turbo;
147 int throttle_sub_turbo;
148 int reason[OCC_MAX_REASON];
053819e0
SB
149} *chips;
150
151static int nr_chips;
3e5963bc 152static DEFINE_PER_CPU(struct chip *, chip_info);
053819e0 153
b3d627a5 154/*
09ca4c9b
AA
155 * Note:
156 * The set of pstates consists of contiguous integers.
157 * powernv_pstate_info stores the index of the frequency table for
158 * max, min and nominal frequencies. It also stores number of
159 * available frequencies.
b3d627a5 160 *
09ca4c9b
AA
161 * powernv_pstate_info.nominal indicates the index to the highest
162 * non-turbo frequency.
b3d627a5
VS
163 */
164static struct powernv_pstate_info {
09ca4c9b
AA
165 unsigned int min;
166 unsigned int max;
167 unsigned int nominal;
168 unsigned int nr_pstates;
b12f7a2b 169 bool wof_enabled;
b3d627a5
VS
170} powernv_pstate_info;
171
967b87fd 172static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift)
ee1f4a7d 173{
967b87fd 174 return ((pmsr_val >> shift) & 0xFF);
ee1f4a7d
GS
175}
176
177#define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT)
178#define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT)
179#define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT)
180
332f0a01
GS
181/* Use following functions for conversions between pstate_id and index */
182
183/**
184 * idx_to_pstate : Returns the pstate id corresponding to the
185 * frequency in the cpufreq frequency table
186 * powernv_freqs indexed by @i.
187 *
188 * If @i is out of bound, this will return the pstate
189 * corresponding to the nominal frequency.
190 */
967b87fd 191static inline u8 idx_to_pstate(unsigned int i)
09ca4c9b 192{
8e859467 193 if (unlikely(i >= powernv_pstate_info.nr_pstates)) {
332f0a01 194 pr_warn_once("idx_to_pstate: index %u is out of bound\n", i);
8e859467
AA
195 return powernv_freqs[powernv_pstate_info.nominal].driver_data;
196 }
197
09ca4c9b
AA
198 return powernv_freqs[i].driver_data;
199}
200
332f0a01
GS
201/**
202 * pstate_to_idx : Returns the index in the cpufreq frequencytable
203 * powernv_freqs for the frequency whose corresponding
204 * pstate id is @pstate.
205 *
206 * If no frequency corresponding to @pstate is found,
207 * this will return the index of the nominal
208 * frequency.
209 */
967b87fd 210static unsigned int pstate_to_idx(u8 pstate)
09ca4c9b 211{
332f0a01
GS
212 unsigned int key = pstate % POWERNV_MAX_PSTATES;
213 struct pstate_idx_revmap_data *revmap_data;
8e859467 214
332f0a01
GS
215 hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) {
216 if (revmap_data->pstate_id == pstate)
217 return revmap_data->cpufreq_table_idx;
8e859467 218 }
332f0a01 219
967b87fd 220 pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate);
332f0a01 221 return powernv_pstate_info.nominal;
09ca4c9b
AA
222}
223
eaa2c3ae
AA
224static inline void reset_gpstates(struct cpufreq_policy *policy)
225{
226 struct global_pstate_info *gpstates = policy->driver_data;
227
09ca4c9b 228 gpstates->highest_lpstate_idx = 0;
eaa2c3ae
AA
229 gpstates->elapsed_time = 0;
230 gpstates->last_sampled_time = 0;
09ca4c9b
AA
231 gpstates->last_lpstate_idx = 0;
232 gpstates->last_gpstate_idx = 0;
eaa2c3ae
AA
233}
234
b3d627a5
VS
235/*
236 * Initialize the freq table based on data obtained
237 * from the firmware passed via device-tree
238 */
239static int init_powernv_pstates(void)
240{
241 struct device_node *power_mgt;
09ca4c9b 242 int i, nr_pstates = 0;
b3d627a5
VS
243 const __be32 *pstate_ids, *pstate_freqs;
244 u32 len_ids, len_freqs;
09ca4c9b 245 u32 pstate_min, pstate_max, pstate_nominal;
b12f7a2b 246 u32 pstate_turbo, pstate_ultra_turbo;
b3d627a5
VS
247
248 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
249 if (!power_mgt) {
250 pr_warn("power-mgt node not found\n");
251 return -ENODEV;
252 }
253
254 if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
255 pr_warn("ibm,pstate-min node not found\n");
256 return -ENODEV;
257 }
258
259 if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
260 pr_warn("ibm,pstate-max node not found\n");
261 return -ENODEV;
262 }
263
264 if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
265 &pstate_nominal)) {
266 pr_warn("ibm,pstate-nominal not found\n");
267 return -ENODEV;
268 }
b12f7a2b
SB
269
270 if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo",
271 &pstate_ultra_turbo)) {
272 powernv_pstate_info.wof_enabled = false;
273 goto next;
274 }
275
276 if (of_property_read_u32(power_mgt, "ibm,pstate-turbo",
277 &pstate_turbo)) {
278 powernv_pstate_info.wof_enabled = false;
279 goto next;
280 }
281
282 if (pstate_turbo == pstate_ultra_turbo)
283 powernv_pstate_info.wof_enabled = false;
284 else
285 powernv_pstate_info.wof_enabled = true;
286
287next:
967b87fd 288 pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min,
b3d627a5 289 pstate_nominal, pstate_max);
b12f7a2b
SB
290 pr_info("Workload Optimized Frequency is %s in the platform\n",
291 (powernv_pstate_info.wof_enabled) ? "enabled" : "disabled");
b3d627a5
VS
292
293 pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
294 if (!pstate_ids) {
295 pr_warn("ibm,pstate-ids not found\n");
296 return -ENODEV;
297 }
298
299 pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
300 &len_freqs);
301 if (!pstate_freqs) {
302 pr_warn("ibm,pstate-frequencies-mhz not found\n");
303 return -ENODEV;
304 }
305
6174bac8
VS
306 if (len_ids != len_freqs) {
307 pr_warn("Entries in ibm,pstate-ids and "
308 "ibm,pstate-frequencies-mhz does not match\n");
309 }
310
b3d627a5
VS
311 nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
312 if (!nr_pstates) {
313 pr_warn("No PStates found\n");
314 return -ENODEV;
315 }
316
09ca4c9b 317 powernv_pstate_info.nr_pstates = nr_pstates;
b3d627a5 318 pr_debug("NR PStates %d\n", nr_pstates);
ee1f4a7d 319
b3d627a5
VS
320 for (i = 0; i < nr_pstates; i++) {
321 u32 id = be32_to_cpu(pstate_ids[i]);
322 u32 freq = be32_to_cpu(pstate_freqs[i]);
332f0a01
GS
323 struct pstate_idx_revmap_data *revmap_data;
324 unsigned int key;
b3d627a5
VS
325
326 pr_debug("PState id %d freq %d MHz\n", id, freq);
327 powernv_freqs[i].frequency = freq * 1000; /* kHz */
967b87fd 328 powernv_freqs[i].driver_data = id & 0xFF;
09ca4c9b 329
332f0a01
GS
330 revmap_data = (struct pstate_idx_revmap_data *)
331 kmalloc(sizeof(*revmap_data), GFP_KERNEL);
332
967b87fd 333 revmap_data->pstate_id = id & 0xFF;
332f0a01 334 revmap_data->cpufreq_table_idx = i;
967b87fd 335 key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES;
332f0a01
GS
336 hash_add(pstate_revmap, &revmap_data->hentry, key);
337
09ca4c9b
AA
338 if (id == pstate_max)
339 powernv_pstate_info.max = i;
3fa4680b 340 if (id == pstate_nominal)
09ca4c9b 341 powernv_pstate_info.nominal = i;
3fa4680b 342 if (id == pstate_min)
09ca4c9b 343 powernv_pstate_info.min = i;
b12f7a2b
SB
344
345 if (powernv_pstate_info.wof_enabled && id == pstate_turbo) {
346 int j;
347
348 for (j = i - 1; j >= (int)powernv_pstate_info.max; j--)
349 powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ;
350 }
b3d627a5 351 }
09ca4c9b 352
b3d627a5
VS
353 /* End of list marker entry */
354 powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
b3d627a5
VS
355 return 0;
356}
357
358/* Returns the CPU frequency corresponding to the pstate_id. */
967b87fd 359static unsigned int pstate_id_to_freq(u8 pstate_id)
b3d627a5
VS
360{
361 int i;
362
09ca4c9b 363 i = pstate_to_idx(pstate_id);
6174bac8 364 if (i >= powernv_pstate_info.nr_pstates || i < 0) {
967b87fd 365 pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n",
09ca4c9b
AA
366 pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
367 i = powernv_pstate_info.nominal;
6174bac8 368 }
b3d627a5
VS
369
370 return powernv_freqs[i].frequency;
371}
372
373/*
374 * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
375 * the firmware
376 */
377static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
378 char *buf)
379{
380 return sprintf(buf, "%u\n",
09ca4c9b 381 powernv_freqs[powernv_pstate_info.nominal].frequency);
b3d627a5
VS
382}
383
384struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
385 __ATTR_RO(cpuinfo_nominal_freq);
386
b12f7a2b
SB
387#define SCALING_BOOST_FREQS_ATTR_INDEX 2
388
b3d627a5
VS
389static struct freq_attr *powernv_cpu_freq_attr[] = {
390 &cpufreq_freq_attr_scaling_available_freqs,
391 &cpufreq_freq_attr_cpuinfo_nominal_freq,
b12f7a2b 392 &cpufreq_freq_attr_scaling_boost_freqs,
b3d627a5
VS
393 NULL,
394};
395
1b028984
SB
396#define throttle_attr(name, member) \
397static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
398{ \
399 struct chip *chip = per_cpu(chip_info, policy->cpu); \
400 \
401 return sprintf(buf, "%u\n", chip->member); \
402} \
403 \
404static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
405
406throttle_attr(unthrottle, reason[NO_THROTTLE]);
407throttle_attr(powercap, reason[POWERCAP]);
408throttle_attr(overtemp, reason[CPU_OVERTEMP]);
409throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
410throttle_attr(overcurrent, reason[OVERCURRENT]);
411throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
412throttle_attr(turbo_stat, throttle_turbo);
413throttle_attr(sub_turbo_stat, throttle_sub_turbo);
414
415static struct attribute *throttle_attrs[] = {
416 &throttle_attr_unthrottle.attr,
417 &throttle_attr_powercap.attr,
418 &throttle_attr_overtemp.attr,
419 &throttle_attr_supply_fault.attr,
420 &throttle_attr_overcurrent.attr,
421 &throttle_attr_occ_reset.attr,
422 &throttle_attr_turbo_stat.attr,
423 &throttle_attr_sub_turbo_stat.attr,
424 NULL,
425};
426
427static const struct attribute_group throttle_attr_grp = {
428 .name = "throttle_stats",
429 .attrs = throttle_attrs,
430};
431
b3d627a5
VS
432/* Helper routines */
433
434/* Access helpers to power mgt SPR */
435
436static inline unsigned long get_pmspr(unsigned long sprn)
437{
438 switch (sprn) {
439 case SPRN_PMCR:
440 return mfspr(SPRN_PMCR);
441
442 case SPRN_PMICR:
443 return mfspr(SPRN_PMICR);
444
445 case SPRN_PMSR:
446 return mfspr(SPRN_PMSR);
447 }
448 BUG();
449}
450
451static inline void set_pmspr(unsigned long sprn, unsigned long val)
452{
453 switch (sprn) {
454 case SPRN_PMCR:
455 mtspr(SPRN_PMCR, val);
456 return;
457
458 case SPRN_PMICR:
459 mtspr(SPRN_PMICR, val);
460 return;
461 }
462 BUG();
463}
464
465/*
466 * Use objects of this type to query/update
467 * pstates on a remote CPU via smp_call_function.
468 */
469struct powernv_smp_call_data {
470 unsigned int freq;
967b87fd
GS
471 u8 pstate_id;
472 u8 gpstate_id;
b3d627a5
VS
473};
474
475/*
476 * powernv_read_cpu_freq: Reads the current frequency on this CPU.
477 *
478 * Called via smp_call_function.
479 *
480 * Note: The caller of the smp_call_function should pass an argument of
481 * the type 'struct powernv_smp_call_data *' along with this function.
482 *
483 * The current frequency on this CPU will be returned via
484 * ((struct powernv_smp_call_data *)arg)->freq;
485 */
486static void powernv_read_cpu_freq(void *arg)
487{
488 unsigned long pmspr_val;
b3d627a5
VS
489 struct powernv_smp_call_data *freq_data = arg;
490
491 pmspr_val = get_pmspr(SPRN_PMSR);
ee1f4a7d 492 freq_data->pstate_id = extract_local_pstate(pmspr_val);
b3d627a5
VS
493 freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
494
967b87fd
GS
495 pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n",
496 raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
497 freq_data->freq);
b3d627a5
VS
498}
499
500/*
501 * powernv_cpufreq_get: Returns the CPU frequency as reported by the
502 * firmware for CPU 'cpu'. This value is reported through the sysfs
503 * file cpuinfo_cur_freq.
504 */
60d1ea4e 505static unsigned int powernv_cpufreq_get(unsigned int cpu)
b3d627a5
VS
506{
507 struct powernv_smp_call_data freq_data;
508
509 smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
510 &freq_data, 1);
511
512 return freq_data.freq;
513}
514
515/*
516 * set_pstate: Sets the pstate on this CPU.
517 *
518 * This is called via an smp_call_function.
519 *
520 * The caller must ensure that freq_data is of the type
521 * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
522 * on this CPU should be present in freq_data->pstate_id.
523 */
eaa2c3ae 524static void set_pstate(void *data)
b3d627a5
VS
525{
526 unsigned long val;
eaa2c3ae
AA
527 struct powernv_smp_call_data *freq_data = data;
528 unsigned long pstate_ul = freq_data->pstate_id;
529 unsigned long gpstate_ul = freq_data->gpstate_id;
b3d627a5
VS
530
531 val = get_pmspr(SPRN_PMCR);
532 val = val & 0x0000FFFFFFFFFFFFULL;
533
534 pstate_ul = pstate_ul & 0xFF;
eaa2c3ae 535 gpstate_ul = gpstate_ul & 0xFF;
b3d627a5
VS
536
537 /* Set both global(bits 56..63) and local(bits 48..55) PStates */
eaa2c3ae 538 val = val | (gpstate_ul << 56) | (pstate_ul << 48);
b3d627a5
VS
539
540 pr_debug("Setting cpu %d pmcr to %016lX\n",
541 raw_smp_processor_id(), val);
542 set_pmspr(SPRN_PMCR, val);
543}
544
cf30af76
SB
545/*
546 * get_nominal_index: Returns the index corresponding to the nominal
547 * pstate in the cpufreq table
548 */
549static inline unsigned int get_nominal_index(void)
550{
09ca4c9b 551 return powernv_pstate_info.nominal;
cf30af76
SB
552}
553
735366fc 554static void powernv_cpufreq_throttle_check(void *data)
09a972d1 555{
3e5963bc 556 struct chip *chip;
735366fc 557 unsigned int cpu = smp_processor_id();
09a972d1 558 unsigned long pmsr;
967b87fd 559 u8 pmsr_pmax;
09ca4c9b 560 unsigned int pmsr_pmax_idx;
09a972d1
SB
561
562 pmsr = get_pmspr(SPRN_PMSR);
3e5963bc 563 chip = this_cpu_read(chip_info);
053819e0 564
09a972d1 565 /* Check for Pmax Capping */
ee1f4a7d 566 pmsr_pmax = extract_max_pstate(pmsr);
09ca4c9b
AA
567 pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
568 if (pmsr_pmax_idx != powernv_pstate_info.max) {
3e5963bc 569 if (chip->throttled)
053819e0 570 goto next;
3e5963bc 571 chip->throttled = true;
09ca4c9b 572 if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
967b87fd 573 pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n",
3e5963bc 574 cpu, chip->id, pmsr_pmax,
09ca4c9b 575 idx_to_pstate(powernv_pstate_info.nominal));
1b028984
SB
576 chip->throttle_sub_turbo++;
577 } else {
578 chip->throttle_turbo++;
579 }
3e5963bc
MN
580 trace_powernv_throttle(chip->id,
581 throttle_reason[chip->throttle_reason],
c89f2682 582 pmsr_pmax);
3e5963bc
MN
583 } else if (chip->throttled) {
584 chip->throttled = false;
585 trace_powernv_throttle(chip->id,
586 throttle_reason[chip->throttle_reason],
c89f2682 587 pmsr_pmax);
09a972d1
SB
588 }
589
3dd3ebe5 590 /* Check if Psafe_mode_active is set in PMSR. */
053819e0 591next:
3dd3ebe5 592 if (pmsr & PMSR_PSAFE_ENABLE) {
09a972d1
SB
593 throttled = true;
594 pr_info("Pstate set to safe frequency\n");
595 }
596
597 /* Check if SPR_EM_DISABLE is set in PMSR */
598 if (pmsr & PMSR_SPR_EM_DISABLE) {
599 throttled = true;
600 pr_info("Frequency Control disabled from OS\n");
601 }
602
603 if (throttled) {
604 pr_info("PMSR = %16lx\n", pmsr);
c89f2682 605 pr_warn("CPU Frequency could be throttled\n");
09a972d1
SB
606 }
607}
608
eaa2c3ae
AA
609/**
610 * calc_global_pstate - Calculate global pstate
09ca4c9b
AA
611 * @elapsed_time: Elapsed time in milliseconds
612 * @local_pstate_idx: New local pstate
613 * @highest_lpstate_idx: pstate from which its ramping down
eaa2c3ae
AA
614 *
615 * Finds the appropriate global pstate based on the pstate from which its
616 * ramping down and the time elapsed in ramping down. It follows a quadratic
617 * equation which ensures that it reaches ramping down to pmin in 5sec.
618 */
619static inline int calc_global_pstate(unsigned int elapsed_time,
09ca4c9b
AA
620 int highest_lpstate_idx,
621 int local_pstate_idx)
eaa2c3ae 622{
09ca4c9b 623 int index_diff;
eaa2c3ae
AA
624
625 /*
626 * Using ramp_down_percent we get the percentage of rampdown
627 * that we are expecting to be dropping. Difference between
09ca4c9b 628 * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
eaa2c3ae
AA
629 * number of how many pstates we will drop eventually by the end of
630 * 5 seconds, then just scale it get the number pstates to be dropped.
631 */
09ca4c9b
AA
632 index_diff = ((int)ramp_down_percent(elapsed_time) *
633 (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
eaa2c3ae
AA
634
635 /* Ensure that global pstate is >= to local pstate */
09ca4c9b
AA
636 if (highest_lpstate_idx + index_diff >= local_pstate_idx)
637 return local_pstate_idx;
eaa2c3ae 638 else
09ca4c9b 639 return highest_lpstate_idx + index_diff;
eaa2c3ae
AA
640}
641
642static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
643{
644 unsigned int timer_interval;
645
646 /*
647 * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
648 * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
649 * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
650 * seconds of ramp down time.
651 */
652 if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
653 > MAX_RAMP_DOWN_TIME)
654 timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
655 else
656 timer_interval = GPSTATE_TIMER_INTERVAL;
657
7bc54b65 658 mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
eaa2c3ae
AA
659}
660
661/**
662 * gpstate_timer_handler
663 *
664 * @data: pointer to cpufreq_policy on which timer was queued
665 *
666 * This handler brings down the global pstate closer to the local pstate
667 * according quadratic equation. Queues a new timer if it is still not equal
668 * to local pstate
669 */
1d1fe902 670void gpstate_timer_handler(struct timer_list *t)
eaa2c3ae 671{
1d1fe902
KC
672 struct global_pstate_info *gpstates = from_timer(gpstates, t, timer);
673 struct cpufreq_policy *policy = gpstates->policy;
20b15b76
AA
674 int gpstate_idx, lpstate_idx;
675 unsigned long val;
eaa2c3ae
AA
676 unsigned int time_diff = jiffies_to_msecs(jiffies)
677 - gpstates->last_sampled_time;
678 struct powernv_smp_call_data freq_data;
679
680 if (!spin_trylock(&gpstates->gpstate_lock))
681 return;
c0f7f5b6
SB
682 /*
683 * If the timer has migrated to the different cpu then bring
684 * it back to one of the policy->cpus
685 */
686 if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) {
687 gpstates->timer.expires = jiffies + msecs_to_jiffies(1);
688 add_timer_on(&gpstates->timer, cpumask_first(policy->cpus));
689 spin_unlock(&gpstates->gpstate_lock);
690 return;
691 }
eaa2c3ae 692
20b15b76
AA
693 /*
694 * If PMCR was last updated was using fast_swtich then
695 * We may have wrong in gpstate->last_lpstate_idx
696 * value. Hence, read from PMCR to get correct data.
697 */
698 val = get_pmspr(SPRN_PMCR);
ee1f4a7d
GS
699 freq_data.gpstate_id = extract_global_pstate(val);
700 freq_data.pstate_id = extract_local_pstate(val);
20b15b76
AA
701 if (freq_data.gpstate_id == freq_data.pstate_id) {
702 reset_gpstates(policy);
703 spin_unlock(&gpstates->gpstate_lock);
704 return;
705 }
706
eaa2c3ae
AA
707 gpstates->last_sampled_time += time_diff;
708 gpstates->elapsed_time += time_diff;
eaa2c3ae 709
20b15b76 710 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
09ca4c9b 711 gpstate_idx = pstate_to_idx(freq_data.pstate_id);
c9a81e68 712 lpstate_idx = gpstate_idx;
eaa2c3ae 713 reset_gpstates(policy);
09ca4c9b 714 gpstates->highest_lpstate_idx = gpstate_idx;
eaa2c3ae 715 } else {
20b15b76 716 lpstate_idx = pstate_to_idx(freq_data.pstate_id);
09ca4c9b
AA
717 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
718 gpstates->highest_lpstate_idx,
20b15b76 719 lpstate_idx);
eaa2c3ae 720 }
20b15b76
AA
721 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
722 gpstates->last_gpstate_idx = gpstate_idx;
723 gpstates->last_lpstate_idx = lpstate_idx;
eaa2c3ae
AA
724 /*
725 * If local pstate is equal to global pstate, rampdown is over
726 * So timer is not required to be queued.
727 */
09ca4c9b 728 if (gpstate_idx != gpstates->last_lpstate_idx)
eaa2c3ae
AA
729 queue_gpstate_timer(gpstates);
730
c0f7f5b6 731 set_pstate(&freq_data);
1fd3ff28 732 spin_unlock(&gpstates->gpstate_lock);
eaa2c3ae
AA
733}
734
b3d627a5
VS
735/*
736 * powernv_cpufreq_target_index: Sets the frequency corresponding to
737 * the cpufreq table entry indexed by new_index on the cpus in the
738 * mask policy->cpus
739 */
740static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
741 unsigned int new_index)
742{
743 struct powernv_smp_call_data freq_data;
09ca4c9b 744 unsigned int cur_msec, gpstate_idx;
eaa2c3ae 745 struct global_pstate_info *gpstates = policy->driver_data;
b3d627a5 746
cf30af76
SB
747 if (unlikely(rebooting) && new_index != get_nominal_index())
748 return 0;
749
8a10c06a
DK
750 if (!throttled) {
751 /* we don't want to be preempted while
752 * checking if the CPU frequency has been throttled
753 */
754 preempt_disable();
735366fc 755 powernv_cpufreq_throttle_check(NULL);
8a10c06a
DK
756 preempt_enable();
757 }
09a972d1 758
eaa2c3ae
AA
759 cur_msec = jiffies_to_msecs(get_jiffies_64());
760
09ca4c9b 761 freq_data.pstate_id = idx_to_pstate(new_index);
dcb14337
SB
762 if (!gpstates) {
763 freq_data.gpstate_id = freq_data.pstate_id;
764 goto no_gpstate;
765 }
766
767 spin_lock(&gpstates->gpstate_lock);
b3d627a5 768
eaa2c3ae 769 if (!gpstates->last_sampled_time) {
09ca4c9b
AA
770 gpstate_idx = new_index;
771 gpstates->highest_lpstate_idx = new_index;
eaa2c3ae
AA
772 goto gpstates_done;
773 }
774
09ca4c9b 775 if (gpstates->last_gpstate_idx < new_index) {
eaa2c3ae
AA
776 gpstates->elapsed_time += cur_msec -
777 gpstates->last_sampled_time;
778
779 /*
780 * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
781 * we should be resetting all global pstate related data. Set it
782 * equal to local pstate to start fresh.
783 */
784 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
785 reset_gpstates(policy);
09ca4c9b
AA
786 gpstates->highest_lpstate_idx = new_index;
787 gpstate_idx = new_index;
eaa2c3ae
AA
788 } else {
789 /* Elaspsed_time is less than 5 seconds, continue to rampdown */
09ca4c9b
AA
790 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
791 gpstates->highest_lpstate_idx,
792 new_index);
eaa2c3ae
AA
793 }
794 } else {
795 reset_gpstates(policy);
09ca4c9b
AA
796 gpstates->highest_lpstate_idx = new_index;
797 gpstate_idx = new_index;
eaa2c3ae
AA
798 }
799
800 /*
801 * If local pstate is equal to global pstate, rampdown is over
802 * So timer is not required to be queued.
803 */
09ca4c9b 804 if (gpstate_idx != new_index)
eaa2c3ae 805 queue_gpstate_timer(gpstates);
0bc10b93
AA
806 else
807 del_timer_sync(&gpstates->timer);
eaa2c3ae
AA
808
809gpstates_done:
09ca4c9b 810 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
eaa2c3ae 811 gpstates->last_sampled_time = cur_msec;
09ca4c9b
AA
812 gpstates->last_gpstate_idx = gpstate_idx;
813 gpstates->last_lpstate_idx = new_index;
eaa2c3ae 814
1fd3ff28
AA
815 spin_unlock(&gpstates->gpstate_lock);
816
dcb14337 817no_gpstate:
b3d627a5
VS
818 /*
819 * Use smp_call_function to send IPI and execute the
820 * mtspr on target CPU. We could do that without IPI
821 * if current CPU is within policy->cpus (core)
822 */
823 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
b3d627a5
VS
824 return 0;
825}
826
827static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
828{
bf14721c 829 int base, i;
2920e9ce 830 struct kernfs_node *kn;
eaa2c3ae 831 struct global_pstate_info *gpstates;
b3d627a5
VS
832
833 base = cpu_first_thread_sibling(policy->cpu);
834
835 for (i = 0; i < threads_per_core; i++)
836 cpumask_set_cpu(base + i, policy->cpus);
837
2920e9ce
SB
838 kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
839 if (!kn) {
1b028984
SB
840 int ret;
841
842 ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
843 if (ret) {
844 pr_info("Failed to create throttle stats directory for cpu %d\n",
845 policy->cpu);
846 return ret;
847 }
2920e9ce
SB
848 } else {
849 kernfs_put(kn);
1b028984 850 }
eaa2c3ae 851
dcb14337
SB
852 policy->freq_table = powernv_freqs;
853 policy->fast_switch_possible = true;
854
855 if (pvr_version_is(PVR_POWER9))
856 return 0;
857
858 /* Initialise Gpstate ramp-down timer only on POWER8 */
eaa2c3ae
AA
859 gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL);
860 if (!gpstates)
861 return -ENOMEM;
862
863 policy->driver_data = gpstates;
864
865 /* initialize timer */
1d1fe902
KC
866 gpstates->policy = policy;
867 timer_setup(&gpstates->timer, gpstate_timer_handler,
868 TIMER_PINNED | TIMER_DEFERRABLE);
eaa2c3ae
AA
869 gpstates->timer.expires = jiffies +
870 msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
871 spin_lock_init(&gpstates->gpstate_lock);
eaa2c3ae 872
bf14721c 873 return 0;
eaa2c3ae
AA
874}
875
876static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
877{
878 /* timer is deleted in cpufreq_cpu_stop() */
879 kfree(policy->driver_data);
880
881 return 0;
b3d627a5
VS
882}
883
cf30af76
SB
884static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
885 unsigned long action, void *unused)
886{
887 int cpu;
888 struct cpufreq_policy cpu_policy;
889
890 rebooting = true;
891 for_each_online_cpu(cpu) {
892 cpufreq_get_policy(&cpu_policy, cpu);
893 powernv_cpufreq_target_index(&cpu_policy, get_nominal_index());
894 }
895
896 return NOTIFY_DONE;
897}
898
899static struct notifier_block powernv_cpufreq_reboot_nb = {
900 .notifier_call = powernv_cpufreq_reboot_notifier,
901};
902
735366fc
SB
903void powernv_cpufreq_work_fn(struct work_struct *work)
904{
905 struct chip *chip = container_of(work, struct chip, throttle);
22794280 906 unsigned int cpu;
6d167a44 907 cpumask_t mask;
735366fc 908
6d167a44
SB
909 get_online_cpus();
910 cpumask_and(&mask, &chip->mask, cpu_online_mask);
911 smp_call_function_any(&mask,
735366fc 912 powernv_cpufreq_throttle_check, NULL, 0);
22794280
SB
913
914 if (!chip->restore)
6d167a44 915 goto out;
22794280
SB
916
917 chip->restore = false;
6d167a44
SB
918 for_each_cpu(cpu, &mask) {
919 int index;
22794280
SB
920 struct cpufreq_policy policy;
921
922 cpufreq_get_policy(&policy, cpu);
82577360 923 index = cpufreq_table_find_index_c(&policy, policy.cur);
22794280 924 powernv_cpufreq_target_index(&policy, index);
6d167a44 925 cpumask_andnot(&mask, &mask, policy.cpus);
22794280 926 }
6d167a44
SB
927out:
928 put_online_cpus();
735366fc
SB
929}
930
cb166fa9
SB
931static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
932 unsigned long msg_type, void *_msg)
933{
934 struct opal_msg *msg = _msg;
935 struct opal_occ_msg omsg;
735366fc 936 int i;
cb166fa9
SB
937
938 if (msg_type != OPAL_MSG_OCC)
939 return 0;
940
941 omsg.type = be64_to_cpu(msg->params[0]);
942
943 switch (omsg.type) {
944 case OCC_RESET:
945 occ_reset = true;
309d0631 946 pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
cb166fa9
SB
947 /*
948 * powernv_cpufreq_throttle_check() is called in
949 * target() callback which can detect the throttle state
950 * for governors like ondemand.
951 * But static governors will not call target() often thus
952 * report throttling here.
953 */
954 if (!throttled) {
955 throttled = true;
c89f2682 956 pr_warn("CPU frequency is throttled for duration\n");
cb166fa9 957 }
309d0631 958
cb166fa9
SB
959 break;
960 case OCC_LOAD:
309d0631 961 pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
cb166fa9
SB
962 break;
963 case OCC_THROTTLE:
964 omsg.chip = be64_to_cpu(msg->params[1]);
965 omsg.throttle_status = be64_to_cpu(msg->params[2]);
966
967 if (occ_reset) {
968 occ_reset = false;
969 throttled = false;
309d0631 970 pr_info("OCC Active, CPU frequency is no longer throttled\n");
735366fc 971
22794280
SB
972 for (i = 0; i < nr_chips; i++) {
973 chips[i].restore = true;
735366fc 974 schedule_work(&chips[i].throttle);
22794280 975 }
735366fc 976
cb166fa9
SB
977 return 0;
978 }
979
c89f2682
SB
980 for (i = 0; i < nr_chips; i++)
981 if (chips[i].id == omsg.chip)
982 break;
983
984 if (omsg.throttle_status >= 0 &&
1b028984 985 omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
c89f2682 986 chips[i].throttle_reason = omsg.throttle_status;
1b028984
SB
987 chips[i].reason[omsg.throttle_status]++;
988 }
735366fc 989
c89f2682
SB
990 if (!omsg.throttle_status)
991 chips[i].restore = true;
992
993 schedule_work(&chips[i].throttle);
cb166fa9
SB
994 }
995 return 0;
996}
997
998static struct notifier_block powernv_cpufreq_opal_nb = {
999 .notifier_call = powernv_cpufreq_occ_msg,
1000 .next = NULL,
1001 .priority = 0,
1002};
1003
b120339c
PM
1004static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1005{
1006 struct powernv_smp_call_data freq_data;
eaa2c3ae 1007 struct global_pstate_info *gpstates = policy->driver_data;
b120339c 1008
09ca4c9b
AA
1009 freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
1010 freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
b120339c 1011 smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
dcb14337
SB
1012 if (gpstates)
1013 del_timer_sync(&gpstates->timer);
b120339c
PM
1014}
1015
60c9efb8
AA
1016static unsigned int powernv_fast_switch(struct cpufreq_policy *policy,
1017 unsigned int target_freq)
1018{
1019 int index;
1020 struct powernv_smp_call_data freq_data;
1021
1022 index = cpufreq_table_find_index_dl(policy, target_freq);
1023 freq_data.pstate_id = powernv_freqs[index].driver_data;
1024 freq_data.gpstate_id = powernv_freqs[index].driver_data;
1025 set_pstate(&freq_data);
1026
1027 return powernv_freqs[index].frequency;
1028}
1029
b3d627a5
VS
1030static struct cpufreq_driver powernv_cpufreq_driver = {
1031 .name = "powernv-cpufreq",
1032 .flags = CPUFREQ_CONST_LOOPS,
1033 .init = powernv_cpufreq_cpu_init,
eaa2c3ae 1034 .exit = powernv_cpufreq_cpu_exit,
b3d627a5
VS
1035 .verify = cpufreq_generic_frequency_table_verify,
1036 .target_index = powernv_cpufreq_target_index,
60c9efb8 1037 .fast_switch = powernv_fast_switch,
b3d627a5 1038 .get = powernv_cpufreq_get,
b120339c 1039 .stop_cpu = powernv_cpufreq_stop_cpu,
b3d627a5
VS
1040 .attr = powernv_cpu_freq_attr,
1041};
1042
053819e0
SB
1043static int init_chip_info(void)
1044{
1045 unsigned int chip[256];
1046 unsigned int cpu, i;
1047 unsigned int prev_chip_id = UINT_MAX;
96c4726f 1048
3e5963bc 1049 for_each_possible_cpu(cpu) {
053819e0
SB
1050 unsigned int id = cpu_to_chip_id(cpu);
1051
1052 if (prev_chip_id != id) {
1053 prev_chip_id = id;
1054 chip[nr_chips++] = id;
1055 }
1056 }
1057
c89f2682 1058 chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
053819e0 1059 if (!chips)
3e5963bc 1060 return -ENOMEM;
053819e0
SB
1061
1062 for (i = 0; i < nr_chips; i++) {
1063 chips[i].id = chip[i];
735366fc
SB
1064 cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
1065 INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
3e5963bc
MN
1066 for_each_cpu(cpu, &chips[i].mask)
1067 per_cpu(chip_info, cpu) = &chips[i];
053819e0
SB
1068 }
1069
1070 return 0;
1071}
1072
c5e29ea7
SB
1073static inline void clean_chip_info(void)
1074{
1075 kfree(chips);
c5e29ea7
SB
1076}
1077
1078static inline void unregister_all_notifiers(void)
1079{
1080 opal_message_notifier_unregister(OPAL_MSG_OCC,
1081 &powernv_cpufreq_opal_nb);
1082 unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
1083}
1084
b3d627a5
VS
1085static int __init powernv_cpufreq_init(void)
1086{
1087 int rc = 0;
1088
6174bac8 1089 /* Don't probe on pseries (guest) platforms */
e4d54f71 1090 if (!firmware_has_feature(FW_FEATURE_OPAL))
6174bac8
VS
1091 return -ENODEV;
1092
b3d627a5
VS
1093 /* Discover pstates from device tree and init */
1094 rc = init_powernv_pstates();
c5e29ea7
SB
1095 if (rc)
1096 goto out;
b3d627a5 1097
053819e0
SB
1098 /* Populate chip info */
1099 rc = init_chip_info();
1100 if (rc)
c5e29ea7 1101 goto out;
053819e0 1102
cf30af76 1103 register_reboot_notifier(&powernv_cpufreq_reboot_nb);
cb166fa9 1104 opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
c5e29ea7 1105
b12f7a2b
SB
1106 if (powernv_pstate_info.wof_enabled)
1107 powernv_cpufreq_driver.boost_enabled = true;
1108 else
1109 powernv_cpu_freq_attr[SCALING_BOOST_FREQS_ATTR_INDEX] = NULL;
1110
c5e29ea7 1111 rc = cpufreq_register_driver(&powernv_cpufreq_driver);
b12f7a2b
SB
1112 if (rc) {
1113 pr_info("Failed to register the cpufreq driver (%d)\n", rc);
1114 goto cleanup_notifiers;
1115 }
c5e29ea7 1116
b12f7a2b
SB
1117 if (powernv_pstate_info.wof_enabled)
1118 cpufreq_enable_boost_support();
1119
1120 return 0;
1121cleanup_notifiers:
c5e29ea7
SB
1122 unregister_all_notifiers();
1123 clean_chip_info();
1124out:
1125 pr_info("Platform driver disabled. System does not support PState control\n");
1126 return rc;
b3d627a5
VS
1127}
1128module_init(powernv_cpufreq_init);
1129
1130static void __exit powernv_cpufreq_exit(void)
1131{
1132 cpufreq_unregister_driver(&powernv_cpufreq_driver);
c5e29ea7
SB
1133 unregister_all_notifiers();
1134 clean_chip_info();
b3d627a5
VS
1135}
1136module_exit(powernv_cpufreq_exit);
1137
1138MODULE_LICENSE("GPL");
1139MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");