Merge tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel...
[linux-2.6-block.git] / drivers / cpufreq / pmac64-cpufreq.c
CommitLineData
4350147a
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1/*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
10 * that is iMac G5 and latest single CPU desktop.
11 */
12
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13#undef DEBUG
14
4350147a
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15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/sched.h>
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21#include <linux/cpufreq.h>
22#include <linux/init.h>
23#include <linux/completion.h>
14cc3e2b 24#include <linux/mutex.h>
760287ab 25#include <linux/of_device.h>
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26#include <asm/prom.h>
27#include <asm/machdep.h>
28#include <asm/irq.h>
29#include <asm/sections.h>
30#include <asm/cputable.h>
31#include <asm/time.h>
32#include <asm/smu.h>
9a699aef 33#include <asm/pmac_pfunc.h>
4350147a 34
7ed14c21 35#define DBG(fmt...) pr_debug(fmt)
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36
37/* see 970FX user manual */
38
39#define SCOM_PCR 0x0aa001 /* PCR scom addr */
40
41#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
42#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
43#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
44#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
45#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
46#define PCR_SPEED_SHIFT 17
47#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
48#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
49#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
50#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
51#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
52#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
53
54#define SCOM_PSR 0x408001 /* PSR scom addr */
55/* warning: PSR is a 64 bits register */
56#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
57#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
58#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
59#define PSR_CUR_SPEED_SHIFT (56)
60
61/*
62 * The G5 only supports two frequencies (Quarter speed is not supported)
63 */
64#define CPUFREQ_HIGH 0
65#define CPUFREQ_LOW 1
66
67static struct cpufreq_frequency_table g5_cpu_freqs[] = {
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68 {0, CPUFREQ_HIGH, 0},
69 {0, CPUFREQ_LOW, 0},
70 {0, 0, CPUFREQ_TABLE_END},
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71};
72
4350147a 73/* Power mode data is an array of the 32 bits PCR values to use for
943ffb58 74 * the various frequencies, retrieved from the device-tree
4350147a 75 */
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76static int g5_pmode_cur;
77
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78static void (*g5_switch_volt)(int speed_mode);
79static int (*g5_switch_freq)(int speed_mode);
80static int (*g5_query_freq)(void);
81
16962e7c 82static unsigned long transition_latency;
4350147a 83
e272a285 84#ifdef CONFIG_PMAC_SMU
7ed14c21 85
9ca91e0f 86static const u32 *g5_pmode_data;
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87static int g5_pmode_max;
88
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89static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
90static int g5_fvt_count; /* number of op. points */
91static int g5_fvt_cur; /* current op. point */
92
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93/*
94 * SMU based voltage switching for Neo2 platforms
95 */
4350147a 96
9a699aef 97static void g5_smu_switch_volt(int speed_mode)
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98{
99 struct smu_simple_cmd cmd;
100
6e9a4738 101 DECLARE_COMPLETION_ONSTACK(comp);
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102 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
103 &comp, 'V', 'S', 'L', 'E', 'W',
104 0xff, g5_fvt_cur+1, speed_mode);
105 wait_for_completion(&comp);
106}
107
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108/*
109 * Platform function based voltage/vdnap switching for Neo2
110 */
111
112static struct pmf_function *pfunc_set_vdnap0;
113static struct pmf_function *pfunc_vdnap0_complete;
114
115static void g5_vdnap_switch_volt(int speed_mode)
4350147a 116{
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117 struct pmf_args args;
118 u32 slew, done = 0;
119 unsigned long timeout;
4350147a 120
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121 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
122 args.count = 1;
123 args.u[0].p = &slew;
4350147a 124
9a699aef 125 pmf_call_one(pfunc_set_vdnap0, &args);
4350147a 126
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127 /* It's an irq GPIO so we should be able to just block here,
128 * I'll do that later after I've properly tested the IRQ code for
129 * platform functions
130 */
131 timeout = jiffies + HZ/10;
132 while(!time_after(jiffies, timeout)) {
133 args.count = 1;
134 args.u[0].p = &done;
135 pmf_call_one(pfunc_vdnap0_complete, &args);
136 if (done)
137 break;
45a428eb 138 usleep_range(1000, 1000);
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139 }
140 if (done == 0)
141 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
142}
4350147a 143
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144
145/*
146 * SCOM based frequency switching for 970FX rev3
147 */
148static int g5_scom_switch_freq(int speed_mode)
149{
150 unsigned long flags;
151 int to;
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152
153 /* If frequency is going up, first ramp up the voltage */
154 if (speed_mode < g5_pmode_cur)
155 g5_switch_volt(speed_mode);
156
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157 local_irq_save(flags);
158
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159 /* Clear PCR high */
160 scom970_write(SCOM_PCR, 0);
161 /* Clear PCR low */
162 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
163 /* Set PCR low */
164 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
165 g5_pmode_data[speed_mode]);
166
167 /* Wait for completion */
168 for (to = 0; to < 10; to++) {
169 unsigned long psr = scom970_read(SCOM_PSR);
170
171 if ((psr & PSR_CMD_RECEIVED) == 0 &&
172 (((psr >> PSR_CUR_SPEED_SHIFT) ^
173 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
174 == 0)
175 break;
176 if (psr & PSR_CMD_COMPLETED)
177 break;
178 udelay(100);
179 }
180
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181 local_irq_restore(flags);
182
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183 /* If frequency is going down, last ramp the voltage */
184 if (speed_mode > g5_pmode_cur)
185 g5_switch_volt(speed_mode);
186
187 g5_pmode_cur = speed_mode;
188 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
189
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190 return 0;
191}
192
9a699aef 193static int g5_scom_query_freq(void)
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194{
195 unsigned long psr = scom970_read(SCOM_PSR);
196 int i;
197
198 for (i = 0; i <= g5_pmode_max; i++)
199 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
200 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
201 break;
202 return i;
203}
204
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205/*
206 * Fake voltage switching for platforms with missing support
207 */
208
209static void g5_dummy_switch_volt(int speed_mode)
210{
211}
212
e272a285 213#endif /* CONFIG_PMAC_SMU */
7ed14c21 214
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215/*
216 * Platform function based voltage switching for PowerMac7,2 & 7,3
217 */
218
219static struct pmf_function *pfunc_cpu0_volt_high;
220static struct pmf_function *pfunc_cpu0_volt_low;
221static struct pmf_function *pfunc_cpu1_volt_high;
222static struct pmf_function *pfunc_cpu1_volt_low;
223
224static void g5_pfunc_switch_volt(int speed_mode)
225{
226 if (speed_mode == CPUFREQ_HIGH) {
227 if (pfunc_cpu0_volt_high)
228 pmf_call_one(pfunc_cpu0_volt_high, NULL);
229 if (pfunc_cpu1_volt_high)
230 pmf_call_one(pfunc_cpu1_volt_high, NULL);
231 } else {
232 if (pfunc_cpu0_volt_low)
233 pmf_call_one(pfunc_cpu0_volt_low, NULL);
234 if (pfunc_cpu1_volt_low)
235 pmf_call_one(pfunc_cpu1_volt_low, NULL);
236 }
45a428eb 237 usleep_range(10000, 10000); /* should be faster , to fix */
9a699aef
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238}
239
240/*
241 * Platform function based frequency switching for PowerMac7,2 & 7,3
242 */
243
244static struct pmf_function *pfunc_cpu_setfreq_high;
245static struct pmf_function *pfunc_cpu_setfreq_low;
246static struct pmf_function *pfunc_cpu_getfreq;
d258e64e 247static struct pmf_function *pfunc_slewing_done;
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248
249static int g5_pfunc_switch_freq(int speed_mode)
250{
251 struct pmf_args args;
252 u32 done = 0;
253 unsigned long timeout;
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254 int rc;
255
256 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
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257
258 /* If frequency is going up, first ramp up the voltage */
259 if (speed_mode < g5_pmode_cur)
260 g5_switch_volt(speed_mode);
261
262 /* Do it */
263 if (speed_mode == CPUFREQ_HIGH)
7ed14c21 264 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
9a699aef 265 else
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266 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
267
268 if (rc)
269 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
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270
271 /* It's an irq GPIO so we should be able to just block here,
272 * I'll do that later after I've properly tested the IRQ code for
273 * platform functions
274 */
275 timeout = jiffies + HZ/10;
276 while(!time_after(jiffies, timeout)) {
277 args.count = 1;
278 args.u[0].p = &done;
279 pmf_call_one(pfunc_slewing_done, &args);
280 if (done)
281 break;
45a428eb 282 usleep_range(500, 500);
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283 }
284 if (done == 0)
285 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
286
287 /* If frequency is going down, last ramp the voltage */
288 if (speed_mode > g5_pmode_cur)
289 g5_switch_volt(speed_mode);
290
291 g5_pmode_cur = speed_mode;
292 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
293
294 return 0;
295}
296
297static int g5_pfunc_query_freq(void)
298{
299 struct pmf_args args;
300 u32 val = 0;
301
302 args.count = 1;
303 args.u[0].p = &val;
304 pmf_call_one(pfunc_cpu_getfreq, &args);
305 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
306}
307
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308
309/*
310 * Common interface to the cpufreq core
311 */
4350147a 312
9c0ebcf7 313static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
4350147a 314{
d4019f0a 315 return g5_switch_freq(index);
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316}
317
318static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
319{
320 return g5_cpu_freqs[g5_pmode_cur].frequency;
321}
322
323static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
324{
8ce6f9de 325 return cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
4350147a
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326}
327
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328static struct cpufreq_driver g5_cpufreq_driver = {
329 .name = "powermac",
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330 .flags = CPUFREQ_CONST_LOOPS,
331 .init = g5_cpufreq_cpu_init,
2633a46c 332 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 333 .target_index = g5_cpufreq_target,
4350147a 334 .get = g5_cpufreq_get_speed,
2633a46c 335 .attr = cpufreq_generic_attr,
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336};
337
338
e272a285 339#ifdef CONFIG_PMAC_SMU
7ed14c21 340
760287ab 341static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
4350147a 342{
4350147a 343 unsigned int psize, ssize;
4350147a 344 unsigned long max_freq;
9a699aef 345 char *freq_method, *volt_method;
018a3d1d
JK
346 const u32 *valp;
347 u32 pvr_hi;
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348 int use_volts_vdnap = 0;
349 int use_volts_smu = 0;
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350 int rc = -ENODEV;
351
9a699aef 352 /* Check supported platforms */
71a157e8
GL
353 if (of_machine_is_compatible("PowerMac8,1") ||
354 of_machine_is_compatible("PowerMac8,2") ||
89108362
AK
355 of_machine_is_compatible("PowerMac9,1") ||
356 of_machine_is_compatible("PowerMac12,1"))
9a699aef 357 use_volts_smu = 1;
71a157e8 358 else if (of_machine_is_compatible("PowerMac11,2"))
9a699aef
BH
359 use_volts_vdnap = 1;
360 else
361 return -ENODEV;
362
4350147a 363 /* Check 970FX for now */
e2eb6392 364 valp = of_get_property(cpunode, "cpu-version", NULL);
4350147a
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365 if (!valp) {
366 DBG("No cpu-version property !\n");
367 goto bail_noprops;
368 }
9a699aef
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369 pvr_hi = (*valp) >> 16;
370 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
371 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
4350147a
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372 goto bail_noprops;
373 }
374
375 /* Look for the powertune data in the device-tree */
e2eb6392 376 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
4350147a
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377 if (!g5_pmode_data) {
378 DBG("No power-mode-data !\n");
379 goto bail_noprops;
380 }
381 g5_pmode_max = psize / sizeof(u32) - 1;
382
9a699aef 383 if (use_volts_smu) {
018a3d1d 384 const struct smu_sdbp_header *shdr;
9a699aef
BH
385
386 /* Look for the FVT table */
387 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
388 if (!shdr)
389 goto bail_noprops;
390 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
d5b73cd8
VK
391 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
392 g5_fvt_count = ssize / sizeof(*g5_fvt_table);
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393 g5_fvt_cur = 0;
394
395 /* Sanity checking */
396 if (g5_fvt_count < 1 || g5_pmode_max < 1)
397 goto bail_noprops;
398
399 g5_switch_volt = g5_smu_switch_volt;
400 volt_method = "SMU";
401 } else if (use_volts_vdnap) {
402 struct device_node *root;
403
404 root = of_find_node_by_path("/");
405 if (root == NULL) {
406 printk(KERN_ERR "cpufreq: Can't find root of "
407 "device tree\n");
408 goto bail_noprops;
409 }
410 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
411 pfunc_vdnap0_complete =
412 pmf_find_function(root, "slewing-done");
413 if (pfunc_set_vdnap0 == NULL ||
414 pfunc_vdnap0_complete == NULL) {
415 printk(KERN_ERR "cpufreq: Can't find required "
416 "platform function\n");
417 goto bail_noprops;
418 }
419
420 g5_switch_volt = g5_vdnap_switch_volt;
421 volt_method = "GPIO";
422 } else {
423 g5_switch_volt = g5_dummy_switch_volt;
424 volt_method = "none";
425 }
4350147a
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426
427 /*
428 * From what I see, clock-frequency is always the maximal frequency.
429 * The current driver can not slew sysclk yet, so we really only deal
430 * with powertune steps for now. We also only implement full freq and
431 * half freq in this version. So far, I haven't yet seen a machine
432 * supporting anything else.
433 */
e2eb6392 434 valp = of_get_property(cpunode, "clock-frequency", NULL);
4350147a
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435 if (!valp)
436 return -ENODEV;
437 max_freq = (*valp)/1000;
438 g5_cpu_freqs[0].frequency = max_freq;
439 g5_cpu_freqs[1].frequency = max_freq/2;
440
9a699aef 441 /* Set callbacks */
16962e7c 442 transition_latency = 12000;
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443 g5_switch_freq = g5_scom_switch_freq;
444 g5_query_freq = g5_scom_query_freq;
445 freq_method = "SCOM";
4350147a
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446
447 /* Force apply current frequency to make sure everything is in
448 * sync (voltage is right for example). Firmware may leave us with
449 * a strange setting ...
450 */
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451 g5_switch_volt(CPUFREQ_HIGH);
452 msleep(10);
453 g5_pmode_cur = -1;
454 g5_switch_freq(g5_query_freq());
4350147a
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455
456 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
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457 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
458 freq_method, volt_method);
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459 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
460 g5_cpu_freqs[1].frequency/1000,
461 g5_cpu_freqs[0].frequency/1000,
462 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
463
464 rc = cpufreq_register_driver(&g5_cpufreq_driver);
465
466 /* We keep the CPU node on hold... hopefully, Apple G5 don't have
467 * hotplug CPU with a dynamic device-tree ...
468 */
469 return rc;
470
471 bail_noprops:
472 of_node_put(cpunode);
473
474 return rc;
475}
476
e272a285 477#endif /* CONFIG_PMAC_SMU */
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478
479
760287ab 480static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
9a699aef 481{
760287ab 482 struct device_node *cpuid = NULL, *hwclock = NULL;
018a3d1d
JK
483 const u8 *eeprom = NULL;
484 const u32 *valp;
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485 u64 max_freq, min_freq, ih, il;
486 int has_volt = 1, rc = 0;
487
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488 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
489 " RackMac3,1...\n");
490
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491 /* Lookup the cpuid eeprom node */
492 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
493 if (cpuid != NULL)
e2eb6392 494 eeprom = of_get_property(cpuid, "cpuid", NULL);
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495 if (eeprom == NULL) {
496 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
497 rc = -ENODEV;
498 goto bail;
499 }
500
501 /* Lookup the i2c hwclock */
ccdb8ed3 502 for_each_node_by_name(hwclock, "i2c-hwclock") {
e2eb6392 503 const char *loc = of_get_property(hwclock,
018a3d1d 504 "hwctrl-location", NULL);
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505 if (loc == NULL)
506 continue;
507 if (strcmp(loc, "CPU CLOCK"))
508 continue;
e2eb6392 509 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
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510 continue;
511 break;
512 }
513 if (hwclock == NULL) {
514 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
515 rc = -ENODEV;
516 goto bail;
517 }
518
519 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
520
521 /* Now get all the platform functions */
522 pfunc_cpu_getfreq =
523 pmf_find_function(hwclock, "get-frequency");
524 pfunc_cpu_setfreq_high =
525 pmf_find_function(hwclock, "set-frequency-high");
526 pfunc_cpu_setfreq_low =
527 pmf_find_function(hwclock, "set-frequency-low");
528 pfunc_slewing_done =
529 pmf_find_function(hwclock, "slewing-done");
530 pfunc_cpu0_volt_high =
531 pmf_find_function(hwclock, "set-voltage-high-0");
532 pfunc_cpu0_volt_low =
533 pmf_find_function(hwclock, "set-voltage-low-0");
534 pfunc_cpu1_volt_high =
535 pmf_find_function(hwclock, "set-voltage-high-1");
536 pfunc_cpu1_volt_low =
537 pmf_find_function(hwclock, "set-voltage-low-1");
538
539 /* Check we have minimum requirements */
540 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
541 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
542 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
543 rc = -ENODEV;
544 goto bail;
545 }
546
547 /* Check that we have complete sets */
548 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
549 pmf_put_function(pfunc_cpu0_volt_high);
550 pmf_put_function(pfunc_cpu0_volt_low);
551 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
552 has_volt = 0;
553 }
554 if (!has_volt ||
555 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
556 pmf_put_function(pfunc_cpu1_volt_high);
557 pmf_put_function(pfunc_cpu1_volt_low);
558 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
559 }
560
561 /* Note: The device tree also contains a "platform-set-values"
562 * function for which I haven't quite figured out the usage. It
563 * might have to be called on init and/or wakeup, I'm not too sure
564 * but things seem to work fine without it so far ...
565 */
566
567 /* Get max frequency from device-tree */
e2eb6392 568 valp = of_get_property(cpunode, "clock-frequency", NULL);
9a699aef
BH
569 if (!valp) {
570 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
571 rc = -ENODEV;
572 goto bail;
573 }
574
575 max_freq = (*valp)/1000;
576
577 /* Now calculate reduced frequency by using the cpuid input freq
578 * ratio. This requires 64 bits math unless we are willing to lose
579 * some precision
580 */
581 ih = *((u32 *)(eeprom + 0x10));
582 il = *((u32 *)(eeprom + 0x20));
7ed14c21
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583
584 /* Check for machines with no useful settings */
585 if (il == ih) {
586 printk(KERN_WARNING "cpufreq: No low frequency mode available"
587 " on this model !\n");
588 rc = -ENODEV;
589 goto bail;
590 }
591
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592 min_freq = 0;
593 if (ih != 0 && il != 0)
594 min_freq = (max_freq * il) / ih;
595
596 /* Sanity check */
597 if (min_freq >= max_freq || min_freq < 1000) {
598 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
7ed14c21 599 rc = -ENXIO;
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600 goto bail;
601 }
602 g5_cpu_freqs[0].frequency = max_freq;
603 g5_cpu_freqs[1].frequency = min_freq;
604
af671d8b
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605 /* Based on a measurement on Xserve G5, rounded up. */
606 transition_latency = 10 * NSEC_PER_MSEC;
607
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608 /* Set callbacks */
609 g5_switch_volt = g5_pfunc_switch_volt;
610 g5_switch_freq = g5_pfunc_switch_freq;
611 g5_query_freq = g5_pfunc_query_freq;
612
613 /* Force apply current frequency to make sure everything is in
614 * sync (voltage is right for example). Firmware may leave us with
615 * a strange setting ...
616 */
617 g5_switch_volt(CPUFREQ_HIGH);
618 msleep(10);
619 g5_pmode_cur = -1;
620 g5_switch_freq(g5_query_freq());
621
622 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
623 printk(KERN_INFO "Frequency method: i2c/pfunc, "
624 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
625 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
626 g5_cpu_freqs[1].frequency/1000,
627 g5_cpu_freqs[0].frequency/1000,
628 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
629
630 rc = cpufreq_register_driver(&g5_cpufreq_driver);
631 bail:
632 if (rc != 0) {
633 pmf_put_function(pfunc_cpu_getfreq);
634 pmf_put_function(pfunc_cpu_setfreq_high);
635 pmf_put_function(pfunc_cpu_setfreq_low);
636 pmf_put_function(pfunc_slewing_done);
637 pmf_put_function(pfunc_cpu0_volt_high);
638 pmf_put_function(pfunc_cpu0_volt_low);
639 pmf_put_function(pfunc_cpu1_volt_high);
640 pmf_put_function(pfunc_cpu1_volt_low);
641 }
642 of_node_put(hwclock);
643 of_node_put(cpuid);
644 of_node_put(cpunode);
645
646 return rc;
647}
648
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649static int __init g5_cpufreq_init(void)
650{
760287ab 651 struct device_node *cpunode;
7ed14c21 652 int rc = 0;
9a699aef 653
760287ab
SK
654 /* Get first CPU node */
655 cpunode = of_cpu_device_node_get(0);
656 if (cpunode == NULL) {
657 pr_err("cpufreq: Can't find any CPU node\n");
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658 return -ENODEV;
659 }
660
71a157e8
GL
661 if (of_machine_is_compatible("PowerMac7,2") ||
662 of_machine_is_compatible("PowerMac7,3") ||
663 of_machine_is_compatible("RackMac3,1"))
760287ab 664 rc = g5_pm72_cpufreq_init(cpunode);
e272a285 665#ifdef CONFIG_PMAC_SMU
9a699aef 666 else
760287ab 667 rc = g5_neo2_cpufreq_init(cpunode);
e272a285 668#endif /* CONFIG_PMAC_SMU */
9a699aef 669
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670 return rc;
671}
672
4350147a
BH
673module_init(g5_cpufreq_init);
674
675
676MODULE_LICENSE("GPL");