Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Pentium 4/Xeon CPU on demand clock modulation/speed scaling | |
4 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> | |
5 | * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com> | |
6 | * (C) 2002 Arjan van de Ven <arjanv@redhat.com> | |
7 | * (C) 2002 Tora T. Engstad | |
8 | * All Rights Reserved | |
9 | * | |
1da177e4 LT |
10 | * The author(s) of this software shall not be held liable for damages |
11 | * of any nature resulting due to the use of this software. This | |
12 | * software is provided AS-IS with no warranties. | |
32ee8c3e | 13 | * |
1da177e4 LT |
14 | * Date Errata Description |
15 | * 20020525 N44, O17 12.5% or 25% DC causes lockup | |
1da177e4 LT |
16 | */ |
17 | ||
1c5864e2 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
32ee8c3e | 21 | #include <linux/module.h> |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/smp.h> | |
24 | #include <linux/cpufreq.h> | |
1da177e4 | 25 | #include <linux/cpumask.h> |
bbfebd66 | 26 | #include <linux/timex.h> |
1da177e4 | 27 | |
32ee8c3e | 28 | #include <asm/processor.h> |
1da177e4 | 29 | #include <asm/msr.h> |
199785ea | 30 | #include <asm/timer.h> |
fa8031ae | 31 | #include <asm/cpu_device_id.h> |
1da177e4 LT |
32 | |
33 | #include "speedstep-lib.h" | |
34 | ||
1da177e4 LT |
35 | /* |
36 | * Duty Cycle (3bits), note DC_DISABLE is not specified in | |
37 | * intel docs i just use it to mean disable | |
38 | */ | |
39 | enum { | |
40 | DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT, | |
41 | DC_64PT, DC_75PT, DC_88PT, DC_DISABLE | |
42 | }; | |
43 | ||
44 | #define DC_ENTRIES 8 | |
45 | ||
46 | ||
47 | static int has_N44_O17_errata[NR_CPUS]; | |
48 | static unsigned int stock_freq; | |
49 | static struct cpufreq_driver p4clockmod_driver; | |
50 | static unsigned int cpufreq_p4_get(unsigned int cpu); | |
51 | ||
52 | static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) | |
53 | { | |
54 | u32 l, h; | |
55 | ||
e9f51837 | 56 | if ((newstate > DC_DISABLE) || (newstate == DC_RESV)) |
1da177e4 LT |
57 | return -EINVAL; |
58 | ||
551948bc | 59 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); |
1da177e4 LT |
60 | |
61 | if (l & 0x01) | |
2d06d8c4 | 62 | pr_debug("CPU#%d currently thermal throttled\n", cpu); |
1da177e4 | 63 | |
bbfebd66 DJ |
64 | if (has_N44_O17_errata[cpu] && |
65 | (newstate == DC_25PT || newstate == DC_DFLT)) | |
1da177e4 LT |
66 | newstate = DC_38PT; |
67 | ||
551948bc | 68 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 | 69 | if (newstate == DC_DISABLE) { |
2d06d8c4 | 70 | pr_debug("CPU#%d disabling modulation\n", cpu); |
551948bc | 71 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); |
1da177e4 | 72 | } else { |
2d06d8c4 | 73 | pr_debug("CPU#%d setting duty cycle to %d%%\n", |
1da177e4 | 74 | cpu, ((125 * newstate) / 10)); |
32ee8c3e | 75 | /* bits 63 - 5 : reserved |
1da177e4 LT |
76 | * bit 4 : enable/disable |
77 | * bits 3-1 : duty cycle | |
78 | * bit 0 : reserved | |
79 | */ | |
80 | l = (l & ~14); | |
81 | l = l | (1<<4) | ((newstate & 0x7)<<1); | |
551948bc | 82 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); |
1da177e4 LT |
83 | } |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | ||
89 | static struct cpufreq_frequency_table p4clockmod_table[] = { | |
7f4b0461 VK |
90 | {0, DC_RESV, CPUFREQ_ENTRY_INVALID}, |
91 | {0, DC_DFLT, 0}, | |
92 | {0, DC_25PT, 0}, | |
93 | {0, DC_38PT, 0}, | |
94 | {0, DC_50PT, 0}, | |
95 | {0, DC_64PT, 0}, | |
96 | {0, DC_75PT, 0}, | |
97 | {0, DC_88PT, 0}, | |
98 | {0, DC_DISABLE, 0}, | |
99 | {0, DC_RESV, CPUFREQ_TABLE_END}, | |
1da177e4 LT |
100 | }; |
101 | ||
102 | ||
9c0ebcf7 | 103 | static int cpufreq_p4_target(struct cpufreq_policy *policy, unsigned int index) |
1da177e4 | 104 | { |
1da177e4 LT |
105 | int i; |
106 | ||
bbfebd66 DJ |
107 | /* run on each logical CPU, |
108 | * see section 13.15.3 of IA32 Intel Architecture Software | |
32ee8c3e | 109 | * Developer's Manual, Volume 3 |
1da177e4 | 110 | */ |
835481d9 | 111 | for_each_cpu(i, policy->cpus) |
9c0ebcf7 | 112 | cpufreq_p4_setdc(i, p4clockmod_table[index].driver_data); |
1da177e4 | 113 | |
1da177e4 LT |
114 | return 0; |
115 | } | |
116 | ||
117 | ||
1da177e4 LT |
118 | static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c) |
119 | { | |
4e74663c DB |
120 | if (c->x86 == 0x06) { |
121 | if (cpu_has(c, X86_FEATURE_EST)) | |
1c5864e2 | 122 | pr_warn_once("Warning: EST-capable CPU detected. The acpi-cpufreq module offers voltage scaling in addition to frequency scaling. You should use that instead of p4-clockmod, if possible.\n"); |
4e74663c DB |
123 | switch (c->x86_model) { |
124 | case 0x0E: /* Core */ | |
125 | case 0x0F: /* Core Duo */ | |
8529154e | 126 | case 0x16: /* Celeron Core */ |
43195037 | 127 | case 0x1C: /* Atom */ |
4e74663c | 128 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; |
bbfebd66 | 129 | return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE); |
4e74663c DB |
130 | case 0x0D: /* Pentium M (Dothan) */ |
131 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
df561f66 | 132 | fallthrough; |
4e74663c | 133 | case 0x09: /* Pentium M (Banias) */ |
bbfebd66 | 134 | return speedstep_get_frequency(SPEEDSTEP_CPU_PM); |
4e74663c | 135 | } |
1da177e4 LT |
136 | } |
137 | ||
9d1f44ee | 138 | if (c->x86 != 0xF) |
1da177e4 | 139 | return 0; |
1da177e4 LT |
140 | |
141 | /* on P-4s, the TSC runs with constant frequency independent whether | |
142 | * throttling is active or not. */ | |
143 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
144 | ||
bbfebd66 | 145 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) { |
1c5864e2 | 146 | pr_warn("Warning: Pentium 4-M detected. The speedstep-ich or acpi cpufreq modules offer voltage scaling in addition of frequency scaling. You should use either one instead of p4-clockmod, if possible.\n"); |
bbfebd66 | 147 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4M); |
1da177e4 LT |
148 | } |
149 | ||
bbfebd66 | 150 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4D); |
1da177e4 LT |
151 | } |
152 | ||
32ee8c3e | 153 | |
1da177e4 LT |
154 | |
155 | static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy) | |
156 | { | |
92cb7612 | 157 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
1da177e4 LT |
158 | int cpuid = 0; |
159 | unsigned int i; | |
160 | ||
161 | #ifdef CONFIG_SMP | |
b60f9a7e | 162 | cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu)); |
1da177e4 LT |
163 | #endif |
164 | ||
165 | /* Errata workaround */ | |
b399151c | 166 | cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping; |
1da177e4 LT |
167 | switch (cpuid) { |
168 | case 0x0f07: | |
169 | case 0x0f0a: | |
170 | case 0x0f11: | |
171 | case 0x0f12: | |
172 | has_N44_O17_errata[policy->cpu] = 1; | |
2d06d8c4 | 173 | pr_debug("has errata -- disabling low frequencies\n"); |
1da177e4 | 174 | } |
32ee8c3e | 175 | |
199785ea MCO |
176 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D && |
177 | c->x86_model < 2) { | |
178 | /* switch to maximum frequency and measure result */ | |
179 | cpufreq_p4_setdc(policy->cpu, DC_DISABLE); | |
180 | recalibrate_cpu_khz(); | |
181 | } | |
1da177e4 LT |
182 | /* get max frequency */ |
183 | stock_freq = cpufreq_p4_get_frequency(c); | |
184 | if (!stock_freq) | |
185 | return -EINVAL; | |
186 | ||
187 | /* table init */ | |
bbfebd66 DJ |
188 | for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) { |
189 | if ((i < 2) && (has_N44_O17_errata[policy->cpu])) | |
1da177e4 LT |
190 | p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID; |
191 | else | |
192 | p4clockmod_table[i].frequency = (stock_freq * i)/8; | |
193 | } | |
32ee8c3e | 194 | |
1da177e4 | 195 | /* cpuinfo and default policy values */ |
36e8abf3 DJ |
196 | |
197 | /* the transition latency is set to be 1 higher than the maximum | |
198 | * transition latency of the ondemand governor */ | |
199 | policy->cpuinfo.transition_latency = 10000001; | |
b01b531f | 200 | policy->freq_table = &p4clockmod_table[0]; |
1da177e4 | 201 | |
b01b531f | 202 | return 0; |
1da177e4 LT |
203 | } |
204 | ||
205 | ||
1da177e4 LT |
206 | static unsigned int cpufreq_p4_get(unsigned int cpu) |
207 | { | |
1da177e4 LT |
208 | u32 l, h; |
209 | ||
551948bc | 210 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 LT |
211 | |
212 | if (l & 0x10) { | |
213 | l = l >> 1; | |
214 | l &= 0x7; | |
215 | } else | |
216 | l = DC_DISABLE; | |
217 | ||
218 | if (l != DC_DISABLE) | |
bbfebd66 | 219 | return stock_freq * l / 8; |
1da177e4 LT |
220 | |
221 | return stock_freq; | |
222 | } | |
223 | ||
1da177e4 | 224 | static struct cpufreq_driver p4clockmod_driver = { |
522f70ce | 225 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 226 | .target_index = cpufreq_p4_target, |
1da177e4 | 227 | .init = cpufreq_p4_cpu_init, |
1da177e4 LT |
228 | .get = cpufreq_p4_get, |
229 | .name = "p4-clockmod", | |
522f70ce | 230 | .attr = cpufreq_generic_attr, |
1da177e4 LT |
231 | }; |
232 | ||
fa8031ae | 233 | static const struct x86_cpu_id cpufreq_p4_id[] = { |
b11d77fa | 234 | X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_ACC, NULL), |
fa8031ae AK |
235 | {} |
236 | }; | |
237 | ||
238 | /* | |
239 | * Intentionally no MODULE_DEVICE_TABLE here: this driver should not | |
240 | * be auto loaded. Please don't add one. | |
241 | */ | |
1da177e4 LT |
242 | |
243 | static int __init cpufreq_p4_init(void) | |
32ee8c3e | 244 | { |
1da177e4 LT |
245 | int ret; |
246 | ||
247 | /* | |
32ee8c3e | 248 | * THERM_CONTROL is architectural for IA32 now, so |
1da177e4 LT |
249 | * we can rely on the capability checks |
250 | */ | |
fa8031ae | 251 | if (!x86_match_cpu(cpufreq_p4_id) || !boot_cpu_has(X86_FEATURE_ACPI)) |
1da177e4 LT |
252 | return -ENODEV; |
253 | ||
254 | ret = cpufreq_register_driver(&p4clockmod_driver); | |
255 | if (!ret) | |
1c5864e2 | 256 | pr_info("P4/Xeon(TM) CPU On-Demand Clock Modulation available\n"); |
1da177e4 | 257 | |
bbfebd66 | 258 | return ret; |
1da177e4 LT |
259 | } |
260 | ||
261 | ||
262 | static void __exit cpufreq_p4_exit(void) | |
263 | { | |
264 | cpufreq_unregister_driver(&p4clockmod_driver); | |
265 | } | |
266 | ||
267 | ||
bbfebd66 DJ |
268 | MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>"); |
269 | MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)"); | |
270 | MODULE_LICENSE("GPL"); | |
1da177e4 LT |
271 | |
272 | late_initcall(cpufreq_p4_init); | |
273 | module_exit(cpufreq_p4_exit); |