Merge tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel...
[linux-2.6-block.git] / drivers / cpufreq / omap-cpufreq.c
CommitLineData
ec6bced6 1/*
ffe4f0f1 2 * CPU frequency scaling for OMAP using OPP information
ec6bced6
TL
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Written by Tony Lindgren <tony@atomide.com>
6 *
7 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
8 *
731e0cc6
SS
9 * Copyright (C) 2007-2011 Texas Instruments, Inc.
10 * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
11 *
ec6bced6
TL
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/sched.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
fced80c7 24#include <linux/io.h>
e4db1c74 25#include <linux/pm_opp.h>
46c12216 26#include <linux/cpu.h>
c1b547bc 27#include <linux/module.h>
49ded525 28#include <linux/platform_device.h>
53dfe8a8 29#include <linux/regulator/consumer.h>
ec6bced6 30
731e0cc6 31#include <asm/smp_plat.h>
46c12216 32#include <asm/cpu.h>
ec6bced6 33
42daffd2
AM
34/* OPP tolerance in percentage */
35#define OPP_TOLERANCE 4
36
731e0cc6 37static struct cpufreq_frequency_table *freq_table;
1c78217f 38static atomic_t freq_table_users = ATOMIC_INIT(0);
a820ffa8 39static struct device *mpu_dev;
53dfe8a8 40static struct regulator *mpu_reg;
b8488fbe 41
9c0ebcf7 42static int omap_target(struct cpufreq_policy *policy, unsigned int index)
ec6bced6 43{
696d0b2c 44 int r, ret;
47d43ba7 45 struct dev_pm_opp *opp;
42daffd2 46 unsigned long freq, volt = 0, volt_old = 0, tol = 0;
d4019f0a 47 unsigned int old_freq, new_freq;
ec6bced6 48
652ed95d 49 old_freq = policy->cur;
d4019f0a 50 new_freq = freq_table[index].frequency;
aeec2990 51
d4019f0a 52 freq = new_freq * 1000;
652ed95d 53 ret = clk_round_rate(policy->clk, freq);
8df0a663
KH
54 if (IS_ERR_VALUE(ret)) {
55 dev_warn(mpu_dev,
56 "CPUfreq: Cannot find matching frequency for %lu\n",
57 freq);
58 return ret;
59 }
60 freq = ret;
53dfe8a8
KH
61
62 if (mpu_reg) {
f44d188a 63 rcu_read_lock();
5d4879cd 64 opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq);
53dfe8a8 65 if (IS_ERR(opp)) {
f44d188a 66 rcu_read_unlock();
53dfe8a8 67 dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
d4019f0a 68 __func__, new_freq);
53dfe8a8
KH
69 return -EINVAL;
70 }
5d4879cd 71 volt = dev_pm_opp_get_voltage(opp);
f44d188a 72 rcu_read_unlock();
42daffd2 73 tol = volt * OPP_TOLERANCE / 100;
53dfe8a8
KH
74 volt_old = regulator_get_voltage(mpu_reg);
75 }
76
77 dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a
VK
78 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
79 new_freq / 1000, volt ? volt / 1000 : -1);
44a49a23 80
53dfe8a8 81 /* scaling up? scale voltage before frequency */
d4019f0a 82 if (mpu_reg && (new_freq > old_freq)) {
42daffd2 83 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
84 if (r < 0) {
85 dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
86 __func__);
d4019f0a 87 return r;
53dfe8a8
KH
88 }
89 }
731e0cc6 90
652ed95d 91 ret = clk_set_rate(policy->clk, new_freq * 1000);
46c12216 92
53dfe8a8 93 /* scaling down? scale voltage after frequency */
d4019f0a 94 if (mpu_reg && (new_freq < old_freq)) {
42daffd2 95 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
96 if (r < 0) {
97 dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
98 __func__);
652ed95d 99 clk_set_rate(policy->clk, old_freq * 1000);
d4019f0a 100 return r;
53dfe8a8
KH
101 }
102 }
103
ec6bced6
TL
104 return ret;
105}
106
1c78217f
NM
107static inline void freq_table_free(void)
108{
109 if (atomic_dec_and_test(&freq_table_users))
5d4879cd 110 dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table);
1c78217f
NM
111}
112
2760984f 113static int omap_cpu_init(struct cpufreq_policy *policy)
ec6bced6 114{
982bce11 115 int result;
731e0cc6 116
652ed95d
VK
117 policy->clk = clk_get(NULL, "cpufreq_ck");
118 if (IS_ERR(policy->clk))
119 return PTR_ERR(policy->clk);
ec6bced6 120
982bce11 121 if (!freq_table) {
5d4879cd 122 result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table);
982bce11
VK
123 if (result) {
124 dev_err(mpu_dev,
125 "%s: cpu%d: failed creating freq table[%d]\n",
bf2a359d 126 __func__, policy->cpu, result);
982bce11
VK
127 goto fail;
128 }
aeec2990
KH
129 }
130
1b865214
RN
131 atomic_inc_return(&freq_table_users);
132
aeec2990 133 /* FIXME: what's the actual transition time? */
982bce11
VK
134 result = cpufreq_generic_init(policy, freq_table, 300 * 1000);
135 if (!result)
136 return 0;
11e04fdd 137
1c78217f 138 freq_table_free();
982bce11 139fail:
652ed95d 140 clk_put(policy->clk);
11e04fdd 141 return result;
ec6bced6
TL
142}
143
b8488fbe
HD
144static int omap_cpu_exit(struct cpufreq_policy *policy)
145{
1c78217f 146 freq_table_free();
652ed95d 147 clk_put(policy->clk);
b8488fbe
HD
148 return 0;
149}
150
ec6bced6 151static struct cpufreq_driver omap_driver = {
ae6b4271 152 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
d5ca1649 153 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 154 .target_index = omap_target,
652ed95d 155 .get = cpufreq_generic_get,
ec6bced6 156 .init = omap_cpu_init,
b8488fbe 157 .exit = omap_cpu_exit,
ec6bced6 158 .name = "omap",
d5ca1649 159 .attr = cpufreq_generic_attr,
ec6bced6
TL
160};
161
49ded525 162static int omap_cpufreq_probe(struct platform_device *pdev)
ec6bced6 163{
747a7f64
KH
164 mpu_dev = get_cpu_device(0);
165 if (!mpu_dev) {
a820ffa8 166 pr_warning("%s: unable to get the mpu device\n", __func__);
747a7f64 167 return -EINVAL;
a820ffa8
NM
168 }
169
53dfe8a8
KH
170 mpu_reg = regulator_get(mpu_dev, "vcc");
171 if (IS_ERR(mpu_reg)) {
172 pr_warning("%s: unable to get MPU regulator\n", __func__);
173 mpu_reg = NULL;
174 } else {
175 /*
176 * Ensure physical regulator is present.
177 * (e.g. could be dummy regulator.)
178 */
179 if (regulator_get_voltage(mpu_reg) < 0) {
180 pr_warn("%s: physical regulator not present for MPU\n",
181 __func__);
182 regulator_put(mpu_reg);
183 mpu_reg = NULL;
184 }
185 }
186
ec6bced6
TL
187 return cpufreq_register_driver(&omap_driver);
188}
189
49ded525 190static int omap_cpufreq_remove(struct platform_device *pdev)
731e0cc6 191{
49ded525 192 return cpufreq_unregister_driver(&omap_driver);
731e0cc6 193}
aeec2990 194
49ded525
NM
195static struct platform_driver omap_cpufreq_platdrv = {
196 .driver = {
197 .name = "omap-cpufreq",
49ded525
NM
198 },
199 .probe = omap_cpufreq_probe,
200 .remove = omap_cpufreq_remove,
201};
202module_platform_driver(omap_cpufreq_platdrv);
203
731e0cc6
SS
204MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
205MODULE_LICENSE("GPL");