cpufreq / intel_pstate: Set timer timeout correctly
[linux-2.6-block.git] / drivers / cpufreq / omap-cpufreq.c
CommitLineData
ec6bced6 1/*
ffe4f0f1 2 * CPU frequency scaling for OMAP using OPP information
ec6bced6
TL
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Written by Tony Lindgren <tony@atomide.com>
6 *
7 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
8 *
731e0cc6
SS
9 * Copyright (C) 2007-2011 Texas Instruments, Inc.
10 * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
11 *
ec6bced6
TL
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/sched.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
fced80c7 24#include <linux/io.h>
731e0cc6 25#include <linux/opp.h>
46c12216 26#include <linux/cpu.h>
c1b547bc 27#include <linux/module.h>
53dfe8a8 28#include <linux/regulator/consumer.h>
ec6bced6 29
731e0cc6 30#include <asm/smp_plat.h>
46c12216 31#include <asm/cpu.h>
ec6bced6 32
42daffd2
AM
33/* OPP tolerance in percentage */
34#define OPP_TOLERANCE 4
35
731e0cc6 36static struct cpufreq_frequency_table *freq_table;
1c78217f 37static atomic_t freq_table_users = ATOMIC_INIT(0);
b8488fbe 38static struct clk *mpu_clk;
a820ffa8 39static struct device *mpu_dev;
53dfe8a8 40static struct regulator *mpu_reg;
b8488fbe 41
b0a330dc 42static int omap_verify_speed(struct cpufreq_policy *policy)
ec6bced6 43{
bf2a359d 44 if (!freq_table)
ec6bced6 45 return -EINVAL;
bf2a359d 46 return cpufreq_frequency_table_verify(policy, freq_table);
ec6bced6
TL
47}
48
b0a330dc 49static unsigned int omap_getspeed(unsigned int cpu)
ec6bced6 50{
ec6bced6
TL
51 unsigned long rate;
52
46c12216 53 if (cpu >= NR_CPUS)
ec6bced6
TL
54 return 0;
55
ec6bced6 56 rate = clk_get_rate(mpu_clk) / 1000;
ec6bced6
TL
57 return rate;
58}
59
60static int omap_target(struct cpufreq_policy *policy,
61 unsigned int target_freq,
62 unsigned int relation)
63{
bf2a359d 64 unsigned int i;
53dfe8a8 65 int r, ret = 0;
731e0cc6 66 struct cpufreq_freqs freqs;
53dfe8a8 67 struct opp *opp;
42daffd2 68 unsigned long freq, volt = 0, volt_old = 0, tol = 0;
ec6bced6 69
bf2a359d
NM
70 if (!freq_table) {
71 dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
72 policy->cpu);
73 return -EINVAL;
74 }
75
76 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
77 relation, &i);
78 if (ret) {
79 dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
80 __func__, policy->cpu, target_freq, ret);
81 return ret;
82 }
83 freqs.new = freq_table[i].frequency;
84 if (!freqs.new) {
85 dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
86 policy->cpu, target_freq);
87 return -EINVAL;
88 }
aeec2990 89
46c12216 90 freqs.old = omap_getspeed(policy->cpu);
46c12216 91 freqs.cpu = policy->cpu;
ec6bced6 92
022ac03b 93 if (freqs.old == freqs.new && policy->cur == freqs.new)
aeec2990
KH
94 return ret;
95
46c12216
RK
96 /* notifiers */
97 for_each_cpu(i, policy->cpus) {
98 freqs.cpu = i;
99 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
100 }
731e0cc6 101
53dfe8a8 102 freq = freqs.new * 1000;
8df0a663
KH
103 ret = clk_round_rate(mpu_clk, freq);
104 if (IS_ERR_VALUE(ret)) {
105 dev_warn(mpu_dev,
106 "CPUfreq: Cannot find matching frequency for %lu\n",
107 freq);
108 return ret;
109 }
110 freq = ret;
53dfe8a8
KH
111
112 if (mpu_reg) {
f44d188a 113 rcu_read_lock();
53dfe8a8
KH
114 opp = opp_find_freq_ceil(mpu_dev, &freq);
115 if (IS_ERR(opp)) {
f44d188a 116 rcu_read_unlock();
53dfe8a8
KH
117 dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
118 __func__, freqs.new);
119 return -EINVAL;
120 }
121 volt = opp_get_voltage(opp);
f44d188a 122 rcu_read_unlock();
42daffd2 123 tol = volt * OPP_TOLERANCE / 100;
53dfe8a8
KH
124 volt_old = regulator_get_voltage(mpu_reg);
125 }
126
127 dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n",
128 freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
129 freqs.new / 1000, volt ? volt / 1000 : -1);
130
131 /* scaling up? scale voltage before frequency */
132 if (mpu_reg && (freqs.new > freqs.old)) {
42daffd2 133 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
134 if (r < 0) {
135 dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
136 __func__);
137 freqs.new = freqs.old;
138 goto done;
139 }
140 }
731e0cc6 141
aeec2990 142 ret = clk_set_rate(mpu_clk, freqs.new * 1000);
46c12216 143
53dfe8a8
KH
144 /* scaling down? scale voltage after frequency */
145 if (mpu_reg && (freqs.new < freqs.old)) {
42daffd2 146 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
147 if (r < 0) {
148 dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
149 __func__);
150 ret = clk_set_rate(mpu_clk, freqs.old * 1000);
151 freqs.new = freqs.old;
152 goto done;
153 }
154 }
155
156 freqs.new = omap_getspeed(policy->cpu);
46c12216 157
53dfe8a8 158done:
46c12216
RK
159 /* notifiers */
160 for_each_cpu(i, policy->cpus) {
161 freqs.cpu = i;
162 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
163 }
ec6bced6
TL
164
165 return ret;
166}
167
1c78217f
NM
168static inline void freq_table_free(void)
169{
170 if (atomic_dec_and_test(&freq_table_users))
171 opp_free_cpufreq_table(mpu_dev, &freq_table);
172}
173
790ab7e9 174static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
ec6bced6 175{
aeec2990 176 int result = 0;
731e0cc6 177
e2ee1b4d 178 mpu_clk = clk_get(NULL, "cpufreq_ck");
ec6bced6
TL
179 if (IS_ERR(mpu_clk))
180 return PTR_ERR(mpu_clk);
181
11e04fdd
NM
182 if (policy->cpu >= NR_CPUS) {
183 result = -EINVAL;
184 goto fail_ck;
185 }
aeec2990 186
46c12216 187 policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
1c78217f 188
1b865214 189 if (!freq_table)
1c78217f 190 result = opp_init_cpufreq_table(mpu_dev, &freq_table);
bf2a359d
NM
191
192 if (result) {
193 dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
194 __func__, policy->cpu, result);
11e04fdd 195 goto fail_ck;
aeec2990
KH
196 }
197
1b865214
RN
198 atomic_inc_return(&freq_table_users);
199
bf2a359d 200 result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
1c78217f
NM
201 if (result)
202 goto fail_table;
203
204 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
bf2a359d 205
731e0cc6
SS
206 policy->min = policy->cpuinfo.min_freq;
207 policy->max = policy->cpuinfo.max_freq;
46c12216
RK
208 policy->cur = omap_getspeed(policy->cpu);
209
210 /*
211 * On OMAP SMP configuartion, both processors share the voltage
212 * and clock. So both CPUs needs to be scaled together and hence
213 * needs software co-ordination. Use cpufreq affected_cpus
214 * interface to handle this scenario. Additional is_smp() check
215 * is to keep SMP_ON_UP build working.
216 */
62b36cc1 217 if (is_smp())
ed8ce00c 218 cpumask_setall(policy->cpus);
731e0cc6 219
aeec2990 220 /* FIXME: what's the actual transition time? */
b029839c 221 policy->cpuinfo.transition_latency = 300 * 1000;
ec6bced6
TL
222
223 return 0;
11e04fdd 224
1c78217f
NM
225fail_table:
226 freq_table_free();
11e04fdd
NM
227fail_ck:
228 clk_put(mpu_clk);
229 return result;
ec6bced6
TL
230}
231
b8488fbe
HD
232static int omap_cpu_exit(struct cpufreq_policy *policy)
233{
1c78217f 234 freq_table_free();
b8488fbe
HD
235 clk_put(mpu_clk);
236 return 0;
237}
238
aeec2990
KH
239static struct freq_attr *omap_cpufreq_attr[] = {
240 &cpufreq_freq_attr_scaling_available_freqs,
241 NULL,
242};
243
ec6bced6
TL
244static struct cpufreq_driver omap_driver = {
245 .flags = CPUFREQ_STICKY,
246 .verify = omap_verify_speed,
247 .target = omap_target,
248 .get = omap_getspeed,
249 .init = omap_cpu_init,
b8488fbe 250 .exit = omap_cpu_exit,
ec6bced6 251 .name = "omap",
aeec2990 252 .attr = omap_cpufreq_attr,
ec6bced6
TL
253};
254
255static int __init omap_cpufreq_init(void)
256{
747a7f64
KH
257 mpu_dev = get_cpu_device(0);
258 if (!mpu_dev) {
a820ffa8 259 pr_warning("%s: unable to get the mpu device\n", __func__);
747a7f64 260 return -EINVAL;
a820ffa8
NM
261 }
262
53dfe8a8
KH
263 mpu_reg = regulator_get(mpu_dev, "vcc");
264 if (IS_ERR(mpu_reg)) {
265 pr_warning("%s: unable to get MPU regulator\n", __func__);
266 mpu_reg = NULL;
267 } else {
268 /*
269 * Ensure physical regulator is present.
270 * (e.g. could be dummy regulator.)
271 */
272 if (regulator_get_voltage(mpu_reg) < 0) {
273 pr_warn("%s: physical regulator not present for MPU\n",
274 __func__);
275 regulator_put(mpu_reg);
276 mpu_reg = NULL;
277 }
278 }
279
ec6bced6
TL
280 return cpufreq_register_driver(&omap_driver);
281}
282
731e0cc6
SS
283static void __exit omap_cpufreq_exit(void)
284{
285 cpufreq_unregister_driver(&omap_driver);
286}
aeec2990 287
731e0cc6
SS
288MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
289MODULE_LICENSE("GPL");
290module_init(omap_cpufreq_init);
291module_exit(omap_cpufreq_exit);