Commit | Line | Data |
---|---|---|
ec6bced6 | 1 | /* |
ffe4f0f1 | 2 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
3 | * |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Written by Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
8 | * | |
731e0cc6 SS |
9 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
10 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
11 | * | |
ec6bced6 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
1c5864e2 JP |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
18 | ||
ec6bced6 TL |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/err.h> | |
f8ce2547 | 26 | #include <linux/clk.h> |
fced80c7 | 27 | #include <linux/io.h> |
e4db1c74 | 28 | #include <linux/pm_opp.h> |
46c12216 | 29 | #include <linux/cpu.h> |
c1b547bc | 30 | #include <linux/module.h> |
49ded525 | 31 | #include <linux/platform_device.h> |
53dfe8a8 | 32 | #include <linux/regulator/consumer.h> |
ec6bced6 | 33 | |
731e0cc6 | 34 | #include <asm/smp_plat.h> |
46c12216 | 35 | #include <asm/cpu.h> |
ec6bced6 | 36 | |
42daffd2 AM |
37 | /* OPP tolerance in percentage */ |
38 | #define OPP_TOLERANCE 4 | |
39 | ||
731e0cc6 | 40 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 41 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
a820ffa8 | 42 | static struct device *mpu_dev; |
53dfe8a8 | 43 | static struct regulator *mpu_reg; |
b8488fbe | 44 | |
9c0ebcf7 | 45 | static int omap_target(struct cpufreq_policy *policy, unsigned int index) |
ec6bced6 | 46 | { |
696d0b2c | 47 | int r, ret; |
47d43ba7 | 48 | struct dev_pm_opp *opp; |
42daffd2 | 49 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
d4019f0a | 50 | unsigned int old_freq, new_freq; |
ec6bced6 | 51 | |
652ed95d | 52 | old_freq = policy->cur; |
d4019f0a | 53 | new_freq = freq_table[index].frequency; |
aeec2990 | 54 | |
d4019f0a | 55 | freq = new_freq * 1000; |
652ed95d | 56 | ret = clk_round_rate(policy->clk, freq); |
287980e4 | 57 | if (ret < 0) { |
8df0a663 KH |
58 | dev_warn(mpu_dev, |
59 | "CPUfreq: Cannot find matching frequency for %lu\n", | |
60 | freq); | |
61 | return ret; | |
62 | } | |
63 | freq = ret; | |
53dfe8a8 KH |
64 | |
65 | if (mpu_reg) { | |
5d4879cd | 66 | opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq); |
53dfe8a8 KH |
67 | if (IS_ERR(opp)) { |
68 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", | |
d4019f0a | 69 | __func__, new_freq); |
53dfe8a8 KH |
70 | return -EINVAL; |
71 | } | |
5d4879cd | 72 | volt = dev_pm_opp_get_voltage(opp); |
8a31d9d9 | 73 | dev_pm_opp_put(opp); |
42daffd2 | 74 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
75 | volt_old = regulator_get_voltage(mpu_reg); |
76 | } | |
77 | ||
78 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
d4019f0a VK |
79 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
80 | new_freq / 1000, volt ? volt / 1000 : -1); | |
44a49a23 | 81 | |
53dfe8a8 | 82 | /* scaling up? scale voltage before frequency */ |
d4019f0a | 83 | if (mpu_reg && (new_freq > old_freq)) { |
42daffd2 | 84 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
85 | if (r < 0) { |
86 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
87 | __func__); | |
d4019f0a | 88 | return r; |
53dfe8a8 KH |
89 | } |
90 | } | |
731e0cc6 | 91 | |
652ed95d | 92 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
46c12216 | 93 | |
53dfe8a8 | 94 | /* scaling down? scale voltage after frequency */ |
d4019f0a | 95 | if (mpu_reg && (new_freq < old_freq)) { |
42daffd2 | 96 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
97 | if (r < 0) { |
98 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
99 | __func__); | |
652ed95d | 100 | clk_set_rate(policy->clk, old_freq * 1000); |
d4019f0a | 101 | return r; |
53dfe8a8 KH |
102 | } |
103 | } | |
104 | ||
ec6bced6 TL |
105 | return ret; |
106 | } | |
107 | ||
1c78217f NM |
108 | static inline void freq_table_free(void) |
109 | { | |
110 | if (atomic_dec_and_test(&freq_table_users)) | |
5d4879cd | 111 | dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table); |
1c78217f NM |
112 | } |
113 | ||
2760984f | 114 | static int omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 115 | { |
982bce11 | 116 | int result; |
731e0cc6 | 117 | |
652ed95d VK |
118 | policy->clk = clk_get(NULL, "cpufreq_ck"); |
119 | if (IS_ERR(policy->clk)) | |
120 | return PTR_ERR(policy->clk); | |
ec6bced6 | 121 | |
982bce11 | 122 | if (!freq_table) { |
5d4879cd | 123 | result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table); |
982bce11 VK |
124 | if (result) { |
125 | dev_err(mpu_dev, | |
126 | "%s: cpu%d: failed creating freq table[%d]\n", | |
bf2a359d | 127 | __func__, policy->cpu, result); |
982bce11 VK |
128 | goto fail; |
129 | } | |
aeec2990 KH |
130 | } |
131 | ||
1b865214 RN |
132 | atomic_inc_return(&freq_table_users); |
133 | ||
aeec2990 | 134 | /* FIXME: what's the actual transition time? */ |
982bce11 VK |
135 | result = cpufreq_generic_init(policy, freq_table, 300 * 1000); |
136 | if (!result) | |
137 | return 0; | |
11e04fdd | 138 | |
1c78217f | 139 | freq_table_free(); |
982bce11 | 140 | fail: |
652ed95d | 141 | clk_put(policy->clk); |
11e04fdd | 142 | return result; |
ec6bced6 TL |
143 | } |
144 | ||
b8488fbe HD |
145 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
146 | { | |
1c78217f | 147 | freq_table_free(); |
652ed95d | 148 | clk_put(policy->clk); |
b8488fbe HD |
149 | return 0; |
150 | } | |
151 | ||
ec6bced6 | 152 | static struct cpufreq_driver omap_driver = { |
ae6b4271 | 153 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
d5ca1649 | 154 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 155 | .target_index = omap_target, |
652ed95d | 156 | .get = cpufreq_generic_get, |
ec6bced6 | 157 | .init = omap_cpu_init, |
b8488fbe | 158 | .exit = omap_cpu_exit, |
ec6bced6 | 159 | .name = "omap", |
d5ca1649 | 160 | .attr = cpufreq_generic_attr, |
ec6bced6 TL |
161 | }; |
162 | ||
49ded525 | 163 | static int omap_cpufreq_probe(struct platform_device *pdev) |
ec6bced6 | 164 | { |
747a7f64 KH |
165 | mpu_dev = get_cpu_device(0); |
166 | if (!mpu_dev) { | |
1c5864e2 | 167 | pr_warn("%s: unable to get the MPU device\n", __func__); |
747a7f64 | 168 | return -EINVAL; |
a820ffa8 NM |
169 | } |
170 | ||
53dfe8a8 KH |
171 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
172 | if (IS_ERR(mpu_reg)) { | |
b49c22a6 | 173 | pr_warn("%s: unable to get MPU regulator\n", __func__); |
53dfe8a8 KH |
174 | mpu_reg = NULL; |
175 | } else { | |
176 | /* | |
177 | * Ensure physical regulator is present. | |
178 | * (e.g. could be dummy regulator.) | |
179 | */ | |
180 | if (regulator_get_voltage(mpu_reg) < 0) { | |
181 | pr_warn("%s: physical regulator not present for MPU\n", | |
182 | __func__); | |
183 | regulator_put(mpu_reg); | |
184 | mpu_reg = NULL; | |
185 | } | |
186 | } | |
187 | ||
ec6bced6 TL |
188 | return cpufreq_register_driver(&omap_driver); |
189 | } | |
190 | ||
49ded525 | 191 | static int omap_cpufreq_remove(struct platform_device *pdev) |
731e0cc6 | 192 | { |
49ded525 | 193 | return cpufreq_unregister_driver(&omap_driver); |
731e0cc6 | 194 | } |
aeec2990 | 195 | |
49ded525 NM |
196 | static struct platform_driver omap_cpufreq_platdrv = { |
197 | .driver = { | |
198 | .name = "omap-cpufreq", | |
49ded525 NM |
199 | }, |
200 | .probe = omap_cpufreq_probe, | |
201 | .remove = omap_cpufreq_remove, | |
202 | }; | |
203 | module_platform_driver(omap_cpufreq_platdrv); | |
204 | ||
731e0cc6 SS |
205 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
206 | MODULE_LICENSE("GPL"); |