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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ec6bced6 | 2 | /* |
ffe4f0f1 | 3 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
4 | * |
5 | * Copyright (C) 2005 Nokia Corporation | |
6 | * Written by Tony Lindgren <tony@atomide.com> | |
7 | * | |
8 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
9 | * | |
731e0cc6 SS |
10 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
11 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
ec6bced6 | 12 | */ |
1c5864e2 JP |
13 | |
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
15 | ||
ec6bced6 TL |
16 | #include <linux/types.h> |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/cpufreq.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
e4db1c74 | 25 | #include <linux/pm_opp.h> |
46c12216 | 26 | #include <linux/cpu.h> |
c1b547bc | 27 | #include <linux/module.h> |
49ded525 | 28 | #include <linux/platform_device.h> |
53dfe8a8 | 29 | #include <linux/regulator/consumer.h> |
ec6bced6 | 30 | |
731e0cc6 | 31 | #include <asm/smp_plat.h> |
46c12216 | 32 | #include <asm/cpu.h> |
ec6bced6 | 33 | |
42daffd2 AM |
34 | /* OPP tolerance in percentage */ |
35 | #define OPP_TOLERANCE 4 | |
36 | ||
731e0cc6 | 37 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 38 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
a820ffa8 | 39 | static struct device *mpu_dev; |
53dfe8a8 | 40 | static struct regulator *mpu_reg; |
b8488fbe | 41 | |
9c0ebcf7 | 42 | static int omap_target(struct cpufreq_policy *policy, unsigned int index) |
ec6bced6 | 43 | { |
696d0b2c | 44 | int r, ret; |
47d43ba7 | 45 | struct dev_pm_opp *opp; |
42daffd2 | 46 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
d4019f0a | 47 | unsigned int old_freq, new_freq; |
ec6bced6 | 48 | |
652ed95d | 49 | old_freq = policy->cur; |
d4019f0a | 50 | new_freq = freq_table[index].frequency; |
aeec2990 | 51 | |
d4019f0a | 52 | freq = new_freq * 1000; |
652ed95d | 53 | ret = clk_round_rate(policy->clk, freq); |
287980e4 | 54 | if (ret < 0) { |
8df0a663 KH |
55 | dev_warn(mpu_dev, |
56 | "CPUfreq: Cannot find matching frequency for %lu\n", | |
57 | freq); | |
58 | return ret; | |
59 | } | |
60 | freq = ret; | |
53dfe8a8 KH |
61 | |
62 | if (mpu_reg) { | |
5d4879cd | 63 | opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq); |
53dfe8a8 KH |
64 | if (IS_ERR(opp)) { |
65 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", | |
d4019f0a | 66 | __func__, new_freq); |
53dfe8a8 KH |
67 | return -EINVAL; |
68 | } | |
5d4879cd | 69 | volt = dev_pm_opp_get_voltage(opp); |
8a31d9d9 | 70 | dev_pm_opp_put(opp); |
42daffd2 | 71 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
72 | volt_old = regulator_get_voltage(mpu_reg); |
73 | } | |
74 | ||
75 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
d4019f0a VK |
76 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
77 | new_freq / 1000, volt ? volt / 1000 : -1); | |
44a49a23 | 78 | |
53dfe8a8 | 79 | /* scaling up? scale voltage before frequency */ |
d4019f0a | 80 | if (mpu_reg && (new_freq > old_freq)) { |
42daffd2 | 81 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
82 | if (r < 0) { |
83 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
84 | __func__); | |
d4019f0a | 85 | return r; |
53dfe8a8 KH |
86 | } |
87 | } | |
731e0cc6 | 88 | |
652ed95d | 89 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
46c12216 | 90 | |
53dfe8a8 | 91 | /* scaling down? scale voltage after frequency */ |
d4019f0a | 92 | if (mpu_reg && (new_freq < old_freq)) { |
42daffd2 | 93 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
94 | if (r < 0) { |
95 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
96 | __func__); | |
652ed95d | 97 | clk_set_rate(policy->clk, old_freq * 1000); |
d4019f0a | 98 | return r; |
53dfe8a8 KH |
99 | } |
100 | } | |
101 | ||
ec6bced6 TL |
102 | return ret; |
103 | } | |
104 | ||
1c78217f NM |
105 | static inline void freq_table_free(void) |
106 | { | |
107 | if (atomic_dec_and_test(&freq_table_users)) | |
5d4879cd | 108 | dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table); |
1c78217f NM |
109 | } |
110 | ||
2760984f | 111 | static int omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 112 | { |
982bce11 | 113 | int result; |
731e0cc6 | 114 | |
652ed95d VK |
115 | policy->clk = clk_get(NULL, "cpufreq_ck"); |
116 | if (IS_ERR(policy->clk)) | |
117 | return PTR_ERR(policy->clk); | |
ec6bced6 | 118 | |
982bce11 | 119 | if (!freq_table) { |
5d4879cd | 120 | result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table); |
982bce11 VK |
121 | if (result) { |
122 | dev_err(mpu_dev, | |
123 | "%s: cpu%d: failed creating freq table[%d]\n", | |
bf2a359d | 124 | __func__, policy->cpu, result); |
c4dcc8a1 VK |
125 | clk_put(policy->clk); |
126 | return result; | |
982bce11 | 127 | } |
aeec2990 KH |
128 | } |
129 | ||
1b865214 RN |
130 | atomic_inc_return(&freq_table_users); |
131 | ||
aeec2990 | 132 | /* FIXME: what's the actual transition time? */ |
c4dcc8a1 | 133 | cpufreq_generic_init(policy, freq_table, 300 * 1000); |
11e04fdd | 134 | |
c4dcc8a1 | 135 | return 0; |
ec6bced6 TL |
136 | } |
137 | ||
b8488fbe HD |
138 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
139 | { | |
1c78217f | 140 | freq_table_free(); |
652ed95d | 141 | clk_put(policy->clk); |
b8488fbe HD |
142 | return 0; |
143 | } | |
144 | ||
ec6bced6 | 145 | static struct cpufreq_driver omap_driver = { |
5ae4a4b4 | 146 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
d5ca1649 | 147 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 148 | .target_index = omap_target, |
652ed95d | 149 | .get = cpufreq_generic_get, |
ec6bced6 | 150 | .init = omap_cpu_init, |
b8488fbe | 151 | .exit = omap_cpu_exit, |
361a172d | 152 | .register_em = cpufreq_register_em_with_opp, |
ec6bced6 | 153 | .name = "omap", |
d5ca1649 | 154 | .attr = cpufreq_generic_attr, |
ec6bced6 TL |
155 | }; |
156 | ||
49ded525 | 157 | static int omap_cpufreq_probe(struct platform_device *pdev) |
ec6bced6 | 158 | { |
747a7f64 KH |
159 | mpu_dev = get_cpu_device(0); |
160 | if (!mpu_dev) { | |
1c5864e2 | 161 | pr_warn("%s: unable to get the MPU device\n", __func__); |
747a7f64 | 162 | return -EINVAL; |
a820ffa8 NM |
163 | } |
164 | ||
53dfe8a8 KH |
165 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
166 | if (IS_ERR(mpu_reg)) { | |
b49c22a6 | 167 | pr_warn("%s: unable to get MPU regulator\n", __func__); |
53dfe8a8 KH |
168 | mpu_reg = NULL; |
169 | } else { | |
170 | /* | |
171 | * Ensure physical regulator is present. | |
172 | * (e.g. could be dummy regulator.) | |
173 | */ | |
174 | if (regulator_get_voltage(mpu_reg) < 0) { | |
175 | pr_warn("%s: physical regulator not present for MPU\n", | |
176 | __func__); | |
177 | regulator_put(mpu_reg); | |
178 | mpu_reg = NULL; | |
179 | } | |
180 | } | |
181 | ||
ec6bced6 TL |
182 | return cpufreq_register_driver(&omap_driver); |
183 | } | |
184 | ||
49ded525 | 185 | static int omap_cpufreq_remove(struct platform_device *pdev) |
731e0cc6 | 186 | { |
49ded525 | 187 | return cpufreq_unregister_driver(&omap_driver); |
731e0cc6 | 188 | } |
aeec2990 | 189 | |
49ded525 NM |
190 | static struct platform_driver omap_cpufreq_platdrv = { |
191 | .driver = { | |
192 | .name = "omap-cpufreq", | |
49ded525 NM |
193 | }, |
194 | .probe = omap_cpufreq_probe, | |
195 | .remove = omap_cpufreq_remove, | |
196 | }; | |
197 | module_platform_driver(omap_cpufreq_platdrv); | |
198 | ||
731e0cc6 SS |
199 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
200 | MODULE_LICENSE("GPL"); |