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[linux-block.git] / drivers / cpufreq / intel_pstate.c
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93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
55687da1 22#include <linux/sched/cpufreq.h>
93f0822d
DB		 23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
fbbcdc07 29#include <linux/acpi.h>
d6472302 30#include <linux/vmalloc.h>
93f0822d
DB		 31#include <trace/events/power.h>
32
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
64df1fdf 36#include <asm/cpufeature.h>
5b20c944 37#include <asm/intel-family.h>
93f0822d 38
d77d4888 39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
eabd22c6 40
001c76f0 41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
1b72e7fd 42#define INTEL_CPUFREQ_TRANSITION_DELAY 500
001c76f0 43
9522a2ff
SP		 44#ifdef CONFIG_ACPI
45#include <acpi/processor.h>
17669006 46#include <acpi/cppc_acpi.h>
9522a2ff
SP		 47#endif
48
f0fe3cd7 49#define FRAC_BITS 8
93f0822d
DB		 50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 52
a1c9787d
RW		 53#define EXT_BITS 6
54#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 55#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 57
93f0822d
DB		 58static inline int32_t mul_fp(int32_t x, int32_t y)
59{
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61}
62
7180dddf 63static inline int32_t div_fp(s64 x, s64 y)
93f0822d 64{
7180dddf 65 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 66}
67
d022a65e
DB		 68static inline int ceiling_fp(int32_t x)
69{
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77}
78
ff35f02e
RW		 79static inline int32_t percent_fp(int percent)
80{
81 return div_fp(percent, 100);
82}
83
a1c9787d
RW		 84static inline u64 mul_ext_fp(u64 x, u64 y)
85{
86 return (x * y) >> EXT_FRAC_BITS;
87}
88
89static inline u64 div_ext_fp(u64 x, u64 y)
90{
91 return div64_u64(x << EXT_FRAC_BITS, y);
92}
93
e4c204ce
RW		 94static inline int32_t percent_ext_fp(int percent)
95{
96 return div_ext_fp(percent, 100);
97}
98
13ad7701
SP		 99/**
100 * struct sample - Store performance sample
a1c9787d 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 104 * P state. This can be different than core_avg_perf
13ad7701
SP		 105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
13ad7701
SP		 112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
93f0822d 117struct sample {
a1c9787d 118 int32_t core_avg_perf;
157386b6 119 int32_t busy_scaled;
93f0822d
DB		 120 u64 aperf;
121 u64 mperf;
4055fad3 122 u64 tsc;
a4675fbc 123 u64 time;
93f0822d
DB		 124};
125
13ad7701
SP		 126/**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
93f0822d
DB		 142struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
3bcc6fa9 146 int max_pstate_physical;
b27580b0 147 int scaling;
93f0822d 148 int turbo_pstate;
001c76f0
RW		 149 unsigned int max_freq;
150 unsigned int turbo_freq;
93f0822d
DB		 151};
152
13ad7701
SP		 153/**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
007bea09 166struct vid_data {
21855ff5
DB		 167 int min;
168 int max;
169 int turbo;
007bea09
DB		 170 int32_t ratio;
171};
172
c5a2ee7d
RW		 173/**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
183 * P-state capacity.
184 */
185struct global_params {
186 bool no_turbo;
187 bool turbo_disabled;
188 int max_perf_pct;
189 int min_perf_pct;
eae48f04
SP		 190};
191
13ad7701
SP		 192/**
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
2f1d407a 195 * @policy: CPUFreq policy value
13ad7701 196 * @update_util: CPUFreq utility callback information
4578ee7e 197 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
13ad7701
SP		 200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
13ad7701 202 * @last_sample_time: Last Sample time
6e34e1f2
SP		 203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
13ad7701
SP		 206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
1a4fe38a
SP		 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
9522a2ff
SP		 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
8442885f 219 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
13ad7701
SP		 224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
93f0822d
DB		 227struct cpudata {
228 int cpu;
229
2f1d407a 230 unsigned int policy;
a4675fbc 231 struct update_util_data update_util;
4578ee7e 232 bool update_util_set;
93f0822d 233
93f0822d 234 struct pstate_data pstate;
007bea09 235 struct vid_data vid;
93f0822d 236
09c448d3 237 u64 last_update;
a4675fbc 238 u64 last_sample_time;
6e34e1f2 239 u64 aperf_mperf_shift;
93f0822d
DB		 240 u64 prev_aperf;
241 u64 prev_mperf;
4055fad3 242 u64 prev_tsc;
63d1d656 243 u64 prev_cummulative_iowait;
d37e2b76 244 struct sample sample;
1a4fe38a
SP		 245 int32_t min_perf_ratio;
246 int32_t max_perf_ratio;
9522a2ff
SP		 247#ifdef CONFIG_ACPI
248 struct acpi_processor_performance acpi_perf_data;
249 bool valid_pss_table;
250#endif
09c448d3 251 unsigned int iowait_boost;
984edbdc 252 s16 epp_powersave;
8442885f 253 s16 epp_policy;
984edbdc
SP		 254 s16 epp_default;
255 s16 epp_saved;
93f0822d
DB		 256};
257
258static struct cpudata **all_cpu_data;
13ad7701 259
13ad7701
SP		 260/**
261 * struct pstate_funcs - Per CPU model specific callbacks
262 * @get_max: Callback to get maximum non turbo effective P state
263 * @get_max_physical: Callback to get maximum non turbo physical P state
264 * @get_min: Callback to get minimum P state
265 * @get_turbo: Callback to get turbo P state
266 * @get_scaling: Callback to get frequency scaling factor
267 * @get_val: Callback to convert P state to actual MSR write value
268 * @get_vid: Callback to get VID data for Atom platforms
13ad7701
SP		 269 *
270 * Core and Atom CPU models have different way to get P State limits. This
271 * structure is used to store those callbacks.
272 */
016c8150
DB		 273struct pstate_funcs {
274 int (*get_max)(void);
3bcc6fa9 275 int (*get_max_physical)(void);
016c8150
DB		 276 int (*get_min)(void);
277 int (*get_turbo)(void);
b27580b0 278 int (*get_scaling)(void);
6e34e1f2 279 int (*get_aperf_mperf_shift)(void);
fdfdb2b1 280 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 281 void (*get_vid)(struct cpudata *);
93f0822d
DB		 282};
283
4a7cb7a9 284static struct pstate_funcs pstate_funcs __read_mostly;
5c439053 285
4a7cb7a9 286static int hwp_active __read_mostly;
eae48f04 287static bool per_cpu_limits __read_mostly;
016c8150 288
ee8df89a 289static struct cpufreq_driver *intel_pstate_driver __read_mostly;
0c30b65b 290
9522a2ff
SP		 291#ifdef CONFIG_ACPI
292static bool acpi_ppc;
293#endif
13ad7701 294
c5a2ee7d 295static struct global_params global;
93f0822d 296
0c30b65b 297static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 298static DEFINE_MUTEX(intel_pstate_limits_lock);
299
9522a2ff 300#ifdef CONFIG_ACPI
2b3ec765
SP		 301
302static bool intel_pstate_get_ppc_enable_status(void)
303{
304 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
305 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
306 return true;
307
308 return acpi_ppc;
309}
310
17669006
RW		 311#ifdef CONFIG_ACPI_CPPC_LIB
312
313/* The work item is needed to avoid CPU hotplug locking issues */
314static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
315{
316 sched_set_itmt_support();
317}
318
319static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
320
321static void intel_pstate_set_itmt_prio(int cpu)
322{
323 struct cppc_perf_caps cppc_perf;
324 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
325 int ret;
326
327 ret = cppc_get_perf_caps(cpu, &cppc_perf);
328 if (ret)
329 return;
330
331 /*
332 * The priorities can be set regardless of whether or not
333 * sched_set_itmt_support(true) has been called and it is valid to
334 * update them at any time after it has been called.
335 */
336 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
337
338 if (max_highest_perf <= min_highest_perf) {
339 if (cppc_perf.highest_perf > max_highest_perf)
340 max_highest_perf = cppc_perf.highest_perf;
341
342 if (cppc_perf.highest_perf < min_highest_perf)
343 min_highest_perf = cppc_perf.highest_perf;
344
345 if (max_highest_perf > min_highest_perf) {
346 /*
347 * This code can be run during CPU online under the
348 * CPU hotplug locks, so sched_set_itmt_support()
349 * cannot be called from here. Queue up a work item
350 * to invoke it.
351 */
352 schedule_work(&sched_itmt_work);
353 }
354 }
355}
356#else
357static void intel_pstate_set_itmt_prio(int cpu)
358{
359}
360#endif
361
9522a2ff
SP		 362static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
363{
364 struct cpudata *cpu;
9522a2ff
SP		 365 int ret;
366 int i;
367
17669006
RW		 368 if (hwp_active) {
369 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 370 return;
17669006 371 }
e59a8f7f 372
2b3ec765 373 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 374 return;
375
376 cpu = all_cpu_data[policy->cpu];
377
378 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
379 policy->cpu);
380 if (ret)
381 return;
382
383 /*
384 * Check if the control value in _PSS is for PERF_CTL MSR, which should
385 * guarantee that the states returned by it map to the states in our
386 * list directly.
387 */
388 if (cpu->acpi_perf_data.control_register.space_id !=
389 ACPI_ADR_SPACE_FIXED_HARDWARE)
390 goto err;
391
392 /*
393 * If there is only one entry _PSS, simply ignore _PSS and continue as
394 * usual without taking _PSS into account
395 */
396 if (cpu->acpi_perf_data.state_count < 2)
397 goto err;
398
399 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
400 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
401 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
402 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
403 (u32) cpu->acpi_perf_data.states[i].core_frequency,
404 (u32) cpu->acpi_perf_data.states[i].power,
405 (u32) cpu->acpi_perf_data.states[i].control);
406 }
407
408 /*
409 * The _PSS table doesn't contain whole turbo frequency range.
410 * This just contains +1 MHZ above the max non turbo frequency,
411 * with control value corresponding to max turbo ratio. But
412 * when cpufreq set policy is called, it will call with this
413 * max frequency, which will cause a reduced performance as
414 * this driver uses real max turbo frequency as the max
415 * frequency. So correct this frequency in _PSS table to
b00345d1 416 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 417 * Also need to convert to MHz as _PSS freq is in MHz.
418 */
7de32556 419 if (!global.turbo_disabled)
9522a2ff
SP		 420 cpu->acpi_perf_data.states[0].core_frequency =
421 policy->cpuinfo.max_freq / 1000;
422 cpu->valid_pss_table = true;
6cacd115 423 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 424
425 return;
426
427 err:
428 cpu->valid_pss_table = false;
429 acpi_processor_unregister_performance(policy->cpu);
430}
431
432static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
433{
434 struct cpudata *cpu;
435
436 cpu = all_cpu_data[policy->cpu];
437 if (!cpu->valid_pss_table)
438 return;
439
440 acpi_processor_unregister_performance(policy->cpu);
441}
9522a2ff 442#else
7a3ba767 443static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 444{
445}
446
7a3ba767 447static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 448{
449}
450#endif
451
4521e1a0
GM		 452static inline void update_turbo_state(void)
453{
454 u64 misc_en;
455 struct cpudata *cpu;
456
457 cpu = all_cpu_data[0];
458 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
7de32556 459 global.turbo_disabled =
4521e1a0
GM		 460 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
461 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
462}
463
c5a2ee7d
RW		 464static int min_perf_pct_min(void)
465{
466 struct cpudata *cpu = all_cpu_data[0];
57caf4ec 467 int turbo_pstate = cpu->pstate.turbo_pstate;
c5a2ee7d 468
57caf4ec 469 return turbo_pstate ?
d4436c0d 470 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
c5a2ee7d
RW		 471}
472
8442885f
SP		 473static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
474{
475 u64 epb;
476 int ret;
477
478 if (!static_cpu_has(X86_FEATURE_EPB))
479 return -ENXIO;
480
481 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
482 if (ret)
483 return (s16)ret;
484
485 return (s16)(epb & 0x0f);
486}
487
488static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
489{
490 s16 epp;
491
984edbdc
SP		 492 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
493 /*
494 * When hwp_req_data is 0, means that caller didn't read
495 * MSR_HWP_REQUEST, so need to read and get EPP.
496 */
497 if (!hwp_req_data) {
498 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
499 &hwp_req_data);
500 if (epp)
501 return epp;
502 }
8442885f 503 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 504 } else {
8442885f
SP		 505 /* When there is no EPP present, HWP uses EPB settings */
506 epp = intel_pstate_get_epb(cpu_data);
984edbdc 507 }
8442885f
SP		 508
509 return epp;
510}
511
984edbdc 512static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 513{
514 u64 epb;
984edbdc 515 int ret;
8442885f
SP		 516
517 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 518 return -ENXIO;
8442885f 519
984edbdc
SP		 520 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
521 if (ret)
522 return ret;
8442885f
SP		 523
524 epb = (epb & ~0x0f) | pref;
525 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 526
527 return 0;
8442885f
SP		 528}
529
984edbdc
SP		 530/*
531 * EPP/EPB display strings corresponding to EPP index in the
532 * energy_perf_strings[]
533 * index String
534 *-------------------------------------
535 * 0 default
536 * 1 performance
537 * 2 balance_performance
538 * 3 balance_power
539 * 4 power
540 */
541static const char * const energy_perf_strings[] = {
542 "default",
543 "performance",
544 "balance_performance",
545 "balance_power",
546 "power",
547 NULL
548};
3cedbc5a
LB		 549static const unsigned int epp_values[] = {
550 HWP_EPP_PERFORMANCE,
551 HWP_EPP_BALANCE_PERFORMANCE,
552 HWP_EPP_BALANCE_POWERSAVE,
553 HWP_EPP_POWERSAVE
554};
984edbdc
SP		 555
556static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
557{
558 s16 epp;
559 int index = -EINVAL;
560
561 epp = intel_pstate_get_epp(cpu_data, 0);
562 if (epp < 0)
563 return epp;
564
565 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
3cedbc5a
LB		 566 if (epp == HWP_EPP_PERFORMANCE)
567 return 1;
568 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
569 return 2;
570 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
571 return 3;
572 else
573 return 4;
984edbdc
SP		 574 } else if (static_cpu_has(X86_FEATURE_EPB)) {
575 /*
576 * Range:
577 * 0x00-0x03 : Performance
578 * 0x04-0x07 : Balance performance
579 * 0x08-0x0B : Balance power
580 * 0x0C-0x0F : Power
581 * The EPB is a 4 bit value, but our ranges restrict the
582 * value which can be set. Here only using top two bits
583 * effectively.
584 */
585 index = (epp >> 2) + 1;
586 }
587
588 return index;
589}
590
591static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
592 int pref_index)
593{
594 int epp = -EINVAL;
595 int ret;
596
597 if (!pref_index)
598 epp = cpu_data->epp_default;
599
600 mutex_lock(&intel_pstate_limits_lock);
601
602 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
603 u64 value;
604
605 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
606 if (ret)
607 goto return_pref;
608
609 value &= ~GENMASK_ULL(31, 24);
610
984edbdc 611 if (epp == -EINVAL)
3cedbc5a 612 epp = epp_values[pref_index - 1];
984edbdc
SP		 613
614 value |= (u64)epp << 24;
615 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
616 } else {
617 if (epp == -EINVAL)
618 epp = (pref_index - 1) << 2;
619 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
620 }
621return_pref:
622 mutex_unlock(&intel_pstate_limits_lock);
623
624 return ret;
625}
626
627static ssize_t show_energy_performance_available_preferences(
628 struct cpufreq_policy *policy, char *buf)
629{
630 int i = 0;
631 int ret = 0;
632
633 while (energy_perf_strings[i] != NULL)
634 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
635
636 ret += sprintf(&buf[ret], "\n");
637
638 return ret;
639}
640
641cpufreq_freq_attr_ro(energy_performance_available_preferences);
642
643static ssize_t store_energy_performance_preference(
644 struct cpufreq_policy *policy, const char *buf, size_t count)
645{
646 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
647 char str_preference[21];
648 int ret, i = 0;
649
650 ret = sscanf(buf, "%20s", str_preference);
651 if (ret != 1)
652 return -EINVAL;
653
654 while (energy_perf_strings[i] != NULL) {
655 if (!strcmp(str_preference, energy_perf_strings[i])) {
656 intel_pstate_set_energy_pref_index(cpu_data, i);
657 return count;
658 }
659 ++i;
660 }
661
662 return -EINVAL;
663}
664
665static ssize_t show_energy_performance_preference(
666 struct cpufreq_policy *policy, char *buf)
667{
668 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
669 int preference;
670
671 preference = intel_pstate_get_energy_pref_index(cpu_data);
672 if (preference < 0)
673 return preference;
674
675 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
676}
677
678cpufreq_freq_attr_rw(energy_performance_preference);
679
680static struct freq_attr *hwp_cpufreq_attrs[] = {
681 &energy_performance_preference,
682 &energy_performance_available_preferences,
683 NULL,
684};
685
1a4fe38a
SP		 686static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
687 int *current_max)
2f86dc4c 688{
1a4fe38a 689 u64 cap;
74da56ce 690
2bfc4cbb 691 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
2bfc4cbb 692 if (global.no_turbo)
1a4fe38a 693 *current_max = HWP_GUARANTEED_PERF(cap);
2bfc4cbb 694 else
1a4fe38a
SP		 695 *current_max = HWP_HIGHEST_PERF(cap);
696
697 *phy_max = HWP_HIGHEST_PERF(cap);
698}
699
700static void intel_pstate_hwp_set(unsigned int cpu)
701{
702 struct cpudata *cpu_data = all_cpu_data[cpu];
703 int max, min;
704 u64 value;
705 s16 epp;
706
707 max = cpu_data->max_perf_ratio;
708 min = cpu_data->min_perf_ratio;
eae48f04 709
2bfc4cbb
RW		 710 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
711 min = max;
3f8ed54a 712
2bfc4cbb 713 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
2f86dc4c 714
2bfc4cbb
RW		 715 value &= ~HWP_MIN_PERF(~0L);
716 value |= HWP_MIN_PERF(min);
8442885f 717
2bfc4cbb
RW		 718 value &= ~HWP_MAX_PERF(~0L);
719 value |= HWP_MAX_PERF(max);
8442885f 720
2bfc4cbb
RW		 721 if (cpu_data->epp_policy == cpu_data->policy)
722 goto skip_epp;
8442885f 723
2bfc4cbb 724 cpu_data->epp_policy = cpu_data->policy;
984edbdc 725
2bfc4cbb
RW		 726 if (cpu_data->epp_saved >= 0) {
727 epp = cpu_data->epp_saved;
728 cpu_data->epp_saved = -EINVAL;
729 goto update_epp;
730 }
8442885f 731
2bfc4cbb
RW		 732 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
733 epp = intel_pstate_get_epp(cpu_data, value);
734 cpu_data->epp_powersave = epp;
735 /* If EPP read was failed, then don't try to write */
736 if (epp < 0)
737 goto skip_epp;
8442885f 738
2bfc4cbb
RW		 739 epp = 0;
740 } else {
741 /* skip setting EPP, when saved value is invalid */
742 if (cpu_data->epp_powersave < 0)
743 goto skip_epp;
8442885f 744
2bfc4cbb
RW		 745 /*
746 * No need to restore EPP when it is not zero. This
747 * means:
748 * - Policy is not changed
749 * - user has manually changed
750 * - Error reading EPB
751 */
752 epp = intel_pstate_get_epp(cpu_data, value);
753 if (epp)
754 goto skip_epp;
8442885f 755
2bfc4cbb
RW		 756 epp = cpu_data->epp_powersave;
757 }
984edbdc 758update_epp:
2bfc4cbb
RW		 759 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
760 value &= ~GENMASK_ULL(31, 24);
761 value |= (u64)epp << 24;
762 } else {
763 intel_pstate_set_epb(cpu, epp);
2f86dc4c 764 }
2bfc4cbb
RW		 765skip_epp:
766 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
41cfd64c 767}
2f86dc4c 768
984edbdc
SP		 769static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
770{
771 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
772
773 if (!hwp_active)
774 return 0;
775
776 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
777
778 return 0;
779}
780
70f6bf2a
CY		 781static void intel_pstate_hwp_enable(struct cpudata *cpudata);
782
8442885f
SP		 783static int intel_pstate_resume(struct cpufreq_policy *policy)
784{
785 if (!hwp_active)
786 return 0;
787
aa439248
RW		 788 mutex_lock(&intel_pstate_limits_lock);
789
70f6bf2a
CY		 790 if (policy->cpu == 0)
791 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
792
8442885f 793 all_cpu_data[policy->cpu]->epp_policy = 0;
2bfc4cbb 794 intel_pstate_hwp_set(policy->cpu);
aa439248
RW		 795
796 mutex_unlock(&intel_pstate_limits_lock);
797
5f98ced1 798 return 0;
8442885f
SP		 799}
800
111b8b3f 801static void intel_pstate_update_policies(void)
41cfd64c 802{
111b8b3f
RW		 803 int cpu;
804
805 for_each_possible_cpu(cpu)
806 cpufreq_update_policy(cpu);
2f86dc4c
DB		 807}
808
93f0822d
DB		 809/************************** sysfs begin ************************/
810#define show_one(file_name, object) \
811 static ssize_t show_##file_name \
812 (struct kobject *kobj, struct attribute *attr, char *buf) \
813 { \
7de32556 814 return sprintf(buf, "%u\n", global.object); \
93f0822d
DB		 815 }
816
fb1fe104
RW		 817static ssize_t intel_pstate_show_status(char *buf);
818static int intel_pstate_update_status(const char *buf, size_t size);
819
820static ssize_t show_status(struct kobject *kobj,
821 struct attribute *attr, char *buf)
822{
823 ssize_t ret;
824
825 mutex_lock(&intel_pstate_driver_lock);
826 ret = intel_pstate_show_status(buf);
827 mutex_unlock(&intel_pstate_driver_lock);
828
829 return ret;
830}
831
832static ssize_t store_status(struct kobject *a, struct attribute *b,
833 const char *buf, size_t count)
834{
835 char *p = memchr(buf, '\n', count);
836 int ret;
837
838 mutex_lock(&intel_pstate_driver_lock);
839 ret = intel_pstate_update_status(buf, p ? p - buf : count);
840 mutex_unlock(&intel_pstate_driver_lock);
841
842 return ret < 0 ? ret : count;
843}
844
d01b1f48
KCA		 845static ssize_t show_turbo_pct(struct kobject *kobj,
846 struct attribute *attr, char *buf)
847{
848 struct cpudata *cpu;
849 int total, no_turbo, turbo_pct;
850 uint32_t turbo_fp;
851
0c30b65b
RW		 852 mutex_lock(&intel_pstate_driver_lock);
853
ee8df89a 854 if (!intel_pstate_driver) {
0c30b65b
RW		 855 mutex_unlock(&intel_pstate_driver_lock);
856 return -EAGAIN;
857 }
858
d01b1f48
KCA		 859 cpu = all_cpu_data[0];
860
861 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
862 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 863 turbo_fp = div_fp(no_turbo, total);
d01b1f48 864 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 865
866 mutex_unlock(&intel_pstate_driver_lock);
867
d01b1f48
KCA		 868 return sprintf(buf, "%u\n", turbo_pct);
869}
870
0522424e
KCA		 871static ssize_t show_num_pstates(struct kobject *kobj,
872 struct attribute *attr, char *buf)
873{
874 struct cpudata *cpu;
875 int total;
876
0c30b65b
RW		 877 mutex_lock(&intel_pstate_driver_lock);
878
ee8df89a 879 if (!intel_pstate_driver) {
0c30b65b
RW		 880 mutex_unlock(&intel_pstate_driver_lock);
881 return -EAGAIN;
882 }
883
0522424e
KCA		 884 cpu = all_cpu_data[0];
885 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 886
887 mutex_unlock(&intel_pstate_driver_lock);
888
0522424e
KCA		 889 return sprintf(buf, "%u\n", total);
890}
891
4521e1a0
GM		 892static ssize_t show_no_turbo(struct kobject *kobj,
893 struct attribute *attr, char *buf)
894{
895 ssize_t ret;
896
0c30b65b
RW		 897 mutex_lock(&intel_pstate_driver_lock);
898
ee8df89a 899 if (!intel_pstate_driver) {
0c30b65b
RW		 900 mutex_unlock(&intel_pstate_driver_lock);
901 return -EAGAIN;
902 }
903
4521e1a0 904 update_turbo_state();
7de32556
RW		 905 if (global.turbo_disabled)
906 ret = sprintf(buf, "%u\n", global.turbo_disabled);
4521e1a0 907 else
7de32556 908 ret = sprintf(buf, "%u\n", global.no_turbo);
4521e1a0 909
0c30b65b
RW		 910 mutex_unlock(&intel_pstate_driver_lock);
911
4521e1a0
GM		 912 return ret;
913}
914
93f0822d 915static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 916 const char *buf, size_t count)
93f0822d
DB		 917{
918 unsigned int input;
919 int ret;
845c1cbe 920
93f0822d
DB		 921 ret = sscanf(buf, "%u", &input);
922 if (ret != 1)
923 return -EINVAL;
4521e1a0 924
0c30b65b
RW		 925 mutex_lock(&intel_pstate_driver_lock);
926
ee8df89a 927 if (!intel_pstate_driver) {
0c30b65b
RW		 928 mutex_unlock(&intel_pstate_driver_lock);
929 return -EAGAIN;
930 }
931
a410c03d
SP		 932 mutex_lock(&intel_pstate_limits_lock);
933
4521e1a0 934 update_turbo_state();
7de32556 935 if (global.turbo_disabled) {
4836df17 936 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 937 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 938 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 939 return -EPERM;
dd5fbf70 940 }
2f86dc4c 941
7de32556 942 global.no_turbo = clamp_t(int, input, 0, 1);
111b8b3f 943
c5a2ee7d
RW		 944 if (global.no_turbo) {
945 struct cpudata *cpu = all_cpu_data[0];
946 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
947
948 /* Squash the global minimum into the permitted range. */
949 if (global.min_perf_pct > pct)
950 global.min_perf_pct = pct;
951 }
952
cd59b4be
RW		 953 mutex_unlock(&intel_pstate_limits_lock);
954
7de32556
RW		 955 intel_pstate_update_policies();
956
0c30b65b
RW		 957 mutex_unlock(&intel_pstate_driver_lock);
958
93f0822d
DB		 959 return count;
960}
961
962static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 963 const char *buf, size_t count)
93f0822d
DB		 964{
965 unsigned int input;
966 int ret;
845c1cbe 967
93f0822d
DB		 968 ret = sscanf(buf, "%u", &input);
969 if (ret != 1)
970 return -EINVAL;
971
0c30b65b
RW		 972 mutex_lock(&intel_pstate_driver_lock);
973
ee8df89a 974 if (!intel_pstate_driver) {
0c30b65b
RW		 975 mutex_unlock(&intel_pstate_driver_lock);
976 return -EAGAIN;
977 }
978
a410c03d
SP		 979 mutex_lock(&intel_pstate_limits_lock);
980
c5a2ee7d 981 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
111b8b3f 982
cd59b4be
RW		 983 mutex_unlock(&intel_pstate_limits_lock);
984
7de32556
RW		 985 intel_pstate_update_policies();
986
0c30b65b
RW		 987 mutex_unlock(&intel_pstate_driver_lock);
988
93f0822d
DB		 989 return count;
990}
991
992static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 993 const char *buf, size_t count)
93f0822d
DB		 994{
995 unsigned int input;
996 int ret;
845c1cbe 997
93f0822d
DB		 998 ret = sscanf(buf, "%u", &input);
999 if (ret != 1)
1000 return -EINVAL;
a0475992 1001
0c30b65b
RW		 1002 mutex_lock(&intel_pstate_driver_lock);
1003
ee8df89a 1004 if (!intel_pstate_driver) {
0c30b65b
RW		 1005 mutex_unlock(&intel_pstate_driver_lock);
1006 return -EAGAIN;
1007 }
1008
a410c03d
SP		 1009 mutex_lock(&intel_pstate_limits_lock);
1010
c5a2ee7d
RW		 1011 global.min_perf_pct = clamp_t(int, input,
1012 min_perf_pct_min(), global.max_perf_pct);
111b8b3f 1013
cd59b4be
RW		 1014 mutex_unlock(&intel_pstate_limits_lock);
1015
7de32556
RW		 1016 intel_pstate_update_policies();
1017
0c30b65b
RW		 1018 mutex_unlock(&intel_pstate_driver_lock);
1019
93f0822d
DB		 1020 return count;
1021}
1022
93f0822d
DB		 1023show_one(max_perf_pct, max_perf_pct);
1024show_one(min_perf_pct, min_perf_pct);
1025
fb1fe104 1026define_one_global_rw(status);
93f0822d
DB		 1027define_one_global_rw(no_turbo);
1028define_one_global_rw(max_perf_pct);
1029define_one_global_rw(min_perf_pct);
d01b1f48 1030define_one_global_ro(turbo_pct);
0522424e 1031define_one_global_ro(num_pstates);
93f0822d
DB		 1032
1033static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1034 &status.attr,
93f0822d 1035 &no_turbo.attr,
d01b1f48 1036 &turbo_pct.attr,
0522424e 1037 &num_pstates.attr,
93f0822d
DB		 1038 NULL
1039};
1040
106c9c77 1041static const struct attribute_group intel_pstate_attr_group = {
93f0822d
DB		 1042 .attrs = intel_pstate_attributes,
1043};
93f0822d 1044
317dd50e 1045static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1046{
317dd50e 1047 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1048 int rc;
1049
1050 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1051 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1052 if (WARN_ON(!intel_pstate_kobject))
1053 return;
1054
2d8d1f18 1055 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1056 if (WARN_ON(rc))
1057 return;
1058
1059 /*
1060 * If per cpu limits are enforced there are no global limits, so
1061 * return without creating max/min_perf_pct attributes
1062 */
1063 if (per_cpu_limits)
1064 return;
1065
1066 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1067 WARN_ON(rc);
1068
1069 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1070 WARN_ON(rc);
1071
93f0822d 1072}
93f0822d 1073/************************** sysfs end ************************/
2f86dc4c 1074
ba88d433 1075static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1076{
f05c9665 1077 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1078 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1079 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1080
ba88d433 1081 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1082 cpudata->epp_policy = 0;
984edbdc
SP		 1083 if (cpudata->epp_default == -EINVAL)
1084 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1085}
1086
6e978b22
SP		 1087#define MSR_IA32_POWER_CTL_BIT_EE 19
1088
1089/* Disable energy efficiency optimization */
1090static void intel_pstate_disable_ee(int cpu)
1091{
1092 u64 power_ctl;
1093 int ret;
1094
1095 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1096 if (ret)
1097 return;
1098
1099 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1100 pr_info("Disabling energy efficiency optimization\n");
1101 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1102 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1103 }
1104}
1105
938d21a2 1106static int atom_get_min_pstate(void)
19e77c28
DB		 1107{
1108 u64 value;
845c1cbe 1109
92134bdb 1110 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1111 return (value >> 8) & 0x7F;
19e77c28
DB		 1112}
1113
938d21a2 1114static int atom_get_max_pstate(void)
19e77c28
DB		 1115{
1116 u64 value;
845c1cbe 1117
92134bdb 1118 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1119 return (value >> 16) & 0x7F;
19e77c28 1120}
93f0822d 1121
938d21a2 1122static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1123{
1124 u64 value;
845c1cbe 1125
92134bdb 1126 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1127 return value & 0x7F;
61d8d2ab
DB		 1128}
1129
fdfdb2b1 1130static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1131{
1132 u64 val;
1133 int32_t vid_fp;
1134 u32 vid;
1135
144c8e17 1136 val = (u64)pstate << 8;
7de32556 1137 if (global.no_turbo && !global.turbo_disabled)
007bea09
DB		 1138 val |= (u64)1 << 32;
1139
1140 vid_fp = cpudata->vid.min + mul_fp(
1141 int_tofp(pstate - cpudata->pstate.min_pstate),
1142 cpudata->vid.ratio);
1143
1144 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1145 vid = ceiling_fp(vid_fp);
007bea09 1146
21855ff5
DB		 1147 if (pstate > cpudata->pstate.max_pstate)
1148 vid = cpudata->vid.turbo;
1149
fdfdb2b1 1150 return val | vid;
007bea09
DB		 1151}
1152
1421df63 1153static int silvermont_get_scaling(void)
b27580b0
DB		 1154{
1155 u64 value;
1156 int i;
1421df63
PL		 1157 /* Defined in Table 35-6 from SDM (Sept 2015) */
1158 static int silvermont_freq_table[] = {
1159 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1160
1161 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1162 i = value & 0x7;
1163 WARN_ON(i > 4);
b27580b0 1164
1421df63
PL		 1165 return silvermont_freq_table[i];
1166}
b27580b0 1167
1421df63
PL		 1168static int airmont_get_scaling(void)
1169{
1170 u64 value;
1171 int i;
1172 /* Defined in Table 35-10 from SDM (Sept 2015) */
1173 static int airmont_freq_table[] = {
1174 83300, 100000, 133300, 116700, 80000,
1175 93300, 90000, 88900, 87500};
1176
1177 rdmsrl(MSR_FSB_FREQ, value);
1178 i = value & 0xF;
1179 WARN_ON(i > 8);
1180
1181 return airmont_freq_table[i];
b27580b0
DB		 1182}
1183
938d21a2 1184static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1185{
1186 u64 value;
1187
92134bdb 1188 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1189 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1190 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1191 cpudata->vid.ratio = div_fp(
1192 cpudata->vid.max - cpudata->vid.min,
1193 int_tofp(cpudata->pstate.max_pstate -
1194 cpudata->pstate.min_pstate));
21855ff5 1195
92134bdb 1196 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1197 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1198}
1199
016c8150 1200static int core_get_min_pstate(void)
93f0822d
DB		 1201{
1202 u64 value;
845c1cbe 1203
05e99c8c 1204 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1205 return (value >> 40) & 0xFF;
1206}
1207
3bcc6fa9 1208static int core_get_max_pstate_physical(void)
93f0822d
DB		 1209{
1210 u64 value;
845c1cbe 1211
05e99c8c 1212 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1213 return (value >> 8) & 0xFF;
1214}
1215
8fc7554a
SP		 1216static int core_get_tdp_ratio(u64 plat_info)
1217{
1218 /* Check how many TDP levels present */
1219 if (plat_info & 0x600000000) {
1220 u64 tdp_ctrl;
1221 u64 tdp_ratio;
1222 int tdp_msr;
1223 int err;
1224
1225 /* Get the TDP level (0, 1, 2) to get ratios */
1226 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1227 if (err)
1228 return err;
1229
1230 /* TDP MSR are continuous starting at 0x648 */
1231 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1232 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1233 if (err)
1234 return err;
1235
1236 /* For level 1 and 2, bits[23:16] contain the ratio */
1237 if (tdp_ctrl & 0x03)
1238 tdp_ratio >>= 16;
1239
1240 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1241 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1242
1243 return (int)tdp_ratio;
1244 }
1245
1246 return -ENXIO;
1247}
1248
016c8150 1249static int core_get_max_pstate(void)
93f0822d 1250{
6a35fc2d
SP		 1251 u64 tar;
1252 u64 plat_info;
1253 int max_pstate;
8fc7554a 1254 int tdp_ratio;
6a35fc2d
SP		 1255 int err;
1256
1257 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1258 max_pstate = (plat_info >> 8) & 0xFF;
1259
8fc7554a
SP		 1260 tdp_ratio = core_get_tdp_ratio(plat_info);
1261 if (tdp_ratio <= 0)
1262 return max_pstate;
1263
1264 if (hwp_active) {
1265 /* Turbo activation ratio is not used on HWP platforms */
1266 return tdp_ratio;
1267 }
1268
6a35fc2d
SP		 1269 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1270 if (!err) {
8fc7554a
SP		 1271 int tar_levels;
1272
6a35fc2d 1273 /* Do some sanity checking for safety */
8fc7554a
SP		 1274 tar_levels = tar & 0xff;
1275 if (tdp_ratio - 1 == tar_levels) {
1276 max_pstate = tar_levels;
1277 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1278 }
1279 }
845c1cbe 1280
6a35fc2d 1281 return max_pstate;
93f0822d
DB		 1282}
1283
016c8150 1284static int core_get_turbo_pstate(void)
93f0822d
DB		 1285{
1286 u64 value;
1287 int nont, ret;
845c1cbe 1288
100cf6f2 1289 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1290 nont = core_get_max_pstate();
285cb990 1291 ret = (value) & 255;
93f0822d
DB		 1292 if (ret <= nont)
1293 ret = nont;
1294 return ret;
1295}
1296
b27580b0
DB		 1297static inline int core_get_scaling(void)
1298{
1299 return 100000;
1300}
1301
fdfdb2b1 1302static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1303{
1304 u64 val;
1305
144c8e17 1306 val = (u64)pstate << 8;
7de32556 1307 if (global.no_turbo && !global.turbo_disabled)
016c8150
DB		 1308 val |= (u64)1 << 32;
1309
fdfdb2b1 1310 return val;
016c8150
DB		 1311}
1312
6e34e1f2
SP		 1313static int knl_get_aperf_mperf_shift(void)
1314{
1315 return 10;
1316}
1317
b34ef932
DC		 1318static int knl_get_turbo_pstate(void)
1319{
1320 u64 value;
1321 int nont, ret;
1322
100cf6f2 1323 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1324 nont = core_get_max_pstate();
1325 ret = (((value) >> 8) & 0xFF);
1326 if (ret <= nont)
1327 ret = nont;
1328 return ret;
1329}
1330
b02aabe8 1331static int intel_pstate_get_base_pstate(struct cpudata *cpu)
93f0822d 1332{
b02aabe8
RW		 1333 return global.no_turbo || global.turbo_disabled ?
1334 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
93f0822d
DB		 1335}
1336
a6c6ead1 1337static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1338{
bc95a454
RW		 1339 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1340 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1341 /*
1342 * Generally, there is no guarantee that this code will always run on
1343 * the CPU being updated, so force the register update to run on the
1344 * right CPU.
1345 */
1346 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1347 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1348}
1349
a6c6ead1
RW		 1350static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1351{
1352 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1353}
1354
1355static void intel_pstate_max_within_limits(struct cpudata *cpu)
1356{
b02aabe8 1357 int pstate;
a6c6ead1
RW		 1358
1359 update_turbo_state();
b02aabe8 1360 pstate = intel_pstate_get_base_pstate(cpu);
1a4fe38a 1361 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
b02aabe8 1362 intel_pstate_set_pstate(cpu, pstate);
a6c6ead1
RW		 1363}
1364
93f0822d
DB		 1365static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1366{
016c8150
DB		 1367 cpu->pstate.min_pstate = pstate_funcs.get_min();
1368 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1369 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1370 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1371 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0
RW		 1372 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1373 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d 1374
6e34e1f2
SP		 1375 if (pstate_funcs.get_aperf_mperf_shift)
1376 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1377
007bea09
DB		 1378 if (pstate_funcs.get_vid)
1379 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1380
1381 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1382}
1383
a1c9787d 1384static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1385{
6b17ddb2 1386 struct sample *sample = &cpu->sample;
e66c1768 1387
a1c9787d 1388 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1389}
1390
4fec7ad5 1391static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1392{
93f0822d 1393 u64 aperf, mperf;
4ab60c3f 1394 unsigned long flags;
4055fad3 1395 u64 tsc;
93f0822d 1396
4ab60c3f 1397 local_irq_save(flags);
93f0822d
DB		 1398 rdmsrl(MSR_IA32_APERF, aperf);
1399 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1400 tsc = rdtsc();
4fec7ad5 1401 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1402 local_irq_restore(flags);
4fec7ad5 1403 return false;
8e601a9f 1404 }
4ab60c3f 1405 local_irq_restore(flags);
b69880f9 1406
c4ee841f 1407 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1408 cpu->sample.time = time;
d37e2b76
DB		 1409 cpu->sample.aperf = aperf;
1410 cpu->sample.mperf = mperf;
4055fad3 1411 cpu->sample.tsc = tsc;
d37e2b76
DB		 1412 cpu->sample.aperf -= cpu->prev_aperf;
1413 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1414 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1415
93f0822d
DB		 1416 cpu->prev_aperf = aperf;
1417 cpu->prev_mperf = mperf;
4055fad3 1418 cpu->prev_tsc = tsc;
febce40f
RW		 1419 /*
1420 * First time this function is invoked in a given cycle, all of the
1421 * previous sample data fields are equal to zero or stale and they must
1422 * be populated with meaningful numbers for things to work, so assume
1423 * that sample.time will always be reset before setting the utilization
1424 * update hook and make the caller skip the sample then.
1425 */
eabd22c6
RW		 1426 if (cpu->last_sample_time) {
1427 intel_pstate_calc_avg_perf(cpu);
1428 return true;
1429 }
1430 return false;
93f0822d
DB		 1431}
1432
8fa520af
PL		 1433static inline int32_t get_avg_frequency(struct cpudata *cpu)
1434{
c587c79f 1435 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
8fa520af
PL		 1436}
1437
bdcaa23f
PL		 1438static inline int32_t get_avg_pstate(struct cpudata *cpu)
1439{
8edb0a6e
RW		 1440 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1441 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1442}
1443
d77d4888 1444static inline int32_t get_target_pstate(struct cpudata *cpu)
e70eed2b
PL		 1445{
1446 struct sample *sample = &cpu->sample;
09c448d3 1447 int32_t busy_frac, boost;
0843e83c 1448 int target, avg_pstate;
e70eed2b 1449
6e34e1f2
SP		 1450 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1451 sample->tsc);
63d1d656 1452
09c448d3
RW		 1453 boost = cpu->iowait_boost;
1454 cpu->iowait_boost >>= 1;
63d1d656 1455
09c448d3
RW		 1456 if (busy_frac < boost)
1457 busy_frac = boost;
63d1d656 1458
09c448d3 1459 sample->busy_scaled = busy_frac * 100;
0843e83c 1460
7de32556 1461 target = global.no_turbo || global.turbo_disabled ?
0843e83c
RW		 1462 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1463 target += target >> 2;
1464 target = mul_fp(target, busy_frac);
1465 if (target < cpu->pstate.min_pstate)
1466 target = cpu->pstate.min_pstate;
1467
1468 /*
1469 * If the average P-state during the previous cycle was higher than the
1470 * current target, add 50% of the difference to the target to reduce
1471 * possible performance oscillations and offset possible performance
1472 * loss related to moving the workload from one CPU to another within
1473 * a package/module.
1474 */
1475 avg_pstate = get_avg_pstate(cpu);
1476 if (avg_pstate > target)
1477 target += (avg_pstate - target) >> 1;
1478
1479 return target;
e70eed2b
PL		 1480}
1481
001c76f0 1482static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1 1483{
b02aabe8
RW		 1484 int max_pstate = intel_pstate_get_base_pstate(cpu);
1485 int min_pstate;
fdfdb2b1 1486
1a4fe38a
SP		 1487 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1488 max_pstate = max(min_pstate, cpu->max_perf_ratio);
b02aabe8 1489 return clamp_t(int, pstate, min_pstate, max_pstate);
001c76f0
RW		 1490}
1491
1492static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1493{
fdfdb2b1
RW		 1494 if (pstate == cpu->pstate.current_pstate)
1495 return;
1496
bc95a454 1497 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1498 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1499}
1500
a891283e 1501static void intel_pstate_adjust_pstate(struct cpudata *cpu)
93f0822d 1502{
67dd9bf4 1503 int from = cpu->pstate.current_pstate;
4055fad3 1504 struct sample *sample;
a891283e 1505 int target_pstate;
4055fad3 1506
001c76f0
RW		 1507 update_turbo_state();
1508
d77d4888 1509 target_pstate = get_target_pstate(cpu);
64078299
RW		 1510 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1511 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1 1512 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1513
1514 sample = &cpu->sample;
a1c9787d 1515 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1516 fp_toint(sample->busy_scaled),
4055fad3
DS		 1517 from,
1518 cpu->pstate.current_pstate,
1519 sample->mperf,
1520 sample->aperf,
1521 sample->tsc,
3ba7bcaa
SP		 1522 get_avg_frequency(cpu),
1523 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1524}
1525
a4675fbc 1526static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1527 unsigned int flags)
93f0822d 1528{
a4675fbc 1529 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1530 u64 delta_ns;
1531
674e7541
VK		 1532 /* Don't allow remote callbacks */
1533 if (smp_processor_id() != cpu->cpu)
1534 return;
1535
eabd22c6
RW		 1536 if (flags & SCHED_CPUFREQ_IOWAIT) {
1537 cpu->iowait_boost = int_tofp(1);
7bde2d50
SP		 1538 cpu->last_update = time;
1539 /*
1540 * The last time the busy was 100% so P-state was max anyway
1541 * so avoid overhead of computation.
1542 */
1543 if (fp_toint(cpu->sample.busy_scaled) == 100)
1544 return;
1545
1546 goto set_pstate;
eabd22c6
RW		 1547 } else if (cpu->iowait_boost) {
1548 /* Clear iowait_boost if the CPU may have been idle. */
1549 delta_ns = time - cpu->last_update;
1550 if (delta_ns > TICK_NSEC)
1551 cpu->iowait_boost = 0;
09c448d3 1552 }
eabd22c6 1553 cpu->last_update = time;
09c448d3 1554 delta_ns = time - cpu->sample.time;
d77d4888 1555 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
eabd22c6 1556 return;
4fec7ad5 1557
7bde2d50 1558set_pstate:
a891283e
RW		 1559 if (intel_pstate_sample(cpu, time))
1560 intel_pstate_adjust_pstate(cpu);
67dd9bf4 1561}
eabd22c6 1562
2f49afc2
RW		 1563static struct pstate_funcs core_funcs = {
1564 .get_max = core_get_max_pstate,
1565 .get_max_physical = core_get_max_pstate_physical,
1566 .get_min = core_get_min_pstate,
1567 .get_turbo = core_get_turbo_pstate,
1568 .get_scaling = core_get_scaling,
1569 .get_val = core_get_val,
de4a76cb
RW		 1570};
1571
2f49afc2
RW		 1572static const struct pstate_funcs silvermont_funcs = {
1573 .get_max = atom_get_max_pstate,
1574 .get_max_physical = atom_get_max_pstate,
1575 .get_min = atom_get_min_pstate,
1576 .get_turbo = atom_get_turbo_pstate,
1577 .get_val = atom_get_val,
1578 .get_scaling = silvermont_get_scaling,
1579 .get_vid = atom_get_vid,
de4a76cb
RW		 1580};
1581
2f49afc2
RW		 1582static const struct pstate_funcs airmont_funcs = {
1583 .get_max = atom_get_max_pstate,
1584 .get_max_physical = atom_get_max_pstate,
1585 .get_min = atom_get_min_pstate,
1586 .get_turbo = atom_get_turbo_pstate,
1587 .get_val = atom_get_val,
1588 .get_scaling = airmont_get_scaling,
1589 .get_vid = atom_get_vid,
de4a76cb
RW		 1590};
1591
2f49afc2
RW		 1592static const struct pstate_funcs knl_funcs = {
1593 .get_max = core_get_max_pstate,
1594 .get_max_physical = core_get_max_pstate_physical,
1595 .get_min = core_get_min_pstate,
1596 .get_turbo = knl_get_turbo_pstate,
6e34e1f2 1597 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2f49afc2
RW		 1598 .get_scaling = core_get_scaling,
1599 .get_val = core_get_val,
de4a76cb
RW		 1600};
1601
93f0822d 1602#define ICPU(model, policy) \
6cbd7ee1
DB		 1603 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1604 (unsigned long)&policy }
93f0822d
DB		 1605
1606static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2f49afc2
RW		 1607 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1608 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1609 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1610 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1611 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1612 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1613 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1614 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1615 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1616 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1617 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1618 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1619 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1620 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1621 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1622 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1623 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1624 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
dbd49b85
SP		 1625 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1626 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
d8de7a44 1627 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
93f0822d
DB		 1628 {}
1629};
1630MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1631
29327c84 1632static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2f49afc2
RW		 1633 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1634 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1635 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
2f86dc4c
DB		 1636 {}
1637};
1638
6e978b22 1639static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2f49afc2 1640 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
6e978b22
SP		 1641 {}
1642};
1643
93f0822d
DB		 1644static int intel_pstate_init_cpu(unsigned int cpunum)
1645{
93f0822d
DB		 1646 struct cpudata *cpu;
1647
eae48f04
SP		 1648 cpu = all_cpu_data[cpunum];
1649
1650 if (!cpu) {
c5a2ee7d 1651 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
eae48f04
SP		 1652 if (!cpu)
1653 return -ENOMEM;
1654
1655 all_cpu_data[cpunum] = cpu;
eae48f04 1656
984edbdc
SP		 1657 cpu->epp_default = -EINVAL;
1658 cpu->epp_powersave = -EINVAL;
1659 cpu->epp_saved = -EINVAL;
eae48f04 1660 }
93f0822d
DB		 1661
1662 cpu = all_cpu_data[cpunum];
1663
93f0822d 1664 cpu->cpu = cpunum;
ba88d433 1665
a4675fbc 1666 if (hwp_active) {
6e978b22
SP		 1667 const struct x86_cpu_id *id;
1668
1669 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1670 if (id)
1671 intel_pstate_disable_ee(cpunum);
1672
ba88d433 1673 intel_pstate_hwp_enable(cpu);
a4675fbc 1674 }
ba88d433 1675
179e8471 1676 intel_pstate_get_cpu_pstates(cpu);
016c8150 1677
4836df17 1678 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1679
1680 return 0;
1681}
1682
febce40f 1683static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1684{
febce40f
RW		 1685 struct cpudata *cpu = all_cpu_data[cpu_num];
1686
62611cb9
LB		 1687 if (hwp_active)
1688 return;
1689
5ab666e0
RW		 1690 if (cpu->update_util_set)
1691 return;
1692
febce40f
RW		 1693 /* Prevent intel_pstate_update_util() from using stale data. */
1694 cpu->sample.time = 0;
67dd9bf4 1695 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
c4f3f70c 1696 intel_pstate_update_util);
4578ee7e 1697 cpu->update_util_set = true;
bb6ab52f
RW		 1698}
1699
1700static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1701{
4578ee7e
CY		 1702 struct cpudata *cpu_data = all_cpu_data[cpu];
1703
1704 if (!cpu_data->update_util_set)
1705 return;
1706
0bed612b 1707 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1708 cpu_data->update_util_set = false;
bb6ab52f
RW		 1709 synchronize_sched();
1710}
1711
80b120ca
RW		 1712static int intel_pstate_get_max_freq(struct cpudata *cpu)
1713{
1714 return global.turbo_disabled || global.no_turbo ?
1715 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1716}
1717
eae48f04 1718static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
c5a2ee7d 1719 struct cpudata *cpu)
eae48f04 1720{
80b120ca 1721 int max_freq = intel_pstate_get_max_freq(cpu);
e4c204ce 1722 int32_t max_policy_perf, min_policy_perf;
1a4fe38a 1723 int max_state, turbo_max;
a410c03d 1724
1a4fe38a
SP		 1725 /*
1726 * HWP needs some special consideration, because on BDX the
1727 * HWP_REQUEST uses abstract value to represent performance
1728 * rather than pure ratios.
1729 */
1730 if (hwp_active) {
1731 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1732 } else {
1733 max_state = intel_pstate_get_base_pstate(cpu);
1734 turbo_max = cpu->pstate.turbo_pstate;
1735 }
1736
1737 max_policy_perf = max_state * policy->max / max_freq;
5879f877 1738 if (policy->max == policy->min) {
e4c204ce 1739 min_policy_perf = max_policy_perf;
5879f877 1740 } else {
1a4fe38a 1741 min_policy_perf = max_state * policy->min / max_freq;
e4c204ce
RW		 1742 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1743 0, max_policy_perf);
5879f877 1744 }
eae48f04 1745
1a4fe38a
SP		 1746 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1747 policy->cpu, max_state,
1748 min_policy_perf, max_policy_perf);
1749
e4c204ce 1750 /* Normalize user input to [min_perf, max_perf] */
c5a2ee7d 1751 if (per_cpu_limits) {
1a4fe38a
SP		 1752 cpu->min_perf_ratio = min_policy_perf;
1753 cpu->max_perf_ratio = max_policy_perf;
c5a2ee7d
RW		 1754 } else {
1755 int32_t global_min, global_max;
1756
1757 /* Global limits are in percent of the maximum turbo P-state. */
1a4fe38a
SP		 1758 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1759 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
c5a2ee7d 1760 global_min = clamp_t(int32_t, global_min, 0, global_max);
eae48f04 1761
1a4fe38a
SP		 1762 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1763 global_min, global_max);
c5a2ee7d 1764
1a4fe38a
SP		 1765 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1766 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1767 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1768 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
eae48f04 1769
1a4fe38a
SP		 1770 /* Make sure min_perf <= max_perf */
1771 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1772 cpu->max_perf_ratio);
eae48f04 1773
1a4fe38a
SP		 1774 }
1775 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1776 cpu->max_perf_ratio,
1777 cpu->min_perf_ratio);
eae48f04
SP		 1778}
1779
93f0822d
DB		 1780static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1781{
3be9200d
SP		 1782 struct cpudata *cpu;
1783
d3929b83
DB		 1784 if (!policy->cpuinfo.max_freq)
1785 return -ENODEV;
1786
2c2c1af4
SP		 1787 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1788 policy->cpuinfo.max_freq, policy->max);
1789
a6c6ead1 1790 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 1791 cpu->policy = policy->policy;
1792
b59fe540
SP		 1793 mutex_lock(&intel_pstate_limits_lock);
1794
c5a2ee7d 1795 intel_pstate_update_perf_limits(policy, cpu);
a240c4aa 1796
2f1d407a 1797 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 1798 /*
1799 * NOHZ_FULL CPUs need this as the governor callback may not
1800 * be invoked on them.
1801 */
1802 intel_pstate_clear_update_util_hook(policy->cpu);
1803 intel_pstate_max_within_limits(cpu);
82b4e03e
LB		 1804 } else {
1805 intel_pstate_set_update_util_hook(policy->cpu);
a6c6ead1
RW		 1806 }
1807
5f98ced1 1808 if (hwp_active)
2bfc4cbb 1809 intel_pstate_hwp_set(policy->cpu);
2f86dc4c 1810
b59fe540
SP		 1811 mutex_unlock(&intel_pstate_limits_lock);
1812
93f0822d
DB		 1813 return 0;
1814}
1815
80b120ca
RW		 1816static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1817 struct cpudata *cpu)
1818{
1819 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1820 policy->max < policy->cpuinfo.max_freq &&
1821 policy->max > cpu->pstate.max_freq) {
1822 pr_debug("policy->max > max non turbo frequency\n");
1823 policy->max = policy->cpuinfo.max_freq;
1824 }
1825}
1826
93f0822d
DB		 1827static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1828{
7d9a8a9f 1829 struct cpudata *cpu = all_cpu_data[policy->cpu];
7d9a8a9f
SP		 1830
1831 update_turbo_state();
80b120ca
RW		 1832 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1833 intel_pstate_get_max_freq(cpu));
93f0822d 1834
285cb990 1835 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 1836 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 1837 return -EINVAL;
1838
80b120ca
RW		 1839 intel_pstate_adjust_policy_max(policy, cpu);
1840
93f0822d
DB		 1841 return 0;
1842}
1843
001c76f0
RW		 1844static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1845{
1846 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1847}
1848
bb18008f 1849static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 1850{
001c76f0 1851 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 1852
001c76f0 1853 intel_pstate_clear_update_util_hook(policy->cpu);
984edbdc
SP		 1854 if (hwp_active)
1855 intel_pstate_hwp_save_state(policy);
1856 else
001c76f0
RW		 1857 intel_cpufreq_stop_cpu(policy);
1858}
bb18008f 1859
001c76f0
RW		 1860static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1861{
1862 intel_pstate_exit_perf_limits(policy);
a4675fbc 1863
001c76f0 1864 policy->fast_switch_possible = false;
2f86dc4c 1865
001c76f0 1866 return 0;
93f0822d
DB		 1867}
1868
001c76f0 1869static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 1870{
93f0822d 1871 struct cpudata *cpu;
52e0a509 1872 int rc;
93f0822d
DB		 1873
1874 rc = intel_pstate_init_cpu(policy->cpu);
1875 if (rc)
1876 return rc;
1877
1878 cpu = all_cpu_data[policy->cpu];
1879
1a4fe38a
SP		 1880 cpu->max_perf_ratio = 0xFF;
1881 cpu->min_perf_ratio = 0;
93f0822d 1882
b27580b0
DB		 1883 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1884 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 1885
1886 /* cpuinfo and default policy values */
b27580b0 1887 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e 1888 update_turbo_state();
7de32556 1889 policy->cpuinfo.max_freq = global.turbo_disabled ?
983e600e
SP		 1890 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1891 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1892
9522a2ff 1893 intel_pstate_init_acpi_perf_limits(policy);
93f0822d 1894
001c76f0
RW		 1895 policy->fast_switch_possible = true;
1896
93f0822d
DB		 1897 return 0;
1898}
1899
001c76f0 1900static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 1901{
001c76f0
RW		 1902 int ret = __intel_pstate_cpu_init(policy);
1903
1904 if (ret)
1905 return ret;
1906
7de32556 1907 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
001c76f0
RW		 1908 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1909 else
1910 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 1911
1912 return 0;
1913}
1914
001c76f0 1915static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 1916 .flags = CPUFREQ_CONST_LOOPS,
1917 .verify = intel_pstate_verify_policy,
1918 .setpolicy = intel_pstate_set_policy,
984edbdc 1919 .suspend = intel_pstate_hwp_save_state,
8442885f 1920 .resume = intel_pstate_resume,
93f0822d 1921 .init = intel_pstate_cpu_init,
9522a2ff 1922 .exit = intel_pstate_cpu_exit,
bb18008f 1923 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 1924 .name = "intel_pstate",
93f0822d
DB		 1925};
1926
001c76f0
RW		 1927static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1928{
1929 struct cpudata *cpu = all_cpu_data[policy->cpu];
001c76f0
RW		 1930
1931 update_turbo_state();
80b120ca
RW		 1932 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1933 intel_pstate_get_max_freq(cpu));
001c76f0 1934
80b120ca 1935 intel_pstate_adjust_policy_max(policy, cpu);
001c76f0 1936
c5a2ee7d
RW		 1937 intel_pstate_update_perf_limits(policy, cpu);
1938
001c76f0
RW		 1939 return 0;
1940}
1941
50e9ffab
DS		 1942/* Use of trace in passive mode:
1943 *
1944 * In passive mode the trace core_busy field (also known as the
1945 * performance field, and lablelled as such on the graphs; also known as
1946 * core_avg_perf) is not needed and so is re-assigned to indicate if the
1947 * driver call was via the normal or fast switch path. Various graphs
1948 * output from the intel_pstate_tracer.py utility that include core_busy
1949 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
1950 * so we use 10 to indicate the the normal path through the driver, and
1951 * 90 to indicate the fast switch path through the driver.
1952 * The scaled_busy field is not used, and is set to 0.
1953 */
1954
1955#define INTEL_PSTATE_TRACE_TARGET 10
1956#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
1957
1958static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
1959{
1960 struct sample *sample;
1961
1962 if (!trace_pstate_sample_enabled())
1963 return;
1964
1965 if (!intel_pstate_sample(cpu, ktime_get()))
1966 return;
1967
1968 sample = &cpu->sample;
1969 trace_pstate_sample(trace_type,
1970 0,
1971 old_pstate,
1972 cpu->pstate.current_pstate,
1973 sample->mperf,
1974 sample->aperf,
1975 sample->tsc,
1976 get_avg_frequency(cpu),
1977 fp_toint(cpu->iowait_boost * 100));
1978}
1979
001c76f0
RW		 1980static int intel_cpufreq_target(struct cpufreq_policy *policy,
1981 unsigned int target_freq,
1982 unsigned int relation)
1983{
1984 struct cpudata *cpu = all_cpu_data[policy->cpu];
1985 struct cpufreq_freqs freqs;
50e9ffab 1986 int target_pstate, old_pstate;
001c76f0 1987
64897b20
RW		 1988 update_turbo_state();
1989
001c76f0 1990 freqs.old = policy->cur;
64897b20 1991 freqs.new = target_freq;
001c76f0
RW		 1992
1993 cpufreq_freq_transition_begin(policy, &freqs);
1994 switch (relation) {
1995 case CPUFREQ_RELATION_L:
1996 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1997 break;
1998 case CPUFREQ_RELATION_H:
1999 target_pstate = freqs.new / cpu->pstate.scaling;
2000 break;
2001 default:
2002 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2003 break;
2004 }
2005 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2006 old_pstate = cpu->pstate.current_pstate;
001c76f0
RW		 2007 if (target_pstate != cpu->pstate.current_pstate) {
2008 cpu->pstate.current_pstate = target_pstate;
2009 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2010 pstate_funcs.get_val(cpu, target_pstate));
2011 }
64078299 2012 freqs.new = target_pstate * cpu->pstate.scaling;
50e9ffab 2013 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
001c76f0
RW		 2014 cpufreq_freq_transition_end(policy, &freqs, false);
2015
2016 return 0;
2017}
2018
2019static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2020 unsigned int target_freq)
2021{
2022 struct cpudata *cpu = all_cpu_data[policy->cpu];
50e9ffab 2023 int target_pstate, old_pstate;
001c76f0 2024
64897b20
RW		 2025 update_turbo_state();
2026
001c76f0 2027 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
64078299 2028 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2029 old_pstate = cpu->pstate.current_pstate;
001c76f0 2030 intel_pstate_update_pstate(cpu, target_pstate);
50e9ffab 2031 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
64078299 2032 return target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2033}
2034
2035static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2036{
2037 int ret = __intel_pstate_cpu_init(policy);
2038
2039 if (ret)
2040 return ret;
2041
2042 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
1b72e7fd 2043 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
001c76f0
RW		 2044 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2045 policy->cur = policy->cpuinfo.min_freq;
2046
2047 return 0;
2048}
2049
2050static struct cpufreq_driver intel_cpufreq = {
2051 .flags = CPUFREQ_CONST_LOOPS,
2052 .verify = intel_cpufreq_verify_policy,
2053 .target = intel_cpufreq_target,
2054 .fast_switch = intel_cpufreq_fast_switch,
2055 .init = intel_cpufreq_cpu_init,
2056 .exit = intel_pstate_cpu_exit,
2057 .stop_cpu = intel_cpufreq_stop_cpu,
2058 .name = "intel_cpufreq",
2059};
2060
ee8df89a 2061static struct cpufreq_driver *default_driver = &intel_pstate;
001c76f0 2062
fb1fe104
RW		 2063static void intel_pstate_driver_cleanup(void)
2064{
2065 unsigned int cpu;
2066
2067 get_online_cpus();
2068 for_each_online_cpu(cpu) {
2069 if (all_cpu_data[cpu]) {
2070 if (intel_pstate_driver == &intel_pstate)
2071 intel_pstate_clear_update_util_hook(cpu);
2072
2073 kfree(all_cpu_data[cpu]);
2074 all_cpu_data[cpu] = NULL;
2075 }
2076 }
2077 put_online_cpus();
ee8df89a 2078 intel_pstate_driver = NULL;
fb1fe104
RW		 2079}
2080
ee8df89a 2081static int intel_pstate_register_driver(struct cpufreq_driver *driver)
fb1fe104
RW		 2082{
2083 int ret;
2084
c5a2ee7d
RW		 2085 memset(&global, 0, sizeof(global));
2086 global.max_perf_pct = 100;
c3a49c89 2087
ee8df89a 2088 intel_pstate_driver = driver;
fb1fe104
RW		 2089 ret = cpufreq_register_driver(intel_pstate_driver);
2090 if (ret) {
2091 intel_pstate_driver_cleanup();
2092 return ret;
2093 }
2094
c5a2ee7d
RW		 2095 global.min_perf_pct = min_perf_pct_min();
2096
fb1fe104
RW		 2097 return 0;
2098}
2099
2100static int intel_pstate_unregister_driver(void)
2101{
2102 if (hwp_active)
2103 return -EBUSY;
2104
fb1fe104
RW		 2105 cpufreq_unregister_driver(intel_pstate_driver);
2106 intel_pstate_driver_cleanup();
2107
2108 return 0;
2109}
2110
2111static ssize_t intel_pstate_show_status(char *buf)
2112{
ee8df89a 2113 if (!intel_pstate_driver)
fb1fe104
RW		 2114 return sprintf(buf, "off\n");
2115
2116 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2117 "active" : "passive");
2118}
2119
2120static int intel_pstate_update_status(const char *buf, size_t size)
2121{
2122 int ret;
2123
2124 if (size == 3 && !strncmp(buf, "off", size))
ee8df89a 2125 return intel_pstate_driver ?
fb1fe104
RW		 2126 intel_pstate_unregister_driver() : -EINVAL;
2127
2128 if (size == 6 && !strncmp(buf, "active", size)) {
ee8df89a 2129 if (intel_pstate_driver) {
fb1fe104
RW		 2130 if (intel_pstate_driver == &intel_pstate)
2131 return 0;
2132
2133 ret = intel_pstate_unregister_driver();
2134 if (ret)
2135 return ret;
2136 }
2137
ee8df89a 2138 return intel_pstate_register_driver(&intel_pstate);
fb1fe104
RW		 2139 }
2140
2141 if (size == 7 && !strncmp(buf, "passive", size)) {
ee8df89a 2142 if (intel_pstate_driver) {
0042b2c0 2143 if (intel_pstate_driver == &intel_cpufreq)
fb1fe104
RW		 2144 return 0;
2145
2146 ret = intel_pstate_unregister_driver();
2147 if (ret)
2148 return ret;
2149 }
2150
ee8df89a 2151 return intel_pstate_register_driver(&intel_cpufreq);
fb1fe104
RW		 2152 }
2153
2154 return -EINVAL;
2155}
2156
eed43609
JZ		 2157static int no_load __initdata;
2158static int no_hwp __initdata;
2159static int hwp_only __initdata;
29327c84 2160static unsigned int force_load __initdata;
6be26498 2161
29327c84 2162static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2163{
016c8150 2164 if (!pstate_funcs.get_max() ||
c410833a
SK		 2165 !pstate_funcs.get_min() ||
2166 !pstate_funcs.get_turbo())
b563b4e3
DB		 2167 return -ENODEV;
2168
b563b4e3
DB		 2169 return 0;
2170}
016c8150 2171
29327c84 2172static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2173{
2174 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2175 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2176 pstate_funcs.get_min = funcs->get_min;
2177 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2178 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2179 pstate_funcs.get_val = funcs->get_val;
007bea09 2180 pstate_funcs.get_vid = funcs->get_vid;
6e34e1f2 2181 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
016c8150
DB		 2182}
2183
9522a2ff 2184#ifdef CONFIG_ACPI
fbbcdc07 2185
29327c84 2186static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2187{
2188 int i;
2189
2190 for_each_possible_cpu(i) {
2191 acpi_status status;
2192 union acpi_object *pss;
2193 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2194 struct acpi_processor *pr = per_cpu(processors, i);
2195
2196 if (!pr)
2197 continue;
2198
2199 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2200 if (ACPI_FAILURE(status))
2201 continue;
2202
2203 pss = buffer.pointer;
2204 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2205 kfree(pss);
2206 return false;
2207 }
2208
2209 kfree(pss);
2210 }
2211
2212 return true;
2213}
2214
29327c84 2215static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2216{
2217 int i;
2218
2219 for_each_possible_cpu(i) {
2220 struct acpi_processor *pr = per_cpu(processors, i);
2221
2222 if (!pr)
2223 continue;
2224 if (acpi_has_method(pr->handle, "_PPC"))
2225 return true;
2226 }
2227 return false;
2228}
2229
2230enum {
2231 PSS,
2232 PPC,
2233};
2234
fbbcdc07 2235/* Hardware vendor-specific info that has its own power management modes */
5e932321
TK		 2236static struct acpi_platform_list plat_info[] __initdata = {
2237 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2238 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2239 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2240 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2241 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2242 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2243 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2244 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2245 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2246 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2247 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2248 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2249 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2250 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2251 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2252 { } /* End */
fbbcdc07
AH		 2253};
2254
29327c84 2255static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07 2256{
2f86dc4c
DB		 2257 const struct x86_cpu_id *id;
2258 u64 misc_pwr;
5e932321 2259 int idx;
2f86dc4c
DB		 2260
2261 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2262 if (id) {
2263 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2264 if ( misc_pwr & (1 << 8))
2265 return true;
2266 }
fbbcdc07 2267
5e932321
TK		 2268 idx = acpi_match_platform_list(plat_info);
2269 if (idx < 0)
fbbcdc07
AH		 2270 return false;
2271
5e932321
TK		 2272 switch (plat_info[idx].data) {
2273 case PSS:
2274 return intel_pstate_no_acpi_pss();
2275 case PPC:
2276 return intel_pstate_has_acpi_ppc() && !force_load;
fbbcdc07
AH		 2277 }
2278
2279 return false;
2280}
d0ea59e1
RW		 2281
2282static void intel_pstate_request_control_from_smm(void)
2283{
2284 /*
2285 * It may be unsafe to request P-states control from SMM if _PPC support
2286 * has not been enabled.
2287 */
2288 if (acpi_ppc)
2289 acpi_processor_pstate_control();
2290}
fbbcdc07
AH		 2291#else /* CONFIG_ACPI not enabled */
2292static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2293static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2294static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2295#endif /* CONFIG_ACPI */
2296
7791e4aa
SP		 2297static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2298 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2299 {}
2300};
2301
93f0822d
DB		 2302static int __init intel_pstate_init(void)
2303{
eb5139d1 2304 int rc;
93f0822d 2305
6be26498
DB		 2306 if (no_load)
2307 return -ENODEV;
2308
eb5139d1 2309 if (x86_match_cpu(hwp_support_ids)) {
2f49afc2 2310 copy_cpu_funcs(&core_funcs);
c4f3f70c 2311 if (!no_hwp) {
eb5139d1
RW		 2312 hwp_active++;
2313 intel_pstate.attr = hwp_cpufreq_attrs;
2314 goto hwp_cpu_matched;
2315 }
2316 } else {
2317 const struct x86_cpu_id *id;
7791e4aa 2318
eb5139d1
RW		 2319 id = x86_match_cpu(intel_pstate_cpu_ids);
2320 if (!id)
2321 return -ENODEV;
93f0822d 2322
2f49afc2 2323 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
eb5139d1 2324 }
016c8150 2325
b563b4e3
DB		 2326 if (intel_pstate_msrs_not_valid())
2327 return -ENODEV;
2328
7791e4aa
SP		 2329hwp_cpu_matched:
2330 /*
2331 * The Intel pstate driver will be ignored if the platform
2332 * firmware has its own power management modes.
2333 */
2334 if (intel_pstate_platform_pwr_mgmt_exists())
2335 return -ENODEV;
2336
fb1fe104
RW		 2337 if (!hwp_active && hwp_only)
2338 return -ENOTSUPP;
2339
4836df17 2340 pr_info("Intel P-state driver initializing\n");
93f0822d 2341
fad953ce 2342 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
93f0822d
DB		 2343 if (!all_cpu_data)
2344 return -ENOMEM;
93f0822d 2345
d0ea59e1
RW		 2346 intel_pstate_request_control_from_smm();
2347
93f0822d 2348 intel_pstate_sysfs_expose_params();
b69880f9 2349
0c30b65b 2350 mutex_lock(&intel_pstate_driver_lock);
ee8df89a 2351 rc = intel_pstate_register_driver(default_driver);
0c30b65b 2352 mutex_unlock(&intel_pstate_driver_lock);
fb1fe104
RW		 2353 if (rc)
2354 return rc;
366430b5 2355
7791e4aa 2356 if (hwp_active)
4836df17 2357 pr_info("HWP enabled\n");
7791e4aa 2358
fb1fe104 2359 return 0;
93f0822d
DB		 2360}
2361device_initcall(intel_pstate_init);
2362
6be26498
DB		 2363static int __init intel_pstate_setup(char *str)
2364{
2365 if (!str)
2366 return -EINVAL;
2367
001c76f0 2368 if (!strcmp(str, "disable")) {
6be26498 2369 no_load = 1;
001c76f0
RW		 2370 } else if (!strcmp(str, "passive")) {
2371 pr_info("Passive mode enabled\n");
ee8df89a 2372 default_driver = &intel_cpufreq;
001c76f0
RW		 2373 no_hwp = 1;
2374 }
539342f6 2375 if (!strcmp(str, "no_hwp")) {
4836df17 2376 pr_info("HWP disabled\n");
2f86dc4c 2377 no_hwp = 1;
539342f6 2378 }
aa4ea34d
EZ		 2379 if (!strcmp(str, "force"))
2380 force_load = 1;
d64c3b0b
KCA		 2381 if (!strcmp(str, "hwp_only"))
2382 hwp_only = 1;
eae48f04
SP		 2383 if (!strcmp(str, "per_cpu_perf_limits"))
2384 per_cpu_limits = true;
9522a2ff
SP		 2385
2386#ifdef CONFIG_ACPI
2387 if (!strcmp(str, "support_acpi_ppc"))
2388 acpi_ppc = true;
2389#endif
2390
6be26498
DB		 2391 return 0;
2392}
2393early_param("intel_pstate", intel_pstate_setup);
2394
93f0822d
DB		 2395MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2396MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2397MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)