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cpufreq: dt: Add support for r8a7743 and r8a7745
[linux-2.6-block.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
22#include <linux/sched.h>
23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/debugfs.h>
fbbcdc07 30#include <linux/acpi.h>
d6472302 31#include <linux/vmalloc.h>
93f0822d
DB		 32#include <trace/events/power.h>
33
34#include <asm/div64.h>
35#include <asm/msr.h>
36#include <asm/cpu_device_id.h>
64df1fdf 37#include <asm/cpufeature.h>
5b20c944 38#include <asm/intel-family.h>
93f0822d 39
938d21a2
PL		 40#define ATOM_RATIOS 0x66a
41#define ATOM_VIDS 0x66b
42#define ATOM_TURBO_RATIOS 0x66c
43#define ATOM_TURBO_VIDS 0x66d
61d8d2ab 44
9522a2ff
SP		 45#ifdef CONFIG_ACPI
46#include <acpi/processor.h>
47#endif
48
f0fe3cd7 49#define FRAC_BITS 8
93f0822d
DB		 50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 52
a1c9787d
RW		 53#define EXT_BITS 6
54#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55
93f0822d
DB		 56static inline int32_t mul_fp(int32_t x, int32_t y)
57{
58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
59}
60
7180dddf 61static inline int32_t div_fp(s64 x, s64 y)
93f0822d 62{
7180dddf 63 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 64}
65
d022a65e
DB		 66static inline int ceiling_fp(int32_t x)
67{
68 int mask, ret;
69
70 ret = fp_toint(x);
71 mask = (1 << FRAC_BITS) - 1;
72 if (x & mask)
73 ret += 1;
74 return ret;
75}
76
a1c9787d
RW		 77static inline u64 mul_ext_fp(u64 x, u64 y)
78{
79 return (x * y) >> EXT_FRAC_BITS;
80}
81
82static inline u64 div_ext_fp(u64 x, u64 y)
83{
84 return div64_u64(x << EXT_FRAC_BITS, y);
85}
86
13ad7701
SP		 87/**
88 * struct sample - Store performance sample
a1c9787d 89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 90 * performance during last sample period
91 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 92 * P state. This can be different than core_avg_perf
13ad7701
SP		 93 * to account for cpu idle period
94 * @aperf: Difference of actual performance frequency clock count
95 * read from APERF MSR between last and current sample
96 * @mperf: Difference of maximum performance frequency clock count
97 * read from MPERF MSR between last and current sample
98 * @tsc: Difference of time stamp counter between last and
99 * current sample
13ad7701
SP		 100 * @time: Current time from scheduler
101 *
102 * This structure is used in the cpudata structure to store performance sample
103 * data for choosing next P State.
104 */
93f0822d 105struct sample {
a1c9787d 106 int32_t core_avg_perf;
157386b6 107 int32_t busy_scaled;
93f0822d
DB		 108 u64 aperf;
109 u64 mperf;
4055fad3 110 u64 tsc;
a4675fbc 111 u64 time;
93f0822d
DB		 112};
113
13ad7701
SP		 114/**
115 * struct pstate_data - Store P state data
116 * @current_pstate: Current requested P state
117 * @min_pstate: Min P state possible for this platform
118 * @max_pstate: Max P state possible for this platform
119 * @max_pstate_physical:This is physical Max P state for a processor
120 * This can be higher than the max_pstate which can
121 * be limited by platform thermal design power limits
122 * @scaling: Scaling factor to convert frequency to cpufreq
123 * frequency units
124 * @turbo_pstate: Max Turbo P state possible for this platform
125 *
126 * Stores the per cpu model P state limits and current P state.
127 */
93f0822d
DB		 128struct pstate_data {
129 int current_pstate;
130 int min_pstate;
131 int max_pstate;
3bcc6fa9 132 int max_pstate_physical;
b27580b0 133 int scaling;
93f0822d
DB		 134 int turbo_pstate;
135};
136
13ad7701
SP		 137/**
138 * struct vid_data - Stores voltage information data
139 * @min: VID data for this platform corresponding to
140 * the lowest P state
141 * @max: VID data corresponding to the highest P State.
142 * @turbo: VID data for turbo P state
143 * @ratio: Ratio of (vid max - vid min) /
144 * (max P state - Min P State)
145 *
146 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
147 * This data is used in Atom platforms, where in addition to target P state,
148 * the voltage data needs to be specified to select next P State.
149 */
007bea09 150struct vid_data {
21855ff5
DB		 151 int min;
152 int max;
153 int turbo;
007bea09
DB		 154 int32_t ratio;
155};
156
13ad7701
SP		 157/**
158 * struct _pid - Stores PID data
159 * @setpoint: Target set point for busyness or performance
160 * @integral: Storage for accumulated error values
161 * @p_gain: PID proportional gain
162 * @i_gain: PID integral gain
163 * @d_gain: PID derivative gain
164 * @deadband: PID deadband
165 * @last_err: Last error storage for integral part of PID calculation
166 *
167 * Stores PID coefficients and last error for PID controller.
168 */
93f0822d
DB		 169struct _pid {
170 int setpoint;
171 int32_t integral;
172 int32_t p_gain;
173 int32_t i_gain;
174 int32_t d_gain;
175 int deadband;
d253d2a5 176 int32_t last_err;
93f0822d
DB		 177};
178
eae48f04
SP		 179/**
180 * struct perf_limits - Store user and policy limits
181 * @no_turbo: User requested turbo state from intel_pstate sysfs
182 * @turbo_disabled: Platform turbo status either from msr
183 * MSR_IA32_MISC_ENABLE or when maximum available pstate
184 * matches the maximum turbo pstate
185 * @max_perf_pct: Effective maximum performance limit in percentage, this
186 * is minimum of either limits enforced by cpufreq policy
187 * or limits from user set limits via intel_pstate sysfs
188 * @min_perf_pct: Effective minimum performance limit in percentage, this
189 * is maximum of either limits enforced by cpufreq policy
190 * or limits from user set limits via intel_pstate sysfs
191 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
192 * This value is used to limit max pstate
193 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
194 * This value is used to limit min pstate
195 * @max_policy_pct: The maximum performance in percentage enforced by
196 * cpufreq setpolicy interface
197 * @max_sysfs_pct: The maximum performance in percentage enforced by
198 * intel pstate sysfs interface, unused when per cpu
199 * controls are enforced
200 * @min_policy_pct: The minimum performance in percentage enforced by
201 * cpufreq setpolicy interface
202 * @min_sysfs_pct: The minimum performance in percentage enforced by
203 * intel pstate sysfs interface, unused when per cpu
204 * controls are enforced
205 *
206 * Storage for user and policy defined limits.
207 */
208struct perf_limits {
209 int no_turbo;
210 int turbo_disabled;
211 int max_perf_pct;
212 int min_perf_pct;
213 int32_t max_perf;
214 int32_t min_perf;
215 int max_policy_pct;
216 int max_sysfs_pct;
217 int min_policy_pct;
218 int min_sysfs_pct;
219};
220
13ad7701
SP		 221/**
222 * struct cpudata - Per CPU instance data storage
223 * @cpu: CPU number for this instance data
2f1d407a 224 * @policy: CPUFreq policy value
13ad7701 225 * @update_util: CPUFreq utility callback information
4578ee7e 226 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 227 * @iowait_boost: iowait-related boost fraction
228 * @last_update: Time of the last update.
13ad7701
SP		 229 * @pstate: Stores P state limits for this CPU
230 * @vid: Stores VID limits for this CPU
231 * @pid: Stores PID parameters for this CPU
232 * @last_sample_time: Last Sample time
233 * @prev_aperf: Last APERF value read from APERF MSR
234 * @prev_mperf: Last MPERF value read from MPERF MSR
235 * @prev_tsc: Last timestamp counter (TSC) value
236 * @prev_cummulative_iowait: IO Wait time difference from last and
237 * current sample
238 * @sample: Storage for storing last Sample data
eae48f04
SP		 239 * @perf_limits: Pointer to perf_limit unique to this CPU
240 * Not all field in the structure are applicable
241 * when per cpu controls are enforced
9522a2ff
SP		 242 * @acpi_perf_data: Stores ACPI perf information read from _PSS
243 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
13ad7701
SP		 244 *
245 * This structure stores per CPU instance data for all CPUs.
246 */
93f0822d
DB		 247struct cpudata {
248 int cpu;
249
2f1d407a 250 unsigned int policy;
a4675fbc 251 struct update_util_data update_util;
4578ee7e 252 bool update_util_set;
93f0822d 253
93f0822d 254 struct pstate_data pstate;
007bea09 255 struct vid_data vid;
93f0822d 256 struct _pid pid;
93f0822d 257
09c448d3 258 u64 last_update;
a4675fbc 259 u64 last_sample_time;
93f0822d
DB		 260 u64 prev_aperf;
261 u64 prev_mperf;
4055fad3 262 u64 prev_tsc;
63d1d656 263 u64 prev_cummulative_iowait;
d37e2b76 264 struct sample sample;
eae48f04 265 struct perf_limits *perf_limits;
9522a2ff
SP		 266#ifdef CONFIG_ACPI
267 struct acpi_processor_performance acpi_perf_data;
268 bool valid_pss_table;
269#endif
09c448d3 270 unsigned int iowait_boost;
93f0822d
DB		 271};
272
273static struct cpudata **all_cpu_data;
13ad7701
SP		 274
275/**
3954517e 276 * struct pstate_adjust_policy - Stores static PID configuration data
13ad7701
SP		 277 * @sample_rate_ms: PID calculation sample rate in ms
278 * @sample_rate_ns: Sample rate calculation in ns
279 * @deadband: PID deadband
280 * @setpoint: PID Setpoint
281 * @p_gain_pct: PID proportional gain
282 * @i_gain_pct: PID integral gain
283 * @d_gain_pct: PID derivative gain
284 *
285 * Stores per CPU model static PID configuration data.
286 */
93f0822d
DB		 287struct pstate_adjust_policy {
288 int sample_rate_ms;
a4675fbc 289 s64 sample_rate_ns;
93f0822d
DB		 290 int deadband;
291 int setpoint;
292 int p_gain_pct;
293 int d_gain_pct;
294 int i_gain_pct;
295};
296
13ad7701
SP		 297/**
298 * struct pstate_funcs - Per CPU model specific callbacks
299 * @get_max: Callback to get maximum non turbo effective P state
300 * @get_max_physical: Callback to get maximum non turbo physical P state
301 * @get_min: Callback to get minimum P state
302 * @get_turbo: Callback to get turbo P state
303 * @get_scaling: Callback to get frequency scaling factor
304 * @get_val: Callback to convert P state to actual MSR write value
305 * @get_vid: Callback to get VID data for Atom platforms
306 * @get_target_pstate: Callback to a function to calculate next P state to use
307 *
308 * Core and Atom CPU models have different way to get P State limits. This
309 * structure is used to store those callbacks.
310 */
016c8150
DB		 311struct pstate_funcs {
312 int (*get_max)(void);
3bcc6fa9 313 int (*get_max_physical)(void);
016c8150
DB		 314 int (*get_min)(void);
315 int (*get_turbo)(void);
b27580b0 316 int (*get_scaling)(void);
fdfdb2b1 317 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 318 void (*get_vid)(struct cpudata *);
157386b6 319 int32_t (*get_target_pstate)(struct cpudata *);
93f0822d
DB		 320};
321
13ad7701
SP		 322/**
323 * struct cpu_defaults- Per CPU model default config data
324 * @pid_policy: PID config data
325 * @funcs: Callback function data
326 */
016c8150
DB		 327struct cpu_defaults {
328 struct pstate_adjust_policy pid_policy;
329 struct pstate_funcs funcs;
93f0822d
DB		 330};
331
157386b6 332static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
e70eed2b 333static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
157386b6 334
4a7cb7a9
JZ		 335static struct pstate_adjust_policy pid_params __read_mostly;
336static struct pstate_funcs pstate_funcs __read_mostly;
337static int hwp_active __read_mostly;
eae48f04 338static bool per_cpu_limits __read_mostly;
016c8150 339
9522a2ff
SP		 340#ifdef CONFIG_ACPI
341static bool acpi_ppc;
342#endif
13ad7701 343
51443fbf
PB		 344static struct perf_limits performance_limits = {
345 .no_turbo = 0,
346 .turbo_disabled = 0,
347 .max_perf_pct = 100,
348 .max_perf = int_tofp(1),
349 .min_perf_pct = 100,
350 .min_perf = int_tofp(1),
351 .max_policy_pct = 100,
352 .max_sysfs_pct = 100,
353 .min_policy_pct = 0,
354 .min_sysfs_pct = 0,
355};
356
357static struct perf_limits powersave_limits = {
93f0822d 358 .no_turbo = 0,
4521e1a0 359 .turbo_disabled = 0,
93f0822d
DB		 360 .max_perf_pct = 100,
361 .max_perf = int_tofp(1),
362 .min_perf_pct = 0,
363 .min_perf = 0,
d8f469e9
DB		 364 .max_policy_pct = 100,
365 .max_sysfs_pct = 100,
a0475992
KCA		 366 .min_policy_pct = 0,
367 .min_sysfs_pct = 0,
93f0822d
DB		 368};
369
51443fbf
PB		 370#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
371static struct perf_limits *limits = &performance_limits;
372#else
373static struct perf_limits *limits = &powersave_limits;
374#endif
375
a410c03d
SP		 376static DEFINE_MUTEX(intel_pstate_limits_lock);
377
9522a2ff 378#ifdef CONFIG_ACPI
2b3ec765
SP		 379
380static bool intel_pstate_get_ppc_enable_status(void)
381{
382 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
383 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
384 return true;
385
386 return acpi_ppc;
387}
388
9522a2ff
SP		 389static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
390{
391 struct cpudata *cpu;
9522a2ff
SP		 392 int ret;
393 int i;
394
e59a8f7f
SP		 395 if (hwp_active)
396 return;
397
2b3ec765 398 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 399 return;
400
401 cpu = all_cpu_data[policy->cpu];
402
403 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
404 policy->cpu);
405 if (ret)
406 return;
407
408 /*
409 * Check if the control value in _PSS is for PERF_CTL MSR, which should
410 * guarantee that the states returned by it map to the states in our
411 * list directly.
412 */
413 if (cpu->acpi_perf_data.control_register.space_id !=
414 ACPI_ADR_SPACE_FIXED_HARDWARE)
415 goto err;
416
417 /*
418 * If there is only one entry _PSS, simply ignore _PSS and continue as
419 * usual without taking _PSS into account
420 */
421 if (cpu->acpi_perf_data.state_count < 2)
422 goto err;
423
424 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
425 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
426 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
427 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
428 (u32) cpu->acpi_perf_data.states[i].core_frequency,
429 (u32) cpu->acpi_perf_data.states[i].power,
430 (u32) cpu->acpi_perf_data.states[i].control);
431 }
432
433 /*
434 * The _PSS table doesn't contain whole turbo frequency range.
435 * This just contains +1 MHZ above the max non turbo frequency,
436 * with control value corresponding to max turbo ratio. But
437 * when cpufreq set policy is called, it will call with this
438 * max frequency, which will cause a reduced performance as
439 * this driver uses real max turbo frequency as the max
440 * frequency. So correct this frequency in _PSS table to
b00345d1 441 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 442 * Also need to convert to MHz as _PSS freq is in MHz.
443 */
b00345d1 444 if (!limits->turbo_disabled)
9522a2ff
SP		 445 cpu->acpi_perf_data.states[0].core_frequency =
446 policy->cpuinfo.max_freq / 1000;
447 cpu->valid_pss_table = true;
6cacd115 448 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 449
450 return;
451
452 err:
453 cpu->valid_pss_table = false;
454 acpi_processor_unregister_performance(policy->cpu);
455}
456
457static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
458{
459 struct cpudata *cpu;
460
461 cpu = all_cpu_data[policy->cpu];
462 if (!cpu->valid_pss_table)
463 return;
464
465 acpi_processor_unregister_performance(policy->cpu);
466}
467
468#else
469static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
470{
471}
472
473static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
474{
475}
476#endif
477
93f0822d 478static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
c410833a 479 int deadband, int integral) {
b54a0dfd
PL		 480 pid->setpoint = int_tofp(setpoint);
481 pid->deadband = int_tofp(deadband);
93f0822d 482 pid->integral = int_tofp(integral);
d98d099b 483 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB		 484}
485
486static inline void pid_p_gain_set(struct _pid *pid, int percent)
487{
22590efb 488 pid->p_gain = div_fp(percent, 100);
93f0822d
DB		 489}
490
491static inline void pid_i_gain_set(struct _pid *pid, int percent)
492{
22590efb 493 pid->i_gain = div_fp(percent, 100);
93f0822d
DB		 494}
495
496static inline void pid_d_gain_set(struct _pid *pid, int percent)
497{
22590efb 498 pid->d_gain = div_fp(percent, 100);
93f0822d
DB		 499}
500
d253d2a5 501static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 502{
d253d2a5 503 signed int result;
93f0822d
DB		 504 int32_t pterm, dterm, fp_error;
505 int32_t integral_limit;
506
b54a0dfd 507 fp_error = pid->setpoint - busy;
93f0822d 508
b54a0dfd 509 if (abs(fp_error) <= pid->deadband)
93f0822d
DB		 510 return 0;
511
512 pterm = mul_fp(pid->p_gain, fp_error);
513
514 pid->integral += fp_error;
515
e0d4c8f8
KCA		 516 /*
517 * We limit the integral here so that it will never
518 * get higher than 30. This prevents it from becoming
519 * too large an input over long periods of time and allows
520 * it to get factored out sooner.
521 *
522 * The value of 30 was chosen through experimentation.
523 */
93f0822d
DB		 524 integral_limit = int_tofp(30);
525 if (pid->integral > integral_limit)
526 pid->integral = integral_limit;
527 if (pid->integral < -integral_limit)
528 pid->integral = -integral_limit;
529
d253d2a5
BS		 530 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
531 pid->last_err = fp_error;
93f0822d
DB		 532
533 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
51d211e9 534 result = result + (1 << (FRAC_BITS-1));
93f0822d
DB		 535 return (signed int)fp_toint(result);
536}
537
538static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
539{
016c8150
DB		 540 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
541 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
542 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d 543
2d8d1f18 544 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
93f0822d
DB		 545}
546
93f0822d
DB		 547static inline void intel_pstate_reset_all_pid(void)
548{
549 unsigned int cpu;
845c1cbe 550
93f0822d
DB		 551 for_each_online_cpu(cpu) {
552 if (all_cpu_data[cpu])
553 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
554 }
555}
556
4521e1a0
GM		 557static inline void update_turbo_state(void)
558{
559 u64 misc_en;
560 struct cpudata *cpu;
561
562 cpu = all_cpu_data[0];
563 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
51443fbf 564 limits->turbo_disabled =
4521e1a0
GM		 565 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
566 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
567}
568
41cfd64c 569static void intel_pstate_hwp_set(const struct cpumask *cpumask)
2f86dc4c 570{
74da56ce 571 int min, hw_min, max, hw_max, cpu, range, adj_range;
eae48f04 572 struct perf_limits *perf_limits = limits;
74da56ce
KCA		 573 u64 value, cap;
574
41cfd64c 575 for_each_cpu(cpu, cpumask) {
eae48f04
SP		 576 int max_perf_pct, min_perf_pct;
577
578 if (per_cpu_limits)
579 perf_limits = all_cpu_data[cpu]->perf_limits;
580
f9f4872d
SP		 581 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
582 hw_min = HWP_LOWEST_PERF(cap);
583 hw_max = HWP_HIGHEST_PERF(cap);
584 range = hw_max - hw_min;
585
eae48f04
SP		 586 max_perf_pct = perf_limits->max_perf_pct;
587 min_perf_pct = perf_limits->min_perf_pct;
588
2f86dc4c 589 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
eae48f04 590 adj_range = min_perf_pct * range / 100;
74da56ce 591 min = hw_min + adj_range;
2f86dc4c
DB		 592 value &= ~HWP_MIN_PERF(~0L);
593 value |= HWP_MIN_PERF(min);
594
eae48f04 595 adj_range = max_perf_pct * range / 100;
74da56ce 596 max = hw_min + adj_range;
51443fbf 597 if (limits->no_turbo) {
74da56ce
KCA		 598 hw_max = HWP_GUARANTEED_PERF(cap);
599 if (hw_max < max)
600 max = hw_max;
2f86dc4c
DB		 601 }
602
603 value &= ~HWP_MAX_PERF(~0L);
604 value |= HWP_MAX_PERF(max);
605 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
606 }
41cfd64c 607}
2f86dc4c 608
ba41e1bc
RW		 609static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
610{
611 if (hwp_active)
612 intel_pstate_hwp_set(policy->cpus);
613
614 return 0;
615}
616
41cfd64c
VK		 617static void intel_pstate_hwp_set_online_cpus(void)
618{
619 get_online_cpus();
620 intel_pstate_hwp_set(cpu_online_mask);
2f86dc4c
DB		 621 put_online_cpus();
622}
623
93f0822d
DB		 624/************************** debugfs begin ************************/
625static int pid_param_set(void *data, u64 val)
626{
627 *(u32 *)data = val;
628 intel_pstate_reset_all_pid();
629 return 0;
630}
845c1cbe 631
93f0822d
DB		 632static int pid_param_get(void *data, u64 *val)
633{
634 *val = *(u32 *)data;
635 return 0;
636}
2d8d1f18 637DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
93f0822d
DB		 638
639struct pid_param {
640 char *name;
641 void *value;
642};
643
644static struct pid_param pid_files[] = {
016c8150
DB		 645 {"sample_rate_ms", &pid_params.sample_rate_ms},
646 {"d_gain_pct", &pid_params.d_gain_pct},
647 {"i_gain_pct", &pid_params.i_gain_pct},
648 {"deadband", &pid_params.deadband},
649 {"setpoint", &pid_params.setpoint},
650 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB		 651 {NULL, NULL}
652};
653
317dd50e 654static void __init intel_pstate_debug_expose_params(void)
93f0822d 655{
317dd50e 656 struct dentry *debugfs_parent;
93f0822d
DB		 657 int i = 0;
658
185d8245
SP		 659 if (hwp_active ||
660 pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load)
2f86dc4c 661 return;
185d8245 662
93f0822d
DB		 663 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
664 if (IS_ERR_OR_NULL(debugfs_parent))
665 return;
666 while (pid_files[i].name) {
667 debugfs_create_file(pid_files[i].name, 0660,
c410833a
SK		 668 debugfs_parent, pid_files[i].value,
669 &fops_pid_param);
93f0822d
DB		 670 i++;
671 }
672}
673
674/************************** debugfs end ************************/
675
676/************************** sysfs begin ************************/
677#define show_one(file_name, object) \
678 static ssize_t show_##file_name \
679 (struct kobject *kobj, struct attribute *attr, char *buf) \
680 { \
51443fbf 681 return sprintf(buf, "%u\n", limits->object); \
93f0822d
DB		 682 }
683
d01b1f48
KCA		 684static ssize_t show_turbo_pct(struct kobject *kobj,
685 struct attribute *attr, char *buf)
686{
687 struct cpudata *cpu;
688 int total, no_turbo, turbo_pct;
689 uint32_t turbo_fp;
690
691 cpu = all_cpu_data[0];
692
693 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
694 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 695 turbo_fp = div_fp(no_turbo, total);
d01b1f48
KCA		 696 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
697 return sprintf(buf, "%u\n", turbo_pct);
698}
699
0522424e
KCA		 700static ssize_t show_num_pstates(struct kobject *kobj,
701 struct attribute *attr, char *buf)
702{
703 struct cpudata *cpu;
704 int total;
705
706 cpu = all_cpu_data[0];
707 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
708 return sprintf(buf, "%u\n", total);
709}
710
4521e1a0
GM		 711static ssize_t show_no_turbo(struct kobject *kobj,
712 struct attribute *attr, char *buf)
713{
714 ssize_t ret;
715
716 update_turbo_state();
51443fbf
PB		 717 if (limits->turbo_disabled)
718 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
4521e1a0 719 else
51443fbf 720 ret = sprintf(buf, "%u\n", limits->no_turbo);
4521e1a0
GM		 721
722 return ret;
723}
724
93f0822d 725static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 726 const char *buf, size_t count)
93f0822d
DB		 727{
728 unsigned int input;
729 int ret;
845c1cbe 730
93f0822d
DB		 731 ret = sscanf(buf, "%u", &input);
732 if (ret != 1)
733 return -EINVAL;
4521e1a0 734
a410c03d
SP		 735 mutex_lock(&intel_pstate_limits_lock);
736
4521e1a0 737 update_turbo_state();
51443fbf 738 if (limits->turbo_disabled) {
4836df17 739 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 740 mutex_unlock(&intel_pstate_limits_lock);
4521e1a0 741 return -EPERM;
dd5fbf70 742 }
2f86dc4c 743
51443fbf 744 limits->no_turbo = clamp_t(int, input, 0, 1);
4521e1a0 745
a410c03d
SP		 746 mutex_unlock(&intel_pstate_limits_lock);
747
2f86dc4c 748 if (hwp_active)
41cfd64c 749 intel_pstate_hwp_set_online_cpus();
2f86dc4c 750
93f0822d
DB		 751 return count;
752}
753
754static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 755 const char *buf, size_t count)
93f0822d
DB		 756{
757 unsigned int input;
758 int ret;
845c1cbe 759
93f0822d
DB		 760 ret = sscanf(buf, "%u", &input);
761 if (ret != 1)
762 return -EINVAL;
763
a410c03d
SP		 764 mutex_lock(&intel_pstate_limits_lock);
765
51443fbf
PB		 766 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
767 limits->max_perf_pct = min(limits->max_policy_pct,
768 limits->max_sysfs_pct);
769 limits->max_perf_pct = max(limits->min_policy_pct,
770 limits->max_perf_pct);
771 limits->max_perf_pct = max(limits->min_perf_pct,
772 limits->max_perf_pct);
22590efb 773 limits->max_perf = div_fp(limits->max_perf_pct, 100);
845c1cbe 774
a410c03d
SP		 775 mutex_unlock(&intel_pstate_limits_lock);
776
2f86dc4c 777 if (hwp_active)
41cfd64c 778 intel_pstate_hwp_set_online_cpus();
93f0822d
DB		 779 return count;
780}
781
782static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 783 const char *buf, size_t count)
93f0822d
DB		 784{
785 unsigned int input;
786 int ret;
845c1cbe 787
93f0822d
DB		 788 ret = sscanf(buf, "%u", &input);
789 if (ret != 1)
790 return -EINVAL;
a0475992 791
a410c03d
SP		 792 mutex_lock(&intel_pstate_limits_lock);
793
51443fbf
PB		 794 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
795 limits->min_perf_pct = max(limits->min_policy_pct,
796 limits->min_sysfs_pct);
797 limits->min_perf_pct = min(limits->max_policy_pct,
798 limits->min_perf_pct);
799 limits->min_perf_pct = min(limits->max_perf_pct,
800 limits->min_perf_pct);
22590efb 801 limits->min_perf = div_fp(limits->min_perf_pct, 100);
93f0822d 802
a410c03d
SP		 803 mutex_unlock(&intel_pstate_limits_lock);
804
2f86dc4c 805 if (hwp_active)
41cfd64c 806 intel_pstate_hwp_set_online_cpus();
93f0822d
DB		 807 return count;
808}
809
93f0822d
DB		 810show_one(max_perf_pct, max_perf_pct);
811show_one(min_perf_pct, min_perf_pct);
812
813define_one_global_rw(no_turbo);
814define_one_global_rw(max_perf_pct);
815define_one_global_rw(min_perf_pct);
d01b1f48 816define_one_global_ro(turbo_pct);
0522424e 817define_one_global_ro(num_pstates);
93f0822d
DB		 818
819static struct attribute *intel_pstate_attributes[] = {
820 &no_turbo.attr,
d01b1f48 821 &turbo_pct.attr,
0522424e 822 &num_pstates.attr,
93f0822d
DB		 823 NULL
824};
825
826static struct attribute_group intel_pstate_attr_group = {
827 .attrs = intel_pstate_attributes,
828};
93f0822d 829
317dd50e 830static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 831{
317dd50e 832 struct kobject *intel_pstate_kobject;
93f0822d
DB		 833 int rc;
834
835 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
836 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 837 if (WARN_ON(!intel_pstate_kobject))
838 return;
839
2d8d1f18 840 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 841 if (WARN_ON(rc))
842 return;
843
844 /*
845 * If per cpu limits are enforced there are no global limits, so
846 * return without creating max/min_perf_pct attributes
847 */
848 if (per_cpu_limits)
849 return;
850
851 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
852 WARN_ON(rc);
853
854 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
855 WARN_ON(rc);
856
93f0822d 857}
93f0822d 858/************************** sysfs end ************************/
2f86dc4c 859
ba88d433 860static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 861{
f05c9665 862 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 863 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
864 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 865
ba88d433 866 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
2f86dc4c
DB		 867}
868
938d21a2 869static int atom_get_min_pstate(void)
19e77c28
DB		 870{
871 u64 value;
845c1cbe 872
938d21a2 873 rdmsrl(ATOM_RATIOS, value);
c16ed060 874 return (value >> 8) & 0x7F;
19e77c28
DB		 875}
876
938d21a2 877static int atom_get_max_pstate(void)
19e77c28
DB		 878{
879 u64 value;
845c1cbe 880
938d21a2 881 rdmsrl(ATOM_RATIOS, value);
c16ed060 882 return (value >> 16) & 0x7F;
19e77c28 883}
93f0822d 884
938d21a2 885static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 886{
887 u64 value;
845c1cbe 888
938d21a2 889 rdmsrl(ATOM_TURBO_RATIOS, value);
c16ed060 890 return value & 0x7F;
61d8d2ab
DB		 891}
892
fdfdb2b1 893static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 894{
895 u64 val;
896 int32_t vid_fp;
897 u32 vid;
898
144c8e17 899 val = (u64)pstate << 8;
51443fbf 900 if (limits->no_turbo && !limits->turbo_disabled)
007bea09
DB		 901 val |= (u64)1 << 32;
902
903 vid_fp = cpudata->vid.min + mul_fp(
904 int_tofp(pstate - cpudata->pstate.min_pstate),
905 cpudata->vid.ratio);
906
907 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 908 vid = ceiling_fp(vid_fp);
007bea09 909
21855ff5
DB		 910 if (pstate > cpudata->pstate.max_pstate)
911 vid = cpudata->vid.turbo;
912
fdfdb2b1 913 return val | vid;
007bea09
DB		 914}
915
1421df63 916static int silvermont_get_scaling(void)
b27580b0
DB		 917{
918 u64 value;
919 int i;
1421df63
PL		 920 /* Defined in Table 35-6 from SDM (Sept 2015) */
921 static int silvermont_freq_table[] = {
922 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 923
924 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 925 i = value & 0x7;
926 WARN_ON(i > 4);
b27580b0 927
1421df63
PL		 928 return silvermont_freq_table[i];
929}
b27580b0 930
1421df63
PL		 931static int airmont_get_scaling(void)
932{
933 u64 value;
934 int i;
935 /* Defined in Table 35-10 from SDM (Sept 2015) */
936 static int airmont_freq_table[] = {
937 83300, 100000, 133300, 116700, 80000,
938 93300, 90000, 88900, 87500};
939
940 rdmsrl(MSR_FSB_FREQ, value);
941 i = value & 0xF;
942 WARN_ON(i > 8);
943
944 return airmont_freq_table[i];
b27580b0
DB		 945}
946
938d21a2 947static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 948{
949 u64 value;
950
938d21a2 951 rdmsrl(ATOM_VIDS, value);
c16ed060
DB		 952 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
953 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 954 cpudata->vid.ratio = div_fp(
955 cpudata->vid.max - cpudata->vid.min,
956 int_tofp(cpudata->pstate.max_pstate -
957 cpudata->pstate.min_pstate));
21855ff5 958
938d21a2 959 rdmsrl(ATOM_TURBO_VIDS, value);
21855ff5 960 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 961}
962
016c8150 963static int core_get_min_pstate(void)
93f0822d
DB		 964{
965 u64 value;
845c1cbe 966
05e99c8c 967 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 968 return (value >> 40) & 0xFF;
969}
970
3bcc6fa9 971static int core_get_max_pstate_physical(void)
93f0822d
DB		 972{
973 u64 value;
845c1cbe 974
05e99c8c 975 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 976 return (value >> 8) & 0xFF;
977}
978
016c8150 979static int core_get_max_pstate(void)
93f0822d 980{
6a35fc2d
SP		 981 u64 tar;
982 u64 plat_info;
983 int max_pstate;
984 int err;
985
986 rdmsrl(MSR_PLATFORM_INFO, plat_info);
987 max_pstate = (plat_info >> 8) & 0xFF;
988
989 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
990 if (!err) {
991 /* Do some sanity checking for safety */
992 if (plat_info & 0x600000000) {
993 u64 tdp_ctrl;
994 u64 tdp_ratio;
995 int tdp_msr;
996
997 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
998 if (err)
999 goto skip_tar;
1000
5fc8f707 1001 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
6a35fc2d
SP		 1002 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1003 if (err)
1004 goto skip_tar;
1005
1becf035
SP		 1006 /* For level 1 and 2, bits[23:16] contain the ratio */
1007 if (tdp_ctrl)
1008 tdp_ratio >>= 16;
1009
1010 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
6a35fc2d
SP		 1011 if (tdp_ratio - 1 == tar) {
1012 max_pstate = tar;
1013 pr_debug("max_pstate=TAC %x\n", max_pstate);
1014 } else {
1015 goto skip_tar;
1016 }
1017 }
1018 }
845c1cbe 1019
6a35fc2d
SP		 1020skip_tar:
1021 return max_pstate;
93f0822d
DB		 1022}
1023
016c8150 1024static int core_get_turbo_pstate(void)
93f0822d
DB		 1025{
1026 u64 value;
1027 int nont, ret;
845c1cbe 1028
100cf6f2 1029 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1030 nont = core_get_max_pstate();
285cb990 1031 ret = (value) & 255;
93f0822d
DB		 1032 if (ret <= nont)
1033 ret = nont;
1034 return ret;
1035}
1036
b27580b0
DB		 1037static inline int core_get_scaling(void)
1038{
1039 return 100000;
1040}
1041
fdfdb2b1 1042static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1043{
1044 u64 val;
1045
144c8e17 1046 val = (u64)pstate << 8;
51443fbf 1047 if (limits->no_turbo && !limits->turbo_disabled)
016c8150
DB		 1048 val |= (u64)1 << 32;
1049
fdfdb2b1 1050 return val;
016c8150
DB		 1051}
1052
b34ef932
DC		 1053static int knl_get_turbo_pstate(void)
1054{
1055 u64 value;
1056 int nont, ret;
1057
100cf6f2 1058 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1059 nont = core_get_max_pstate();
1060 ret = (((value) >> 8) & 0xFF);
1061 if (ret <= nont)
1062 ret = nont;
1063 return ret;
1064}
1065
016c8150
DB		 1066static struct cpu_defaults core_params = {
1067 .pid_policy = {
1068 .sample_rate_ms = 10,
1069 .deadband = 0,
1070 .setpoint = 97,
1071 .p_gain_pct = 20,
1072 .d_gain_pct = 0,
1073 .i_gain_pct = 0,
1074 },
1075 .funcs = {
1076 .get_max = core_get_max_pstate,
3bcc6fa9 1077 .get_max_physical = core_get_max_pstate_physical,
016c8150
DB		 1078 .get_min = core_get_min_pstate,
1079 .get_turbo = core_get_turbo_pstate,
b27580b0 1080 .get_scaling = core_get_scaling,
fdfdb2b1 1081 .get_val = core_get_val,
157386b6 1082 .get_target_pstate = get_target_pstate_use_performance,
016c8150
DB		 1083 },
1084};
1085
42ce8921 1086static const struct cpu_defaults silvermont_params = {
1421df63
PL		 1087 .pid_policy = {
1088 .sample_rate_ms = 10,
1089 .deadband = 0,
1090 .setpoint = 60,
1091 .p_gain_pct = 14,
1092 .d_gain_pct = 0,
1093 .i_gain_pct = 4,
1094 },
1095 .funcs = {
1096 .get_max = atom_get_max_pstate,
1097 .get_max_physical = atom_get_max_pstate,
1098 .get_min = atom_get_min_pstate,
1099 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1100 .get_val = atom_get_val,
1421df63
PL		 1101 .get_scaling = silvermont_get_scaling,
1102 .get_vid = atom_get_vid,
e70eed2b 1103 .get_target_pstate = get_target_pstate_use_cpu_load,
1421df63
PL		 1104 },
1105};
1106
42ce8921 1107static const struct cpu_defaults airmont_params = {
19e77c28
DB		 1108 .pid_policy = {
1109 .sample_rate_ms = 10,
1110 .deadband = 0,
6a82ba6d 1111 .setpoint = 60,
19e77c28
DB		 1112 .p_gain_pct = 14,
1113 .d_gain_pct = 0,
1114 .i_gain_pct = 4,
1115 },
1116 .funcs = {
938d21a2
PL		 1117 .get_max = atom_get_max_pstate,
1118 .get_max_physical = atom_get_max_pstate,
1119 .get_min = atom_get_min_pstate,
1120 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1121 .get_val = atom_get_val,
1421df63 1122 .get_scaling = airmont_get_scaling,
938d21a2 1123 .get_vid = atom_get_vid,
e70eed2b 1124 .get_target_pstate = get_target_pstate_use_cpu_load,
19e77c28
DB		 1125 },
1126};
1127
42ce8921 1128static const struct cpu_defaults knl_params = {
b34ef932
DC		 1129 .pid_policy = {
1130 .sample_rate_ms = 10,
1131 .deadband = 0,
1132 .setpoint = 97,
1133 .p_gain_pct = 20,
1134 .d_gain_pct = 0,
1135 .i_gain_pct = 0,
1136 },
1137 .funcs = {
1138 .get_max = core_get_max_pstate,
3bcc6fa9 1139 .get_max_physical = core_get_max_pstate_physical,
b34ef932
DC		 1140 .get_min = core_get_min_pstate,
1141 .get_turbo = knl_get_turbo_pstate,
69cefc27 1142 .get_scaling = core_get_scaling,
fdfdb2b1 1143 .get_val = core_get_val,
157386b6 1144 .get_target_pstate = get_target_pstate_use_performance,
b34ef932
DC		 1145 },
1146};
1147
42ce8921 1148static const struct cpu_defaults bxt_params = {
41bad47f
SP		 1149 .pid_policy = {
1150 .sample_rate_ms = 10,
1151 .deadband = 0,
1152 .setpoint = 60,
1153 .p_gain_pct = 14,
1154 .d_gain_pct = 0,
1155 .i_gain_pct = 4,
1156 },
1157 .funcs = {
1158 .get_max = core_get_max_pstate,
1159 .get_max_physical = core_get_max_pstate_physical,
1160 .get_min = core_get_min_pstate,
1161 .get_turbo = core_get_turbo_pstate,
1162 .get_scaling = core_get_scaling,
1163 .get_val = core_get_val,
1164 .get_target_pstate = get_target_pstate_use_cpu_load,
1165 },
1166};
1167
93f0822d
DB		 1168static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1169{
1170 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 1171 int max_perf_adj;
93f0822d 1172 int min_perf;
eae48f04 1173 struct perf_limits *perf_limits = limits;
845c1cbe 1174
51443fbf 1175 if (limits->no_turbo || limits->turbo_disabled)
93f0822d
DB		 1176 max_perf = cpu->pstate.max_pstate;
1177
eae48f04
SP		 1178 if (per_cpu_limits)
1179 perf_limits = cpu->perf_limits;
1180
e0d4c8f8
KCA		 1181 /*
1182 * performance can be limited by user through sysfs, by cpufreq
1183 * policy, or by cpu specific default values determined through
1184 * experimentation.
1185 */
eae48f04 1186 max_perf_adj = fp_toint(max_perf * perf_limits->max_perf);
799281a3
RW		 1187 *max = clamp_t(int, max_perf_adj,
1188 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
93f0822d 1189
eae48f04 1190 min_perf = fp_toint(max_perf * perf_limits->min_perf);
799281a3 1191 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
93f0822d
DB		 1192}
1193
a6c6ead1 1194static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1195{
bc95a454
RW		 1196 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1197 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1198 /*
1199 * Generally, there is no guarantee that this code will always run on
1200 * the CPU being updated, so force the register update to run on the
1201 * right CPU.
1202 */
1203 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1204 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1205}
1206
a6c6ead1
RW		 1207static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1208{
1209 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1210}
1211
1212static void intel_pstate_max_within_limits(struct cpudata *cpu)
1213{
1214 int min_pstate, max_pstate;
1215
1216 update_turbo_state();
1217 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1218 intel_pstate_set_pstate(cpu, max_pstate);
1219}
1220
93f0822d
DB		 1221static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1222{
016c8150
DB		 1223 cpu->pstate.min_pstate = pstate_funcs.get_min();
1224 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1225 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1226 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1227 cpu->pstate.scaling = pstate_funcs.get_scaling();
93f0822d 1228
007bea09
DB		 1229 if (pstate_funcs.get_vid)
1230 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1231
1232 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1233}
1234
a1c9787d 1235static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1236{
6b17ddb2 1237 struct sample *sample = &cpu->sample;
e66c1768 1238
a1c9787d 1239 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1240}
1241
4fec7ad5 1242static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1243{
93f0822d 1244 u64 aperf, mperf;
4ab60c3f 1245 unsigned long flags;
4055fad3 1246 u64 tsc;
93f0822d 1247
4ab60c3f 1248 local_irq_save(flags);
93f0822d
DB		 1249 rdmsrl(MSR_IA32_APERF, aperf);
1250 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1251 tsc = rdtsc();
4fec7ad5 1252 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1253 local_irq_restore(flags);
4fec7ad5 1254 return false;
8e601a9f 1255 }
4ab60c3f 1256 local_irq_restore(flags);
b69880f9 1257
c4ee841f 1258 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1259 cpu->sample.time = time;
d37e2b76
DB		 1260 cpu->sample.aperf = aperf;
1261 cpu->sample.mperf = mperf;
4055fad3 1262 cpu->sample.tsc = tsc;
d37e2b76
DB		 1263 cpu->sample.aperf -= cpu->prev_aperf;
1264 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1265 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1266
93f0822d
DB		 1267 cpu->prev_aperf = aperf;
1268 cpu->prev_mperf = mperf;
4055fad3 1269 cpu->prev_tsc = tsc;
febce40f
RW		 1270 /*
1271 * First time this function is invoked in a given cycle, all of the
1272 * previous sample data fields are equal to zero or stale and they must
1273 * be populated with meaningful numbers for things to work, so assume
1274 * that sample.time will always be reset before setting the utilization
1275 * update hook and make the caller skip the sample then.
1276 */
1277 return !!cpu->last_sample_time;
93f0822d
DB		 1278}
1279
8fa520af
PL		 1280static inline int32_t get_avg_frequency(struct cpudata *cpu)
1281{
a1c9787d
RW		 1282 return mul_ext_fp(cpu->sample.core_avg_perf,
1283 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
8fa520af
PL		 1284}
1285
bdcaa23f
PL		 1286static inline int32_t get_avg_pstate(struct cpudata *cpu)
1287{
8edb0a6e
RW		 1288 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1289 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1290}
1291
e70eed2b
PL		 1292static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1293{
1294 struct sample *sample = &cpu->sample;
09c448d3 1295 int32_t busy_frac, boost;
0843e83c 1296 int target, avg_pstate;
e70eed2b 1297
09c448d3 1298 busy_frac = div_fp(sample->mperf, sample->tsc);
63d1d656 1299
09c448d3
RW		 1300 boost = cpu->iowait_boost;
1301 cpu->iowait_boost >>= 1;
63d1d656 1302
09c448d3
RW		 1303 if (busy_frac < boost)
1304 busy_frac = boost;
63d1d656 1305
09c448d3 1306 sample->busy_scaled = busy_frac * 100;
0843e83c
RW		 1307
1308 target = limits->no_turbo || limits->turbo_disabled ?
1309 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1310 target += target >> 2;
1311 target = mul_fp(target, busy_frac);
1312 if (target < cpu->pstate.min_pstate)
1313 target = cpu->pstate.min_pstate;
1314
1315 /*
1316 * If the average P-state during the previous cycle was higher than the
1317 * current target, add 50% of the difference to the target to reduce
1318 * possible performance oscillations and offset possible performance
1319 * loss related to moving the workload from one CPU to another within
1320 * a package/module.
1321 */
1322 avg_pstate = get_avg_pstate(cpu);
1323 if (avg_pstate > target)
1324 target += (avg_pstate - target) >> 1;
1325
1326 return target;
e70eed2b
PL		 1327}
1328
157386b6 1329static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
93f0822d 1330{
1aa7a6e2 1331 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
a4675fbc 1332 u64 duration_ns;
93f0822d 1333
e0d4c8f8 1334 /*
f00593a4
RW		 1335 * perf_scaled is the ratio of the average P-state during the last
1336 * sampling period to the P-state requested last time (in percent).
1337 *
1338 * That measures the system's response to the previous P-state
1339 * selection.
e0d4c8f8 1340 */
22590efb
RW		 1341 max_pstate = cpu->pstate.max_pstate_physical;
1342 current_pstate = cpu->pstate.current_pstate;
1aa7a6e2 1343 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
a1c9787d 1344 div_fp(100 * max_pstate, current_pstate));
c4ee841f 1345
e0d4c8f8 1346 /*
a4675fbc
RW		 1347 * Since our utilization update callback will not run unless we are
1348 * in C0, check if the actual elapsed time is significantly greater (3x)
1349 * than our sample interval. If it is, then we were idle for a long
1aa7a6e2 1350 * enough period of time to adjust our performance metric.
e0d4c8f8 1351 */
a4675fbc 1352 duration_ns = cpu->sample.time - cpu->last_sample_time;
febce40f 1353 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
22590efb 1354 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1aa7a6e2 1355 perf_scaled = mul_fp(perf_scaled, sample_ratio);
ffb81056
RW		 1356 } else {
1357 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1358 if (sample_ratio < int_tofp(1))
1aa7a6e2 1359 perf_scaled = 0;
c4ee841f
DB		 1360 }
1361
1aa7a6e2
RW		 1362 cpu->sample.busy_scaled = perf_scaled;
1363 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
93f0822d
DB		 1364}
1365
fdfdb2b1
RW		 1366static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1367{
1368 int max_perf, min_perf;
1369
1370 update_turbo_state();
1371
1372 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1373 pstate = clamp_t(int, pstate, min_perf, max_perf);
bc95a454 1374 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1
RW		 1375 if (pstate == cpu->pstate.current_pstate)
1376 return;
1377
bc95a454 1378 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1379 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1380}
1381
93f0822d
DB		 1382static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1383{
157386b6 1384 int from, target_pstate;
4055fad3
DS		 1385 struct sample *sample;
1386
1387 from = cpu->pstate.current_pstate;
93f0822d 1388
2f1d407a
RW		 1389 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1390 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
93f0822d 1391
fdfdb2b1 1392 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1393
1394 sample = &cpu->sample;
a1c9787d 1395 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1396 fp_toint(sample->busy_scaled),
4055fad3
DS		 1397 from,
1398 cpu->pstate.current_pstate,
1399 sample->mperf,
1400 sample->aperf,
1401 sample->tsc,
3ba7bcaa
SP		 1402 get_avg_frequency(cpu),
1403 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1404}
1405
a4675fbc 1406static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1407 unsigned int flags)
93f0822d 1408{
a4675fbc 1409 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1410 u64 delta_ns;
1411
1d29815e 1412 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
09c448d3
RW		 1413 if (flags & SCHED_CPUFREQ_IOWAIT) {
1414 cpu->iowait_boost = int_tofp(1);
1415 } else if (cpu->iowait_boost) {
1416 /* Clear iowait_boost if the CPU may have been idle. */
1417 delta_ns = time - cpu->last_update;
1418 if (delta_ns > TICK_NSEC)
1419 cpu->iowait_boost = 0;
1420 }
1421 cpu->last_update = time;
1422 }
b69880f9 1423
09c448d3 1424 delta_ns = time - cpu->sample.time;
a4675fbc 1425 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
4fec7ad5
RW		 1426 bool sample_taken = intel_pstate_sample(cpu, time);
1427
6d45b719 1428 if (sample_taken) {
a1c9787d 1429 intel_pstate_calc_avg_perf(cpu);
6d45b719
RW		 1430 if (!hwp_active)
1431 intel_pstate_adjust_busy_pstate(cpu);
1432 }
a4675fbc 1433 }
93f0822d
DB		 1434}
1435
1436#define ICPU(model, policy) \
6cbd7ee1
DB		 1437 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1438 (unsigned long)&policy }
93f0822d
DB		 1439
1440static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
5b20c944
DH		 1441 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1442 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1443 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1444 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1445 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1446 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1447 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1448 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1449 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1450 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1451 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1452 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1453 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1454 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1455 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1456 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1457 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
41bad47f 1458 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
93f0822d
DB		 1459 {}
1460};
1461MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1462
29327c84 1463static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
5b20c944 1464 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
65c1262f
SP		 1465 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1466 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
2f86dc4c
DB		 1467 {}
1468};
1469
93f0822d
DB		 1470static int intel_pstate_init_cpu(unsigned int cpunum)
1471{
93f0822d
DB		 1472 struct cpudata *cpu;
1473
eae48f04
SP		 1474 cpu = all_cpu_data[cpunum];
1475
1476 if (!cpu) {
1477 unsigned int size = sizeof(struct cpudata);
1478
1479 if (per_cpu_limits)
1480 size += sizeof(struct perf_limits);
1481
1482 cpu = kzalloc(size, GFP_KERNEL);
1483 if (!cpu)
1484 return -ENOMEM;
1485
1486 all_cpu_data[cpunum] = cpu;
1487 if (per_cpu_limits)
1488 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1489
1490 }
93f0822d
DB		 1491
1492 cpu = all_cpu_data[cpunum];
1493
93f0822d 1494 cpu->cpu = cpunum;
ba88d433 1495
a4675fbc 1496 if (hwp_active) {
ba88d433 1497 intel_pstate_hwp_enable(cpu);
a4675fbc
RW		 1498 pid_params.sample_rate_ms = 50;
1499 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1500 }
ba88d433 1501
179e8471 1502 intel_pstate_get_cpu_pstates(cpu);
016c8150 1503
93f0822d 1504 intel_pstate_busy_pid_reset(cpu);
93f0822d 1505
4836df17 1506 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1507
1508 return 0;
1509}
1510
1511static unsigned int intel_pstate_get(unsigned int cpu_num)
1512{
f96fd0c8 1513 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 1514
f96fd0c8 1515 return cpu ? get_avg_frequency(cpu) : 0;
93f0822d
DB		 1516}
1517
febce40f 1518static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1519{
febce40f
RW		 1520 struct cpudata *cpu = all_cpu_data[cpu_num];
1521
5ab666e0
RW		 1522 if (cpu->update_util_set)
1523 return;
1524
febce40f
RW		 1525 /* Prevent intel_pstate_update_util() from using stale data. */
1526 cpu->sample.time = 0;
0bed612b
RW		 1527 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1528 intel_pstate_update_util);
4578ee7e 1529 cpu->update_util_set = true;
bb6ab52f
RW		 1530}
1531
1532static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1533{
4578ee7e
CY		 1534 struct cpudata *cpu_data = all_cpu_data[cpu];
1535
1536 if (!cpu_data->update_util_set)
1537 return;
1538
0bed612b 1539 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1540 cpu_data->update_util_set = false;
bb6ab52f
RW		 1541 synchronize_sched();
1542}
1543
30a39153
SP		 1544static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1545{
a410c03d 1546 mutex_lock(&intel_pstate_limits_lock);
30a39153
SP		 1547 limits->no_turbo = 0;
1548 limits->turbo_disabled = 0;
1549 limits->max_perf_pct = 100;
1550 limits->max_perf = int_tofp(1);
1551 limits->min_perf_pct = 100;
1552 limits->min_perf = int_tofp(1);
1553 limits->max_policy_pct = 100;
1554 limits->max_sysfs_pct = 100;
1555 limits->min_policy_pct = 0;
1556 limits->min_sysfs_pct = 0;
a410c03d 1557 mutex_unlock(&intel_pstate_limits_lock);
30a39153
SP		 1558}
1559
eae48f04
SP		 1560static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1561 struct perf_limits *limits)
1562{
a410c03d
SP		 1563
1564 mutex_lock(&intel_pstate_limits_lock);
1565
eae48f04
SP		 1566 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1567 policy->cpuinfo.max_freq);
1568 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
5879f877
SP		 1569 if (policy->max == policy->min) {
1570 limits->min_policy_pct = limits->max_policy_pct;
1571 } else {
1572 limits->min_policy_pct = (policy->min * 100) /
1573 policy->cpuinfo.max_freq;
1574 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1575 0, 100);
1576 }
eae48f04
SP		 1577
1578 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1579 limits->min_perf_pct = max(limits->min_policy_pct,
1580 limits->min_sysfs_pct);
1581 limits->min_perf_pct = min(limits->max_policy_pct,
1582 limits->min_perf_pct);
1583 limits->max_perf_pct = min(limits->max_policy_pct,
1584 limits->max_sysfs_pct);
1585 limits->max_perf_pct = max(limits->min_policy_pct,
1586 limits->max_perf_pct);
1587
1588 /* Make sure min_perf_pct <= max_perf_pct */
1589 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1590
1591 limits->min_perf = div_fp(limits->min_perf_pct, 100);
1592 limits->max_perf = div_fp(limits->max_perf_pct, 100);
1593 limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
1594
a410c03d
SP		 1595 mutex_unlock(&intel_pstate_limits_lock);
1596
eae48f04
SP		 1597 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
1598 limits->max_perf_pct, limits->min_perf_pct);
1599}
1600
93f0822d
DB		 1601static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1602{
3be9200d 1603 struct cpudata *cpu;
eae48f04 1604 struct perf_limits *perf_limits = NULL;
3be9200d 1605
d3929b83
DB		 1606 if (!policy->cpuinfo.max_freq)
1607 return -ENODEV;
1608
2c2c1af4
SP		 1609 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1610 policy->cpuinfo.max_freq, policy->max);
1611
a6c6ead1 1612 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 1613 cpu->policy = policy->policy;
1614
c749c64f
RW		 1615 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1616 policy->max < policy->cpuinfo.max_freq &&
1617 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1618 pr_debug("policy->max > max non turbo frequency\n");
1619 policy->max = policy->cpuinfo.max_freq;
3be9200d
SP		 1620 }
1621
eae48f04
SP		 1622 if (per_cpu_limits)
1623 perf_limits = cpu->perf_limits;
1624
1625 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1626 if (!perf_limits) {
1627 limits = &performance_limits;
1628 perf_limits = limits;
1629 }
30a39153 1630 if (policy->max >= policy->cpuinfo.max_freq) {
4836df17 1631 pr_debug("set performance\n");
eae48f04 1632 intel_pstate_set_performance_limits(perf_limits);
30a39153
SP		 1633 goto out;
1634 }
1635 } else {
4836df17 1636 pr_debug("set powersave\n");
eae48f04
SP		 1637 if (!perf_limits) {
1638 limits = &powersave_limits;
1639 perf_limits = limits;
1640 }
43717aad 1641
eae48f04 1642 }
93f0822d 1643
eae48f04 1644 intel_pstate_update_perf_limits(policy, perf_limits);
bb6ab52f 1645 out:
2f1d407a 1646 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 1647 /*
1648 * NOHZ_FULL CPUs need this as the governor callback may not
1649 * be invoked on them.
1650 */
1651 intel_pstate_clear_update_util_hook(policy->cpu);
1652 intel_pstate_max_within_limits(cpu);
1653 }
1654
bb6ab52f
RW		 1655 intel_pstate_set_update_util_hook(policy->cpu);
1656
ba41e1bc 1657 intel_pstate_hwp_set_policy(policy);
2f86dc4c 1658
93f0822d
DB		 1659 return 0;
1660}
1661
1662static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1663{
be49e346 1664 cpufreq_verify_within_cpu_limits(policy);
93f0822d 1665
285cb990 1666 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 1667 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 1668 return -EINVAL;
1669
1670 return 0;
1671}
1672
bb18008f 1673static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 1674{
bb18008f
DB		 1675 int cpu_num = policy->cpu;
1676 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 1677
4836df17 1678 pr_debug("CPU %d exiting\n", cpu_num);
bb18008f 1679
bb6ab52f 1680 intel_pstate_clear_update_util_hook(cpu_num);
a4675fbc 1681
2f86dc4c
DB		 1682 if (hwp_active)
1683 return;
1684
fdfdb2b1 1685 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1686}
1687
2760984f 1688static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 1689{
93f0822d 1690 struct cpudata *cpu;
52e0a509 1691 int rc;
93f0822d
DB		 1692
1693 rc = intel_pstate_init_cpu(policy->cpu);
1694 if (rc)
1695 return rc;
1696
1697 cpu = all_cpu_data[policy->cpu];
1698
51443fbf 1699 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
93f0822d
DB		 1700 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1701 else
1702 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1703
eae48f04
SP		 1704 /*
1705 * We need sane value in the cpu->perf_limits, so inherit from global
1706 * perf_limits limits, which are seeded with values based on the
1707 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
1708 */
1709 if (per_cpu_limits)
1710 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
1711
b27580b0
DB		 1712 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1713 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 1714
1715 /* cpuinfo and default policy values */
b27580b0 1716 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e
SP		 1717 update_turbo_state();
1718 policy->cpuinfo.max_freq = limits->turbo_disabled ?
1719 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1720 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1721
9522a2ff 1722 intel_pstate_init_acpi_perf_limits(policy);
93f0822d
DB		 1723 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1724 cpumask_set_cpu(policy->cpu, policy->cpus);
1725
1726 return 0;
1727}
1728
9522a2ff
SP		 1729static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1730{
1731 intel_pstate_exit_perf_limits(policy);
1732
1733 return 0;
1734}
1735
93f0822d
DB		 1736static struct cpufreq_driver intel_pstate_driver = {
1737 .flags = CPUFREQ_CONST_LOOPS,
1738 .verify = intel_pstate_verify_policy,
1739 .setpolicy = intel_pstate_set_policy,
ba41e1bc 1740 .resume = intel_pstate_hwp_set_policy,
93f0822d
DB		 1741 .get = intel_pstate_get,
1742 .init = intel_pstate_cpu_init,
9522a2ff 1743 .exit = intel_pstate_cpu_exit,
bb18008f 1744 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 1745 .name = "intel_pstate",
93f0822d
DB		 1746};
1747
eed43609
JZ		 1748static int no_load __initdata;
1749static int no_hwp __initdata;
1750static int hwp_only __initdata;
29327c84 1751static unsigned int force_load __initdata;
6be26498 1752
29327c84 1753static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 1754{
016c8150 1755 if (!pstate_funcs.get_max() ||
c410833a
SK		 1756 !pstate_funcs.get_min() ||
1757 !pstate_funcs.get_turbo())
b563b4e3
DB		 1758 return -ENODEV;
1759
b563b4e3
DB		 1760 return 0;
1761}
016c8150 1762
29327c84 1763static void __init copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB		 1764{
1765 pid_params.sample_rate_ms = policy->sample_rate_ms;
a4675fbc 1766 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
016c8150
DB		 1767 pid_params.p_gain_pct = policy->p_gain_pct;
1768 pid_params.i_gain_pct = policy->i_gain_pct;
1769 pid_params.d_gain_pct = policy->d_gain_pct;
1770 pid_params.deadband = policy->deadband;
1771 pid_params.setpoint = policy->setpoint;
1772}
1773
7f7a516e
SP		 1774#ifdef CONFIG_ACPI
1775static void intel_pstate_use_acpi_profile(void)
1776{
1777 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
1778 pstate_funcs.get_target_pstate =
1779 get_target_pstate_use_cpu_load;
1780}
1781#else
1782static void intel_pstate_use_acpi_profile(void)
1783{
1784}
1785#endif
1786
29327c84 1787static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 1788{
1789 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 1790 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 1791 pstate_funcs.get_min = funcs->get_min;
1792 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 1793 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 1794 pstate_funcs.get_val = funcs->get_val;
007bea09 1795 pstate_funcs.get_vid = funcs->get_vid;
157386b6
PL		 1796 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
1797
7f7a516e 1798 intel_pstate_use_acpi_profile();
016c8150
DB		 1799}
1800
9522a2ff 1801#ifdef CONFIG_ACPI
fbbcdc07 1802
29327c84 1803static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 1804{
1805 int i;
1806
1807 for_each_possible_cpu(i) {
1808 acpi_status status;
1809 union acpi_object *pss;
1810 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1811 struct acpi_processor *pr = per_cpu(processors, i);
1812
1813 if (!pr)
1814 continue;
1815
1816 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1817 if (ACPI_FAILURE(status))
1818 continue;
1819
1820 pss = buffer.pointer;
1821 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1822 kfree(pss);
1823 return false;
1824 }
1825
1826 kfree(pss);
1827 }
1828
1829 return true;
1830}
1831
29327c84 1832static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 1833{
1834 int i;
1835
1836 for_each_possible_cpu(i) {
1837 struct acpi_processor *pr = per_cpu(processors, i);
1838
1839 if (!pr)
1840 continue;
1841 if (acpi_has_method(pr->handle, "_PPC"))
1842 return true;
1843 }
1844 return false;
1845}
1846
1847enum {
1848 PSS,
1849 PPC,
1850};
1851
fbbcdc07
AH		 1852struct hw_vendor_info {
1853 u16 valid;
1854 char oem_id[ACPI_OEM_ID_SIZE];
1855 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
966916ea 1856 int oem_pwr_table;
fbbcdc07
AH		 1857};
1858
1859/* Hardware vendor-specific info that has its own power management modes */
29327c84 1860static struct hw_vendor_info vendor_info[] __initdata = {
966916ea 1861 {1, "HP ", "ProLiant", PSS},
1862 {1, "ORACLE", "X4-2 ", PPC},
1863 {1, "ORACLE", "X4-2L ", PPC},
1864 {1, "ORACLE", "X4-2B ", PPC},
1865 {1, "ORACLE", "X3-2 ", PPC},
1866 {1, "ORACLE", "X3-2L ", PPC},
1867 {1, "ORACLE", "X3-2B ", PPC},
1868 {1, "ORACLE", "X4470M2 ", PPC},
1869 {1, "ORACLE", "X4270M3 ", PPC},
1870 {1, "ORACLE", "X4270M2 ", PPC},
1871 {1, "ORACLE", "X4170M2 ", PPC},
5aecc3c8
EZ		 1872 {1, "ORACLE", "X4170 M3", PPC},
1873 {1, "ORACLE", "X4275 M3", PPC},
1874 {1, "ORACLE", "X6-2 ", PPC},
1875 {1, "ORACLE", "Sudbury ", PPC},
fbbcdc07
AH		 1876 {0, "", ""},
1877};
1878
29327c84 1879static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07
AH		 1880{
1881 struct acpi_table_header hdr;
1882 struct hw_vendor_info *v_info;
2f86dc4c
DB		 1883 const struct x86_cpu_id *id;
1884 u64 misc_pwr;
1885
1886 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1887 if (id) {
1888 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1889 if ( misc_pwr & (1 << 8))
1890 return true;
1891 }
fbbcdc07 1892
c410833a
SK		 1893 if (acpi_disabled ||
1894 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
fbbcdc07
AH		 1895 return false;
1896
1897 for (v_info = vendor_info; v_info->valid; v_info++) {
c410833a 1898 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
966916ea 1899 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1900 ACPI_OEM_TABLE_ID_SIZE))
1901 switch (v_info->oem_pwr_table) {
1902 case PSS:
1903 return intel_pstate_no_acpi_pss();
1904 case PPC:
aa4ea34d
EZ		 1905 return intel_pstate_has_acpi_ppc() &&
1906 (!force_load);
966916ea 1907 }
fbbcdc07
AH		 1908 }
1909
1910 return false;
1911}
1912#else /* CONFIG_ACPI not enabled */
1913static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 1914static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
fbbcdc07
AH		 1915#endif /* CONFIG_ACPI */
1916
7791e4aa
SP		 1917static const struct x86_cpu_id hwp_support_ids[] __initconst = {
1918 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
1919 {}
1920};
1921
93f0822d
DB		 1922static int __init intel_pstate_init(void)
1923{
907cc908 1924 int cpu, rc = 0;
93f0822d 1925 const struct x86_cpu_id *id;
64df1fdf 1926 struct cpu_defaults *cpu_def;
93f0822d 1927
6be26498
DB		 1928 if (no_load)
1929 return -ENODEV;
1930
7791e4aa
SP		 1931 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
1932 copy_cpu_funcs(&core_params.funcs);
1933 hwp_active++;
1934 goto hwp_cpu_matched;
1935 }
1936
93f0822d
DB		 1937 id = x86_match_cpu(intel_pstate_cpu_ids);
1938 if (!id)
1939 return -ENODEV;
1940
64df1fdf 1941 cpu_def = (struct cpu_defaults *)id->driver_data;
016c8150 1942
64df1fdf
BP		 1943 copy_pid_params(&cpu_def->pid_policy);
1944 copy_cpu_funcs(&cpu_def->funcs);
016c8150 1945
b563b4e3
DB		 1946 if (intel_pstate_msrs_not_valid())
1947 return -ENODEV;
1948
7791e4aa
SP		 1949hwp_cpu_matched:
1950 /*
1951 * The Intel pstate driver will be ignored if the platform
1952 * firmware has its own power management modes.
1953 */
1954 if (intel_pstate_platform_pwr_mgmt_exists())
1955 return -ENODEV;
1956
4836df17 1957 pr_info("Intel P-state driver initializing\n");
93f0822d 1958
b57ffac5 1959 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB		 1960 if (!all_cpu_data)
1961 return -ENOMEM;
93f0822d 1962
d64c3b0b
KCA		 1963 if (!hwp_active && hwp_only)
1964 goto out;
1965
93f0822d
DB		 1966 rc = cpufreq_register_driver(&intel_pstate_driver);
1967 if (rc)
1968 goto out;
1969
1970 intel_pstate_debug_expose_params();
1971 intel_pstate_sysfs_expose_params();
b69880f9 1972
7791e4aa 1973 if (hwp_active)
4836df17 1974 pr_info("HWP enabled\n");
7791e4aa 1975
93f0822d
DB		 1976 return rc;
1977out:
907cc908
DB		 1978 get_online_cpus();
1979 for_each_online_cpu(cpu) {
1980 if (all_cpu_data[cpu]) {
bb6ab52f 1981 intel_pstate_clear_update_util_hook(cpu);
907cc908
DB		 1982 kfree(all_cpu_data[cpu]);
1983 }
1984 }
1985
1986 put_online_cpus();
1987 vfree(all_cpu_data);
93f0822d
DB		 1988 return -ENODEV;
1989}
1990device_initcall(intel_pstate_init);
1991
6be26498
DB		 1992static int __init intel_pstate_setup(char *str)
1993{
1994 if (!str)
1995 return -EINVAL;
1996
1997 if (!strcmp(str, "disable"))
1998 no_load = 1;
539342f6 1999 if (!strcmp(str, "no_hwp")) {
4836df17 2000 pr_info("HWP disabled\n");
2f86dc4c 2001 no_hwp = 1;
539342f6 2002 }
aa4ea34d
EZ		 2003 if (!strcmp(str, "force"))
2004 force_load = 1;
d64c3b0b
KCA		 2005 if (!strcmp(str, "hwp_only"))
2006 hwp_only = 1;
eae48f04
SP		 2007 if (!strcmp(str, "per_cpu_perf_limits"))
2008 per_cpu_limits = true;
9522a2ff
SP		 2009
2010#ifdef CONFIG_ACPI
2011 if (!strcmp(str, "support_acpi_ppc"))
2012 acpi_ppc = true;
2013#endif
2014
6be26498
DB		 2015 return 0;
2016}
2017early_param("intel_pstate", intel_pstate_setup);
2018
93f0822d
DB		 2019MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2020MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2021MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)