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cpufreq: intel_pstate: Eliminate intel_pstate_get_base_pstate()
[linux-block.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
55687da1 22#include <linux/sched/cpufreq.h>
93f0822d
DB		 23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
fbbcdc07 29#include <linux/acpi.h>
d6472302 30#include <linux/vmalloc.h>
93f0822d
DB		 31#include <trace/events/power.h>
32
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
64df1fdf 36#include <asm/cpufeature.h>
5b20c944 37#include <asm/intel-family.h>
93f0822d 38
d77d4888 39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
eabd22c6 40
001c76f0 41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
1b72e7fd 42#define INTEL_CPUFREQ_TRANSITION_DELAY 500
001c76f0 43
9522a2ff
SP		 44#ifdef CONFIG_ACPI
45#include <acpi/processor.h>
17669006 46#include <acpi/cppc_acpi.h>
9522a2ff
SP		 47#endif
48
f0fe3cd7 49#define FRAC_BITS 8
93f0822d
DB		 50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 52
a1c9787d
RW		 53#define EXT_BITS 6
54#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 55#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 57
93f0822d
DB		 58static inline int32_t mul_fp(int32_t x, int32_t y)
59{
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61}
62
7180dddf 63static inline int32_t div_fp(s64 x, s64 y)
93f0822d 64{
7180dddf 65 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 66}
67
d022a65e
DB		 68static inline int ceiling_fp(int32_t x)
69{
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77}
78
ff35f02e
RW		 79static inline int32_t percent_fp(int percent)
80{
81 return div_fp(percent, 100);
82}
83
a1c9787d
RW		 84static inline u64 mul_ext_fp(u64 x, u64 y)
85{
86 return (x * y) >> EXT_FRAC_BITS;
87}
88
89static inline u64 div_ext_fp(u64 x, u64 y)
90{
91 return div64_u64(x << EXT_FRAC_BITS, y);
92}
93
e4c204ce
RW		 94static inline int32_t percent_ext_fp(int percent)
95{
96 return div_ext_fp(percent, 100);
97}
98
13ad7701
SP		 99/**
100 * struct sample - Store performance sample
a1c9787d 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 104 * P state. This can be different than core_avg_perf
13ad7701
SP		 105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
13ad7701
SP		 112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
93f0822d 117struct sample {
a1c9787d 118 int32_t core_avg_perf;
157386b6 119 int32_t busy_scaled;
93f0822d
DB		 120 u64 aperf;
121 u64 mperf;
4055fad3 122 u64 tsc;
a4675fbc 123 u64 time;
93f0822d
DB		 124};
125
13ad7701
SP		 126/**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
93f0822d
DB		 142struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
3bcc6fa9 146 int max_pstate_physical;
b27580b0 147 int scaling;
93f0822d 148 int turbo_pstate;
001c76f0
RW		 149 unsigned int max_freq;
150 unsigned int turbo_freq;
93f0822d
DB		 151};
152
13ad7701
SP		 153/**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
007bea09 166struct vid_data {
21855ff5
DB		 167 int min;
168 int max;
169 int turbo;
007bea09
DB		 170 int32_t ratio;
171};
172
c5a2ee7d
RW		 173/**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
183 * P-state capacity.
184 */
185struct global_params {
186 bool no_turbo;
187 bool turbo_disabled;
188 int max_perf_pct;
189 int min_perf_pct;
eae48f04
SP		 190};
191
13ad7701
SP		 192/**
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
2f1d407a 195 * @policy: CPUFreq policy value
13ad7701 196 * @update_util: CPUFreq utility callback information
4578ee7e 197 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
13ad7701
SP		 200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
13ad7701 202 * @last_sample_time: Last Sample time
6e34e1f2
SP		 203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
13ad7701
SP		 206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
1a4fe38a
SP		 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
9522a2ff
SP		 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
8442885f 219 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
e0efd5be
SP		 224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
52ccc431
SP		 226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
e0efd5be 228 * @hwp_boost_min: Last HWP boosted min performance
13ad7701
SP		 229 *
230 * This structure stores per CPU instance data for all CPUs.
231 */
93f0822d
DB		 232struct cpudata {
233 int cpu;
234
2f1d407a 235 unsigned int policy;
a4675fbc 236 struct update_util_data update_util;
4578ee7e 237 bool update_util_set;
93f0822d 238
93f0822d 239 struct pstate_data pstate;
007bea09 240 struct vid_data vid;
93f0822d 241
09c448d3 242 u64 last_update;
a4675fbc 243 u64 last_sample_time;
6e34e1f2 244 u64 aperf_mperf_shift;
93f0822d
DB		 245 u64 prev_aperf;
246 u64 prev_mperf;
4055fad3 247 u64 prev_tsc;
63d1d656 248 u64 prev_cummulative_iowait;
d37e2b76 249 struct sample sample;
1a4fe38a
SP		 250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
9522a2ff
SP		 252#ifdef CONFIG_ACPI
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
255#endif
09c448d3 256 unsigned int iowait_boost;
984edbdc 257 s16 epp_powersave;
8442885f 258 s16 epp_policy;
984edbdc
SP		 259 s16 epp_default;
260 s16 epp_saved;
e0efd5be
SP		 261 u64 hwp_req_cached;
262 u64 hwp_cap_cached;
52ccc431
SP		 263 u64 last_io_update;
264 unsigned int sched_flags;
e0efd5be 265 u32 hwp_boost_min;
93f0822d
DB		 266};
267
268static struct cpudata **all_cpu_data;
13ad7701 269
13ad7701
SP		 270/**
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
13ad7701
SP		 279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
016c8150
DB		 283struct pstate_funcs {
284 int (*get_max)(void);
3bcc6fa9 285 int (*get_max_physical)(void);
016c8150
DB		 286 int (*get_min)(void);
287 int (*get_turbo)(void);
b27580b0 288 int (*get_scaling)(void);
6e34e1f2 289 int (*get_aperf_mperf_shift)(void);
fdfdb2b1 290 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 291 void (*get_vid)(struct cpudata *);
93f0822d
DB		 292};
293
4a7cb7a9 294static struct pstate_funcs pstate_funcs __read_mostly;
5c439053 295
4a7cb7a9 296static int hwp_active __read_mostly;
ff7c9917 297static int hwp_mode_bdw __read_mostly;
eae48f04 298static bool per_cpu_limits __read_mostly;
e0efd5be 299static bool hwp_boost __read_mostly;
016c8150 300
ee8df89a 301static struct cpufreq_driver *intel_pstate_driver __read_mostly;
0c30b65b 302
9522a2ff
SP		 303#ifdef CONFIG_ACPI
304static bool acpi_ppc;
305#endif
13ad7701 306
c5a2ee7d 307static struct global_params global;
93f0822d 308
0c30b65b 309static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 310static DEFINE_MUTEX(intel_pstate_limits_lock);
311
9522a2ff 312#ifdef CONFIG_ACPI
2b3ec765 313
01e61a42 314static bool intel_pstate_acpi_pm_profile_server(void)
2b3ec765
SP		 315{
316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
318 return true;
319
01e61a42
SP		 320 return false;
321}
322
323static bool intel_pstate_get_ppc_enable_status(void)
324{
325 if (intel_pstate_acpi_pm_profile_server())
326 return true;
327
2b3ec765
SP		 328 return acpi_ppc;
329}
330
17669006
RW		 331#ifdef CONFIG_ACPI_CPPC_LIB
332
333/* The work item is needed to avoid CPU hotplug locking issues */
334static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
335{
336 sched_set_itmt_support();
337}
338
339static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
340
341static void intel_pstate_set_itmt_prio(int cpu)
342{
343 struct cppc_perf_caps cppc_perf;
344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
345 int ret;
346
347 ret = cppc_get_perf_caps(cpu, &cppc_perf);
348 if (ret)
349 return;
350
351 /*
352 * The priorities can be set regardless of whether or not
353 * sched_set_itmt_support(true) has been called and it is valid to
354 * update them at any time after it has been called.
355 */
356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
357
358 if (max_highest_perf <= min_highest_perf) {
359 if (cppc_perf.highest_perf > max_highest_perf)
360 max_highest_perf = cppc_perf.highest_perf;
361
362 if (cppc_perf.highest_perf < min_highest_perf)
363 min_highest_perf = cppc_perf.highest_perf;
364
365 if (max_highest_perf > min_highest_perf) {
366 /*
367 * This code can be run during CPU online under the
368 * CPU hotplug locks, so sched_set_itmt_support()
369 * cannot be called from here. Queue up a work item
370 * to invoke it.
371 */
372 schedule_work(&sched_itmt_work);
373 }
374 }
375}
86d333a8
SP		 376
377static int intel_pstate_get_cppc_guranteed(int cpu)
378{
379 struct cppc_perf_caps cppc_perf;
380 int ret;
381
382 ret = cppc_get_perf_caps(cpu, &cppc_perf);
383 if (ret)
384 return ret;
385
386 return cppc_perf.guaranteed_perf;
387}
388
5906056e 389#else /* CONFIG_ACPI_CPPC_LIB */
17669006
RW		 390static void intel_pstate_set_itmt_prio(int cpu)
391{
392}
5906056e 393#endif /* CONFIG_ACPI_CPPC_LIB */
17669006 394
9522a2ff
SP		 395static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
396{
397 struct cpudata *cpu;
9522a2ff
SP		 398 int ret;
399 int i;
400
17669006
RW		 401 if (hwp_active) {
402 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 403 return;
17669006 404 }
e59a8f7f 405
2b3ec765 406 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 407 return;
408
409 cpu = all_cpu_data[policy->cpu];
410
411 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
412 policy->cpu);
413 if (ret)
414 return;
415
416 /*
417 * Check if the control value in _PSS is for PERF_CTL MSR, which should
418 * guarantee that the states returned by it map to the states in our
419 * list directly.
420 */
421 if (cpu->acpi_perf_data.control_register.space_id !=
422 ACPI_ADR_SPACE_FIXED_HARDWARE)
423 goto err;
424
425 /*
426 * If there is only one entry _PSS, simply ignore _PSS and continue as
427 * usual without taking _PSS into account
428 */
429 if (cpu->acpi_perf_data.state_count < 2)
430 goto err;
431
432 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
433 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
434 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
435 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
436 (u32) cpu->acpi_perf_data.states[i].core_frequency,
437 (u32) cpu->acpi_perf_data.states[i].power,
438 (u32) cpu->acpi_perf_data.states[i].control);
439 }
440
441 /*
442 * The _PSS table doesn't contain whole turbo frequency range.
443 * This just contains +1 MHZ above the max non turbo frequency,
444 * with control value corresponding to max turbo ratio. But
445 * when cpufreq set policy is called, it will call with this
446 * max frequency, which will cause a reduced performance as
447 * this driver uses real max turbo frequency as the max
448 * frequency. So correct this frequency in _PSS table to
b00345d1 449 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 450 * Also need to convert to MHz as _PSS freq is in MHz.
451 */
7de32556 452 if (!global.turbo_disabled)
9522a2ff
SP		 453 cpu->acpi_perf_data.states[0].core_frequency =
454 policy->cpuinfo.max_freq / 1000;
455 cpu->valid_pss_table = true;
6cacd115 456 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 457
458 return;
459
460 err:
461 cpu->valid_pss_table = false;
462 acpi_processor_unregister_performance(policy->cpu);
463}
464
465static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
466{
467 struct cpudata *cpu;
468
469 cpu = all_cpu_data[policy->cpu];
470 if (!cpu->valid_pss_table)
471 return;
472
473 acpi_processor_unregister_performance(policy->cpu);
474}
5906056e 475#else /* CONFIG_ACPI */
7a3ba767 476static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 477{
478}
479
7a3ba767 480static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 481{
482}
01e61a42
SP		 483
484static inline bool intel_pstate_acpi_pm_profile_server(void)
485{
486 return false;
487}
5906056e
DB		 488#endif /* CONFIG_ACPI */
489
490#ifndef CONFIG_ACPI_CPPC_LIB
491static int intel_pstate_get_cppc_guranteed(int cpu)
492{
493 return -ENOTSUPP;
494}
495#endif /* CONFIG_ACPI_CPPC_LIB */
9522a2ff 496
4521e1a0
GM		 497static inline void update_turbo_state(void)
498{
499 u64 misc_en;
500 struct cpudata *cpu;
501
502 cpu = all_cpu_data[0];
503 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
7de32556 504 global.turbo_disabled =
4521e1a0
GM		 505 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
506 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
507}
508
c5a2ee7d
RW		 509static int min_perf_pct_min(void)
510{
511 struct cpudata *cpu = all_cpu_data[0];
57caf4ec 512 int turbo_pstate = cpu->pstate.turbo_pstate;
c5a2ee7d 513
57caf4ec 514 return turbo_pstate ?
d4436c0d 515 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
c5a2ee7d
RW		 516}
517
8442885f
SP		 518static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
519{
520 u64 epb;
521 int ret;
522
523 if (!static_cpu_has(X86_FEATURE_EPB))
524 return -ENXIO;
525
526 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
527 if (ret)
528 return (s16)ret;
529
530 return (s16)(epb & 0x0f);
531}
532
533static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
534{
535 s16 epp;
536
984edbdc
SP		 537 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
538 /*
539 * When hwp_req_data is 0, means that caller didn't read
540 * MSR_HWP_REQUEST, so need to read and get EPP.
541 */
542 if (!hwp_req_data) {
543 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
544 &hwp_req_data);
545 if (epp)
546 return epp;
547 }
8442885f 548 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 549 } else {
8442885f
SP		 550 /* When there is no EPP present, HWP uses EPB settings */
551 epp = intel_pstate_get_epb(cpu_data);
984edbdc 552 }
8442885f
SP		 553
554 return epp;
555}
556
984edbdc 557static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 558{
559 u64 epb;
984edbdc 560 int ret;
8442885f
SP		 561
562 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 563 return -ENXIO;
8442885f 564
984edbdc
SP		 565 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
566 if (ret)
567 return ret;
8442885f
SP		 568
569 epb = (epb & ~0x0f) | pref;
570 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 571
572 return 0;
8442885f
SP		 573}
574
984edbdc
SP		 575/*
576 * EPP/EPB display strings corresponding to EPP index in the
577 * energy_perf_strings[]
578 * index String
579 *-------------------------------------
580 * 0 default
581 * 1 performance
582 * 2 balance_performance
583 * 3 balance_power
584 * 4 power
585 */
586static const char * const energy_perf_strings[] = {
587 "default",
588 "performance",
589 "balance_performance",
590 "balance_power",
591 "power",
592 NULL
593};
3cedbc5a
LB		 594static const unsigned int epp_values[] = {
595 HWP_EPP_PERFORMANCE,
596 HWP_EPP_BALANCE_PERFORMANCE,
597 HWP_EPP_BALANCE_POWERSAVE,
598 HWP_EPP_POWERSAVE
599};
984edbdc
SP		 600
601static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
602{
603 s16 epp;
604 int index = -EINVAL;
605
606 epp = intel_pstate_get_epp(cpu_data, 0);
607 if (epp < 0)
608 return epp;
609
610 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
3cedbc5a
LB		 611 if (epp == HWP_EPP_PERFORMANCE)
612 return 1;
613 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
614 return 2;
615 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
616 return 3;
617 else
618 return 4;
984edbdc
SP		 619 } else if (static_cpu_has(X86_FEATURE_EPB)) {
620 /*
621 * Range:
622 * 0x00-0x03 : Performance
623 * 0x04-0x07 : Balance performance
624 * 0x08-0x0B : Balance power
625 * 0x0C-0x0F : Power
626 * The EPB is a 4 bit value, but our ranges restrict the
627 * value which can be set. Here only using top two bits
628 * effectively.
629 */
630 index = (epp >> 2) + 1;
631 }
632
633 return index;
634}
635
636static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
637 int pref_index)
638{
639 int epp = -EINVAL;
640 int ret;
641
642 if (!pref_index)
643 epp = cpu_data->epp_default;
644
645 mutex_lock(&intel_pstate_limits_lock);
646
647 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
648 u64 value;
649
650 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
651 if (ret)
652 goto return_pref;
653
654 value &= ~GENMASK_ULL(31, 24);
655
984edbdc 656 if (epp == -EINVAL)
3cedbc5a 657 epp = epp_values[pref_index - 1];
984edbdc
SP		 658
659 value |= (u64)epp << 24;
660 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
661 } else {
662 if (epp == -EINVAL)
663 epp = (pref_index - 1) << 2;
664 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
665 }
666return_pref:
667 mutex_unlock(&intel_pstate_limits_lock);
668
669 return ret;
670}
671
672static ssize_t show_energy_performance_available_preferences(
673 struct cpufreq_policy *policy, char *buf)
674{
675 int i = 0;
676 int ret = 0;
677
678 while (energy_perf_strings[i] != NULL)
679 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
680
681 ret += sprintf(&buf[ret], "\n");
682
683 return ret;
684}
685
686cpufreq_freq_attr_ro(energy_performance_available_preferences);
687
688static ssize_t store_energy_performance_preference(
689 struct cpufreq_policy *policy, const char *buf, size_t count)
690{
691 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
692 char str_preference[21];
1111b783 693 int ret;
984edbdc
SP		 694
695 ret = sscanf(buf, "%20s", str_preference);
696 if (ret != 1)
697 return -EINVAL;
698
1111b783
XY		 699 ret = match_string(energy_perf_strings, -1, str_preference);
700 if (ret < 0)
701 return ret;
984edbdc 702
1111b783
XY		 703 intel_pstate_set_energy_pref_index(cpu_data, ret);
704 return count;
984edbdc
SP		 705}
706
707static ssize_t show_energy_performance_preference(
708 struct cpufreq_policy *policy, char *buf)
709{
710 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
711 int preference;
712
713 preference = intel_pstate_get_energy_pref_index(cpu_data);
714 if (preference < 0)
715 return preference;
716
717 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
718}
719
720cpufreq_freq_attr_rw(energy_performance_preference);
721
86d333a8
SP		 722static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
723{
724 struct cpudata *cpu;
725 u64 cap;
726 int ratio;
727
728 ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
729 if (ratio <= 0) {
730 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
731 ratio = HWP_GUARANTEED_PERF(cap);
732 }
733
734 cpu = all_cpu_data[policy->cpu];
735
736 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
737}
738
739cpufreq_freq_attr_ro(base_frequency);
740
984edbdc
SP		 741static struct freq_attr *hwp_cpufreq_attrs[] = {
742 &energy_performance_preference,
743 &energy_performance_available_preferences,
86d333a8 744 &base_frequency,
984edbdc
SP		 745 NULL,
746};
747
1a4fe38a
SP		 748static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
749 int *current_max)
2f86dc4c 750{
1a4fe38a 751 u64 cap;
74da56ce 752
2bfc4cbb 753 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
e0efd5be 754 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
2bfc4cbb 755 if (global.no_turbo)
1a4fe38a 756 *current_max = HWP_GUARANTEED_PERF(cap);
2bfc4cbb 757 else
1a4fe38a
SP		 758 *current_max = HWP_HIGHEST_PERF(cap);
759
760 *phy_max = HWP_HIGHEST_PERF(cap);
761}
762
763static void intel_pstate_hwp_set(unsigned int cpu)
764{
765 struct cpudata *cpu_data = all_cpu_data[cpu];
766 int max, min;
767 u64 value;
768 s16 epp;
769
770 max = cpu_data->max_perf_ratio;
771 min = cpu_data->min_perf_ratio;
eae48f04 772
2bfc4cbb
RW		 773 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
774 min = max;
3f8ed54a 775
2bfc4cbb 776 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
2f86dc4c 777
2bfc4cbb
RW		 778 value &= ~HWP_MIN_PERF(~0L);
779 value |= HWP_MIN_PERF(min);
8442885f 780
2bfc4cbb
RW		 781 value &= ~HWP_MAX_PERF(~0L);
782 value |= HWP_MAX_PERF(max);
8442885f 783
2bfc4cbb
RW		 784 if (cpu_data->epp_policy == cpu_data->policy)
785 goto skip_epp;
8442885f 786
2bfc4cbb 787 cpu_data->epp_policy = cpu_data->policy;
984edbdc 788
2bfc4cbb
RW		 789 if (cpu_data->epp_saved >= 0) {
790 epp = cpu_data->epp_saved;
791 cpu_data->epp_saved = -EINVAL;
792 goto update_epp;
793 }
8442885f 794
2bfc4cbb
RW		 795 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
796 epp = intel_pstate_get_epp(cpu_data, value);
797 cpu_data->epp_powersave = epp;
798 /* If EPP read was failed, then don't try to write */
799 if (epp < 0)
800 goto skip_epp;
8442885f 801
2bfc4cbb
RW		 802 epp = 0;
803 } else {
804 /* skip setting EPP, when saved value is invalid */
805 if (cpu_data->epp_powersave < 0)
806 goto skip_epp;
8442885f 807
2bfc4cbb
RW		 808 /*
809 * No need to restore EPP when it is not zero. This
810 * means:
811 * - Policy is not changed
812 * - user has manually changed
813 * - Error reading EPB
814 */
815 epp = intel_pstate_get_epp(cpu_data, value);
816 if (epp)
817 goto skip_epp;
8442885f 818
2bfc4cbb
RW		 819 epp = cpu_data->epp_powersave;
820 }
984edbdc 821update_epp:
2bfc4cbb
RW		 822 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
823 value &= ~GENMASK_ULL(31, 24);
824 value |= (u64)epp << 24;
825 } else {
826 intel_pstate_set_epb(cpu, epp);
2f86dc4c 827 }
2bfc4cbb 828skip_epp:
e0efd5be 829 WRITE_ONCE(cpu_data->hwp_req_cached, value);
2bfc4cbb 830 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
41cfd64c 831}
2f86dc4c 832
af3b7379
SP		 833static void intel_pstate_hwp_force_min_perf(int cpu)
834{
835 u64 value;
836 int min_perf;
837
838 value = all_cpu_data[cpu]->hwp_req_cached;
839 value &= ~GENMASK_ULL(31, 0);
840 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
841
842 /* Set hwp_max = hwp_min */
843 value |= HWP_MAX_PERF(min_perf);
844 value |= HWP_MIN_PERF(min_perf);
845
846 /* Set EPP/EPB to min */
847 if (static_cpu_has(X86_FEATURE_HWP_EPP))
848 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
849 else
850 intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
851
852 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
853}
854
984edbdc
SP		 855static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
856{
857 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
858
859 if (!hwp_active)
860 return 0;
861
862 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
863
864 return 0;
865}
866
70f6bf2a
CY		 867static void intel_pstate_hwp_enable(struct cpudata *cpudata);
868
8442885f
SP		 869static int intel_pstate_resume(struct cpufreq_policy *policy)
870{
871 if (!hwp_active)
872 return 0;
873
aa439248
RW		 874 mutex_lock(&intel_pstate_limits_lock);
875
70f6bf2a
CY		 876 if (policy->cpu == 0)
877 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
878
8442885f 879 all_cpu_data[policy->cpu]->epp_policy = 0;
2bfc4cbb 880 intel_pstate_hwp_set(policy->cpu);
aa439248
RW		 881
882 mutex_unlock(&intel_pstate_limits_lock);
883
5f98ced1 884 return 0;
8442885f
SP		 885}
886
111b8b3f 887static void intel_pstate_update_policies(void)
41cfd64c 888{
111b8b3f
RW		 889 int cpu;
890
891 for_each_possible_cpu(cpu)
892 cpufreq_update_policy(cpu);
2f86dc4c
DB		 893}
894
93f0822d
DB		 895/************************** sysfs begin ************************/
896#define show_one(file_name, object) \
897 static ssize_t show_##file_name \
625c85a6 898 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
93f0822d 899 { \
7de32556 900 return sprintf(buf, "%u\n", global.object); \
93f0822d
DB		 901 }
902
fb1fe104
RW		 903static ssize_t intel_pstate_show_status(char *buf);
904static int intel_pstate_update_status(const char *buf, size_t size);
905
906static ssize_t show_status(struct kobject *kobj,
625c85a6 907 struct kobj_attribute *attr, char *buf)
fb1fe104
RW		 908{
909 ssize_t ret;
910
911 mutex_lock(&intel_pstate_driver_lock);
912 ret = intel_pstate_show_status(buf);
913 mutex_unlock(&intel_pstate_driver_lock);
914
915 return ret;
916}
917
625c85a6 918static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
fb1fe104
RW		 919 const char *buf, size_t count)
920{
921 char *p = memchr(buf, '\n', count);
922 int ret;
923
924 mutex_lock(&intel_pstate_driver_lock);
925 ret = intel_pstate_update_status(buf, p ? p - buf : count);
926 mutex_unlock(&intel_pstate_driver_lock);
927
928 return ret < 0 ? ret : count;
929}
930
d01b1f48 931static ssize_t show_turbo_pct(struct kobject *kobj,
625c85a6 932 struct kobj_attribute *attr, char *buf)
d01b1f48
KCA		 933{
934 struct cpudata *cpu;
935 int total, no_turbo, turbo_pct;
936 uint32_t turbo_fp;
937
0c30b65b
RW		 938 mutex_lock(&intel_pstate_driver_lock);
939
ee8df89a 940 if (!intel_pstate_driver) {
0c30b65b
RW		 941 mutex_unlock(&intel_pstate_driver_lock);
942 return -EAGAIN;
943 }
944
d01b1f48
KCA		 945 cpu = all_cpu_data[0];
946
947 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
948 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 949 turbo_fp = div_fp(no_turbo, total);
d01b1f48 950 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 951
952 mutex_unlock(&intel_pstate_driver_lock);
953
d01b1f48
KCA		 954 return sprintf(buf, "%u\n", turbo_pct);
955}
956
0522424e 957static ssize_t show_num_pstates(struct kobject *kobj,
625c85a6 958 struct kobj_attribute *attr, char *buf)
0522424e
KCA		 959{
960 struct cpudata *cpu;
961 int total;
962
0c30b65b
RW		 963 mutex_lock(&intel_pstate_driver_lock);
964
ee8df89a 965 if (!intel_pstate_driver) {
0c30b65b
RW		 966 mutex_unlock(&intel_pstate_driver_lock);
967 return -EAGAIN;
968 }
969
0522424e
KCA		 970 cpu = all_cpu_data[0];
971 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 972
973 mutex_unlock(&intel_pstate_driver_lock);
974
0522424e
KCA		 975 return sprintf(buf, "%u\n", total);
976}
977
4521e1a0 978static ssize_t show_no_turbo(struct kobject *kobj,
625c85a6 979 struct kobj_attribute *attr, char *buf)
4521e1a0
GM		 980{
981 ssize_t ret;
982
0c30b65b
RW		 983 mutex_lock(&intel_pstate_driver_lock);
984
ee8df89a 985 if (!intel_pstate_driver) {
0c30b65b
RW		 986 mutex_unlock(&intel_pstate_driver_lock);
987 return -EAGAIN;
988 }
989
4521e1a0 990 update_turbo_state();
7de32556
RW		 991 if (global.turbo_disabled)
992 ret = sprintf(buf, "%u\n", global.turbo_disabled);
4521e1a0 993 else
7de32556 994 ret = sprintf(buf, "%u\n", global.no_turbo);
4521e1a0 995
0c30b65b
RW		 996 mutex_unlock(&intel_pstate_driver_lock);
997
4521e1a0
GM		 998 return ret;
999}
1000
625c85a6 1001static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
c410833a 1002 const char *buf, size_t count)
93f0822d
DB		 1003{
1004 unsigned int input;
1005 int ret;
845c1cbe 1006
93f0822d
DB		 1007 ret = sscanf(buf, "%u", &input);
1008 if (ret != 1)
1009 return -EINVAL;
4521e1a0 1010
0c30b65b
RW		 1011 mutex_lock(&intel_pstate_driver_lock);
1012
ee8df89a 1013 if (!intel_pstate_driver) {
0c30b65b
RW		 1014 mutex_unlock(&intel_pstate_driver_lock);
1015 return -EAGAIN;
1016 }
1017
a410c03d
SP		 1018 mutex_lock(&intel_pstate_limits_lock);
1019
4521e1a0 1020 update_turbo_state();
7de32556 1021 if (global.turbo_disabled) {
4836df17 1022 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 1023 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 1024 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 1025 return -EPERM;
dd5fbf70 1026 }
2f86dc4c 1027
7de32556 1028 global.no_turbo = clamp_t(int, input, 0, 1);
111b8b3f 1029
c5a2ee7d
RW		 1030 if (global.no_turbo) {
1031 struct cpudata *cpu = all_cpu_data[0];
1032 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1033
1034 /* Squash the global minimum into the permitted range. */
1035 if (global.min_perf_pct > pct)
1036 global.min_perf_pct = pct;
1037 }
1038
cd59b4be
RW		 1039 mutex_unlock(&intel_pstate_limits_lock);
1040
7de32556
RW		 1041 intel_pstate_update_policies();
1042
0c30b65b
RW		 1043 mutex_unlock(&intel_pstate_driver_lock);
1044
93f0822d
DB		 1045 return count;
1046}
1047
625c85a6 1048static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
c410833a 1049 const char *buf, size_t count)
93f0822d
DB		 1050{
1051 unsigned int input;
1052 int ret;
845c1cbe 1053
93f0822d
DB		 1054 ret = sscanf(buf, "%u", &input);
1055 if (ret != 1)
1056 return -EINVAL;
1057
0c30b65b
RW		 1058 mutex_lock(&intel_pstate_driver_lock);
1059
ee8df89a 1060 if (!intel_pstate_driver) {
0c30b65b
RW		 1061 mutex_unlock(&intel_pstate_driver_lock);
1062 return -EAGAIN;
1063 }
1064
a410c03d
SP		 1065 mutex_lock(&intel_pstate_limits_lock);
1066
c5a2ee7d 1067 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
111b8b3f 1068
cd59b4be
RW		 1069 mutex_unlock(&intel_pstate_limits_lock);
1070
7de32556
RW		 1071 intel_pstate_update_policies();
1072
0c30b65b
RW		 1073 mutex_unlock(&intel_pstate_driver_lock);
1074
93f0822d
DB		 1075 return count;
1076}
1077
625c85a6 1078static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
c410833a 1079 const char *buf, size_t count)
93f0822d
DB		 1080{
1081 unsigned int input;
1082 int ret;
845c1cbe 1083
93f0822d
DB		 1084 ret = sscanf(buf, "%u", &input);
1085 if (ret != 1)
1086 return -EINVAL;
a0475992 1087
0c30b65b
RW		 1088 mutex_lock(&intel_pstate_driver_lock);
1089
ee8df89a 1090 if (!intel_pstate_driver) {
0c30b65b
RW		 1091 mutex_unlock(&intel_pstate_driver_lock);
1092 return -EAGAIN;
1093 }
1094
a410c03d
SP		 1095 mutex_lock(&intel_pstate_limits_lock);
1096
c5a2ee7d
RW		 1097 global.min_perf_pct = clamp_t(int, input,
1098 min_perf_pct_min(), global.max_perf_pct);
111b8b3f 1099
cd59b4be
RW		 1100 mutex_unlock(&intel_pstate_limits_lock);
1101
7de32556
RW		 1102 intel_pstate_update_policies();
1103
0c30b65b
RW		 1104 mutex_unlock(&intel_pstate_driver_lock);
1105
93f0822d
DB		 1106 return count;
1107}
1108
aaaece3d 1109static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
625c85a6 1110 struct kobj_attribute *attr, char *buf)
aaaece3d
SP		 1111{
1112 return sprintf(buf, "%u\n", hwp_boost);
1113}
1114
625c85a6
VK		 1115static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1116 struct kobj_attribute *b,
aaaece3d
SP		 1117 const char *buf, size_t count)
1118{
1119 unsigned int input;
1120 int ret;
1121
1122 ret = kstrtouint(buf, 10, &input);
1123 if (ret)
1124 return ret;
1125
1126 mutex_lock(&intel_pstate_driver_lock);
1127 hwp_boost = !!input;
1128 intel_pstate_update_policies();
1129 mutex_unlock(&intel_pstate_driver_lock);
1130
1131 return count;
1132}
1133
93f0822d
DB		 1134show_one(max_perf_pct, max_perf_pct);
1135show_one(min_perf_pct, min_perf_pct);
1136
fb1fe104 1137define_one_global_rw(status);
93f0822d
DB		 1138define_one_global_rw(no_turbo);
1139define_one_global_rw(max_perf_pct);
1140define_one_global_rw(min_perf_pct);
d01b1f48 1141define_one_global_ro(turbo_pct);
0522424e 1142define_one_global_ro(num_pstates);
aaaece3d 1143define_one_global_rw(hwp_dynamic_boost);
93f0822d
DB		 1144
1145static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1146 &status.attr,
93f0822d 1147 &no_turbo.attr,
d01b1f48 1148 &turbo_pct.attr,
0522424e 1149 &num_pstates.attr,
93f0822d
DB		 1150 NULL
1151};
1152
106c9c77 1153static const struct attribute_group intel_pstate_attr_group = {
93f0822d
DB		 1154 .attrs = intel_pstate_attributes,
1155};
93f0822d 1156
317dd50e 1157static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1158{
317dd50e 1159 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1160 int rc;
1161
1162 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1163 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1164 if (WARN_ON(!intel_pstate_kobject))
1165 return;
1166
2d8d1f18 1167 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1168 if (WARN_ON(rc))
1169 return;
1170
1171 /*
1172 * If per cpu limits are enforced there are no global limits, so
1173 * return without creating max/min_perf_pct attributes
1174 */
1175 if (per_cpu_limits)
1176 return;
1177
1178 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1179 WARN_ON(rc);
1180
1181 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1182 WARN_ON(rc);
1183
aaaece3d
SP		 1184 if (hwp_active) {
1185 rc = sysfs_create_file(intel_pstate_kobject,
1186 &hwp_dynamic_boost.attr);
1187 WARN_ON(rc);
1188 }
93f0822d 1189}
93f0822d 1190/************************** sysfs end ************************/
2f86dc4c 1191
ba88d433 1192static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1193{
f05c9665 1194 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1195 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1196 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1197
ba88d433 1198 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1199 cpudata->epp_policy = 0;
984edbdc
SP		 1200 if (cpudata->epp_default == -EINVAL)
1201 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1202}
1203
6e978b22
SP		 1204#define MSR_IA32_POWER_CTL_BIT_EE 19
1205
1206/* Disable energy efficiency optimization */
1207static void intel_pstate_disable_ee(int cpu)
1208{
1209 u64 power_ctl;
1210 int ret;
1211
1212 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1213 if (ret)
1214 return;
1215
1216 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1217 pr_info("Disabling energy efficiency optimization\n");
1218 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1219 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1220 }
1221}
1222
938d21a2 1223static int atom_get_min_pstate(void)
19e77c28
DB		 1224{
1225 u64 value;
845c1cbe 1226
92134bdb 1227 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1228 return (value >> 8) & 0x7F;
19e77c28
DB		 1229}
1230
938d21a2 1231static int atom_get_max_pstate(void)
19e77c28
DB		 1232{
1233 u64 value;
845c1cbe 1234
92134bdb 1235 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1236 return (value >> 16) & 0x7F;
19e77c28 1237}
93f0822d 1238
938d21a2 1239static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1240{
1241 u64 value;
845c1cbe 1242
92134bdb 1243 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1244 return value & 0x7F;
61d8d2ab
DB		 1245}
1246
fdfdb2b1 1247static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1248{
1249 u64 val;
1250 int32_t vid_fp;
1251 u32 vid;
1252
144c8e17 1253 val = (u64)pstate << 8;
7de32556 1254 if (global.no_turbo && !global.turbo_disabled)
007bea09
DB		 1255 val |= (u64)1 << 32;
1256
1257 vid_fp = cpudata->vid.min + mul_fp(
1258 int_tofp(pstate - cpudata->pstate.min_pstate),
1259 cpudata->vid.ratio);
1260
1261 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1262 vid = ceiling_fp(vid_fp);
007bea09 1263
21855ff5
DB		 1264 if (pstate > cpudata->pstate.max_pstate)
1265 vid = cpudata->vid.turbo;
1266
fdfdb2b1 1267 return val | vid;
007bea09
DB		 1268}
1269
1421df63 1270static int silvermont_get_scaling(void)
b27580b0
DB		 1271{
1272 u64 value;
1273 int i;
1421df63
PL		 1274 /* Defined in Table 35-6 from SDM (Sept 2015) */
1275 static int silvermont_freq_table[] = {
1276 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1277
1278 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1279 i = value & 0x7;
1280 WARN_ON(i > 4);
b27580b0 1281
1421df63
PL		 1282 return silvermont_freq_table[i];
1283}
b27580b0 1284
1421df63
PL		 1285static int airmont_get_scaling(void)
1286{
1287 u64 value;
1288 int i;
1289 /* Defined in Table 35-10 from SDM (Sept 2015) */
1290 static int airmont_freq_table[] = {
1291 83300, 100000, 133300, 116700, 80000,
1292 93300, 90000, 88900, 87500};
1293
1294 rdmsrl(MSR_FSB_FREQ, value);
1295 i = value & 0xF;
1296 WARN_ON(i > 8);
1297
1298 return airmont_freq_table[i];
b27580b0
DB		 1299}
1300
938d21a2 1301static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1302{
1303 u64 value;
1304
92134bdb 1305 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1306 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1307 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1308 cpudata->vid.ratio = div_fp(
1309 cpudata->vid.max - cpudata->vid.min,
1310 int_tofp(cpudata->pstate.max_pstate -
1311 cpudata->pstate.min_pstate));
21855ff5 1312
92134bdb 1313 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1314 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1315}
1316
016c8150 1317static int core_get_min_pstate(void)
93f0822d
DB		 1318{
1319 u64 value;
845c1cbe 1320
05e99c8c 1321 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1322 return (value >> 40) & 0xFF;
1323}
1324
3bcc6fa9 1325static int core_get_max_pstate_physical(void)
93f0822d
DB		 1326{
1327 u64 value;
845c1cbe 1328
05e99c8c 1329 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1330 return (value >> 8) & 0xFF;
1331}
1332
8fc7554a
SP		 1333static int core_get_tdp_ratio(u64 plat_info)
1334{
1335 /* Check how many TDP levels present */
1336 if (plat_info & 0x600000000) {
1337 u64 tdp_ctrl;
1338 u64 tdp_ratio;
1339 int tdp_msr;
1340 int err;
1341
1342 /* Get the TDP level (0, 1, 2) to get ratios */
1343 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1344 if (err)
1345 return err;
1346
1347 /* TDP MSR are continuous starting at 0x648 */
1348 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1349 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1350 if (err)
1351 return err;
1352
1353 /* For level 1 and 2, bits[23:16] contain the ratio */
1354 if (tdp_ctrl & 0x03)
1355 tdp_ratio >>= 16;
1356
1357 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1358 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1359
1360 return (int)tdp_ratio;
1361 }
1362
1363 return -ENXIO;
1364}
1365
016c8150 1366static int core_get_max_pstate(void)
93f0822d 1367{
6a35fc2d
SP		 1368 u64 tar;
1369 u64 plat_info;
1370 int max_pstate;
8fc7554a 1371 int tdp_ratio;
6a35fc2d
SP		 1372 int err;
1373
1374 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1375 max_pstate = (plat_info >> 8) & 0xFF;
1376
8fc7554a
SP		 1377 tdp_ratio = core_get_tdp_ratio(plat_info);
1378 if (tdp_ratio <= 0)
1379 return max_pstate;
1380
1381 if (hwp_active) {
1382 /* Turbo activation ratio is not used on HWP platforms */
1383 return tdp_ratio;
1384 }
1385
6a35fc2d
SP		 1386 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1387 if (!err) {
8fc7554a
SP		 1388 int tar_levels;
1389
6a35fc2d 1390 /* Do some sanity checking for safety */
8fc7554a
SP		 1391 tar_levels = tar & 0xff;
1392 if (tdp_ratio - 1 == tar_levels) {
1393 max_pstate = tar_levels;
1394 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1395 }
1396 }
845c1cbe 1397
6a35fc2d 1398 return max_pstate;
93f0822d
DB		 1399}
1400
016c8150 1401static int core_get_turbo_pstate(void)
93f0822d
DB		 1402{
1403 u64 value;
1404 int nont, ret;
845c1cbe 1405
100cf6f2 1406 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1407 nont = core_get_max_pstate();
285cb990 1408 ret = (value) & 255;
93f0822d
DB		 1409 if (ret <= nont)
1410 ret = nont;
1411 return ret;
1412}
1413
b27580b0
DB		 1414static inline int core_get_scaling(void)
1415{
1416 return 100000;
1417}
1418
fdfdb2b1 1419static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1420{
1421 u64 val;
1422
144c8e17 1423 val = (u64)pstate << 8;
7de32556 1424 if (global.no_turbo && !global.turbo_disabled)
016c8150
DB		 1425 val |= (u64)1 << 32;
1426
fdfdb2b1 1427 return val;
016c8150
DB		 1428}
1429
6e34e1f2
SP		 1430static int knl_get_aperf_mperf_shift(void)
1431{
1432 return 10;
1433}
1434
b34ef932
DC		 1435static int knl_get_turbo_pstate(void)
1436{
1437 u64 value;
1438 int nont, ret;
1439
100cf6f2 1440 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1441 nont = core_get_max_pstate();
1442 ret = (((value) >> 8) & 0xFF);
1443 if (ret <= nont)
1444 ret = nont;
1445 return ret;
1446}
1447
a6c6ead1 1448static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1449{
bc95a454
RW		 1450 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1451 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1452 /*
1453 * Generally, there is no guarantee that this code will always run on
1454 * the CPU being updated, so force the register update to run on the
1455 * right CPU.
1456 */
1457 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1458 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1459}
1460
a6c6ead1
RW		 1461static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1462{
1463 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1464}
1465
1466static void intel_pstate_max_within_limits(struct cpudata *cpu)
1467{
fa93b51c 1468 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
a6c6ead1
RW		 1469
1470 update_turbo_state();
b02aabe8 1471 intel_pstate_set_pstate(cpu, pstate);
a6c6ead1
RW		 1472}
1473
93f0822d
DB		 1474static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1475{
016c8150
DB		 1476 cpu->pstate.min_pstate = pstate_funcs.get_min();
1477 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1478 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1479 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1480 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0 1481 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
ff7c9917
SP		 1482
1483 if (hwp_active && !hwp_mode_bdw) {
1484 unsigned int phy_max, current_max;
1485
1486 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1487 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1488 } else {
1489 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1490 }
93f0822d 1491
6e34e1f2
SP		 1492 if (pstate_funcs.get_aperf_mperf_shift)
1493 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1494
007bea09
DB		 1495 if (pstate_funcs.get_vid)
1496 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1497
1498 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1499}
1500
e0efd5be
SP		 1501/*
1502 * Long hold time will keep high perf limits for long time,
1503 * which negatively impacts perf/watt for some workloads,
1504 * like specpower. 3ms is based on experiements on some
1505 * workoads.
1506 */
1507static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1508
1509static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1510{
1511 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1512 u32 max_limit = (hwp_req & 0xff00) >> 8;
1513 u32 min_limit = (hwp_req & 0xff);
1514 u32 boost_level1;
1515
1516 /*
1517 * Cases to consider (User changes via sysfs or boot time):
1518 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1519 * No boost, return.
1520 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1521 * Should result in one level boost only for P0.
1522 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1523 * Should result in two level boost:
1524 * (min + p1)/2 and P1.
1525 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1526 * Should result in three level boost:
1527 * (min + p1)/2, P1 and P0.
1528 */
1529
1530 /* If max and min are equal or already at max, nothing to boost */
1531 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1532 return;
1533
1534 if (!cpu->hwp_boost_min)
1535 cpu->hwp_boost_min = min_limit;
1536
1537 /* level at half way mark between min and guranteed */
1538 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1539
1540 if (cpu->hwp_boost_min < boost_level1)
1541 cpu->hwp_boost_min = boost_level1;
1542 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1543 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1544 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1545 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1546 cpu->hwp_boost_min = max_limit;
1547 else
1548 return;
1549
1550 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1551 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1552 cpu->last_update = cpu->sample.time;
1553}
1554
1555static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1556{
1557 if (cpu->hwp_boost_min) {
1558 bool expired;
1559
1560 /* Check if we are idle for hold time to boost down */
1561 expired = time_after64(cpu->sample.time, cpu->last_update +
1562 hwp_boost_hold_time_ns);
1563 if (expired) {
1564 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1565 cpu->hwp_boost_min = 0;
1566 }
1567 }
1568 cpu->last_update = cpu->sample.time;
1569}
1570
52ccc431
SP		 1571static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1572 u64 time)
1573{
1574 cpu->sample.time = time;
1575
1576 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1577 bool do_io = false;
1578
1579 cpu->sched_flags = 0;
1580 /*
1581 * Set iowait_boost flag and update time. Since IO WAIT flag
1582 * is set all the time, we can't just conclude that there is
1583 * some IO bound activity is scheduled on this CPU with just
1584 * one occurrence. If we receive at least two in two
1585 * consecutive ticks, then we treat as boost candidate.
1586 */
1587 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1588 do_io = true;
1589
1590 cpu->last_io_update = time;
1591
1592 if (do_io)
1593 intel_pstate_hwp_boost_up(cpu);
1594
1595 } else {
1596 intel_pstate_hwp_boost_down(cpu);
1597 }
1598}
1599
e0efd5be
SP		 1600static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1601 u64 time, unsigned int flags)
1602{
52ccc431
SP		 1603 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1604
1605 cpu->sched_flags |= flags;
1606
1607 if (smp_processor_id() == cpu->cpu)
1608 intel_pstate_update_util_hwp_local(cpu, time);
e0efd5be
SP		 1609}
1610
a1c9787d 1611static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1612{
6b17ddb2 1613 struct sample *sample = &cpu->sample;
e66c1768 1614
a1c9787d 1615 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1616}
1617
4fec7ad5 1618static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1619{
93f0822d 1620 u64 aperf, mperf;
4ab60c3f 1621 unsigned long flags;
4055fad3 1622 u64 tsc;
93f0822d 1623
4ab60c3f 1624 local_irq_save(flags);
93f0822d
DB		 1625 rdmsrl(MSR_IA32_APERF, aperf);
1626 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1627 tsc = rdtsc();
4fec7ad5 1628 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1629 local_irq_restore(flags);
4fec7ad5 1630 return false;
8e601a9f 1631 }
4ab60c3f 1632 local_irq_restore(flags);
b69880f9 1633
c4ee841f 1634 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1635 cpu->sample.time = time;
d37e2b76
DB		 1636 cpu->sample.aperf = aperf;
1637 cpu->sample.mperf = mperf;
4055fad3 1638 cpu->sample.tsc = tsc;
d37e2b76
DB		 1639 cpu->sample.aperf -= cpu->prev_aperf;
1640 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1641 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1642
93f0822d
DB		 1643 cpu->prev_aperf = aperf;
1644 cpu->prev_mperf = mperf;
4055fad3 1645 cpu->prev_tsc = tsc;
febce40f
RW		 1646 /*
1647 * First time this function is invoked in a given cycle, all of the
1648 * previous sample data fields are equal to zero or stale and they must
1649 * be populated with meaningful numbers for things to work, so assume
1650 * that sample.time will always be reset before setting the utilization
1651 * update hook and make the caller skip the sample then.
1652 */
eabd22c6
RW		 1653 if (cpu->last_sample_time) {
1654 intel_pstate_calc_avg_perf(cpu);
1655 return true;
1656 }
1657 return false;
93f0822d
DB		 1658}
1659
8fa520af
PL		 1660static inline int32_t get_avg_frequency(struct cpudata *cpu)
1661{
c587c79f 1662 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
8fa520af
PL		 1663}
1664
bdcaa23f
PL		 1665static inline int32_t get_avg_pstate(struct cpudata *cpu)
1666{
8edb0a6e
RW		 1667 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1668 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1669}
1670
d77d4888 1671static inline int32_t get_target_pstate(struct cpudata *cpu)
e70eed2b
PL		 1672{
1673 struct sample *sample = &cpu->sample;
09c448d3 1674 int32_t busy_frac, boost;
0843e83c 1675 int target, avg_pstate;
e70eed2b 1676
6e34e1f2
SP		 1677 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1678 sample->tsc);
63d1d656 1679
09c448d3
RW		 1680 boost = cpu->iowait_boost;
1681 cpu->iowait_boost >>= 1;
63d1d656 1682
09c448d3
RW		 1683 if (busy_frac < boost)
1684 busy_frac = boost;
63d1d656 1685
09c448d3 1686 sample->busy_scaled = busy_frac * 100;
0843e83c 1687
7de32556 1688 target = global.no_turbo || global.turbo_disabled ?
0843e83c
RW		 1689 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1690 target += target >> 2;
1691 target = mul_fp(target, busy_frac);
1692 if (target < cpu->pstate.min_pstate)
1693 target = cpu->pstate.min_pstate;
1694
1695 /*
1696 * If the average P-state during the previous cycle was higher than the
1697 * current target, add 50% of the difference to the target to reduce
1698 * possible performance oscillations and offset possible performance
1699 * loss related to moving the workload from one CPU to another within
1700 * a package/module.
1701 */
1702 avg_pstate = get_avg_pstate(cpu);
1703 if (avg_pstate > target)
1704 target += (avg_pstate - target) >> 1;
1705
1706 return target;
e70eed2b
PL		 1707}
1708
001c76f0 1709static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1 1710{
fa93b51c
RW		 1711 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1712 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
fdfdb2b1 1713
b02aabe8 1714 return clamp_t(int, pstate, min_pstate, max_pstate);
001c76f0
RW		 1715}
1716
1717static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1718{
fdfdb2b1
RW		 1719 if (pstate == cpu->pstate.current_pstate)
1720 return;
1721
bc95a454 1722 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1723 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1724}
1725
a891283e 1726static void intel_pstate_adjust_pstate(struct cpudata *cpu)
93f0822d 1727{
67dd9bf4 1728 int from = cpu->pstate.current_pstate;
4055fad3 1729 struct sample *sample;
a891283e 1730 int target_pstate;
4055fad3 1731
001c76f0
RW		 1732 update_turbo_state();
1733
d77d4888 1734 target_pstate = get_target_pstate(cpu);
64078299
RW		 1735 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1736 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1 1737 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1738
1739 sample = &cpu->sample;
a1c9787d 1740 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1741 fp_toint(sample->busy_scaled),
4055fad3
DS		 1742 from,
1743 cpu->pstate.current_pstate,
1744 sample->mperf,
1745 sample->aperf,
1746 sample->tsc,
3ba7bcaa
SP		 1747 get_avg_frequency(cpu),
1748 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1749}
1750
a4675fbc 1751static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1752 unsigned int flags)
93f0822d 1753{
a4675fbc 1754 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1755 u64 delta_ns;
1756
674e7541
VK		 1757 /* Don't allow remote callbacks */
1758 if (smp_processor_id() != cpu->cpu)
1759 return;
1760
eabd22c6
RW		 1761 if (flags & SCHED_CPUFREQ_IOWAIT) {
1762 cpu->iowait_boost = int_tofp(1);
7bde2d50
SP		 1763 cpu->last_update = time;
1764 /*
1765 * The last time the busy was 100% so P-state was max anyway
1766 * so avoid overhead of computation.
1767 */
1768 if (fp_toint(cpu->sample.busy_scaled) == 100)
1769 return;
1770
1771 goto set_pstate;
eabd22c6
RW		 1772 } else if (cpu->iowait_boost) {
1773 /* Clear iowait_boost if the CPU may have been idle. */
1774 delta_ns = time - cpu->last_update;
1775 if (delta_ns > TICK_NSEC)
1776 cpu->iowait_boost = 0;
09c448d3 1777 }
eabd22c6 1778 cpu->last_update = time;
09c448d3 1779 delta_ns = time - cpu->sample.time;
d77d4888 1780 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
eabd22c6 1781 return;
4fec7ad5 1782
7bde2d50 1783set_pstate:
a891283e
RW		 1784 if (intel_pstate_sample(cpu, time))
1785 intel_pstate_adjust_pstate(cpu);
67dd9bf4 1786}
eabd22c6 1787
2f49afc2
RW		 1788static struct pstate_funcs core_funcs = {
1789 .get_max = core_get_max_pstate,
1790 .get_max_physical = core_get_max_pstate_physical,
1791 .get_min = core_get_min_pstate,
1792 .get_turbo = core_get_turbo_pstate,
1793 .get_scaling = core_get_scaling,
1794 .get_val = core_get_val,
de4a76cb
RW		 1795};
1796
2f49afc2
RW		 1797static const struct pstate_funcs silvermont_funcs = {
1798 .get_max = atom_get_max_pstate,
1799 .get_max_physical = atom_get_max_pstate,
1800 .get_min = atom_get_min_pstate,
1801 .get_turbo = atom_get_turbo_pstate,
1802 .get_val = atom_get_val,
1803 .get_scaling = silvermont_get_scaling,
1804 .get_vid = atom_get_vid,
de4a76cb
RW		 1805};
1806
2f49afc2
RW		 1807static const struct pstate_funcs airmont_funcs = {
1808 .get_max = atom_get_max_pstate,
1809 .get_max_physical = atom_get_max_pstate,
1810 .get_min = atom_get_min_pstate,
1811 .get_turbo = atom_get_turbo_pstate,
1812 .get_val = atom_get_val,
1813 .get_scaling = airmont_get_scaling,
1814 .get_vid = atom_get_vid,
de4a76cb
RW		 1815};
1816
2f49afc2
RW		 1817static const struct pstate_funcs knl_funcs = {
1818 .get_max = core_get_max_pstate,
1819 .get_max_physical = core_get_max_pstate_physical,
1820 .get_min = core_get_min_pstate,
1821 .get_turbo = knl_get_turbo_pstate,
6e34e1f2 1822 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2f49afc2
RW		 1823 .get_scaling = core_get_scaling,
1824 .get_val = core_get_val,
de4a76cb
RW		 1825};
1826
93f0822d 1827#define ICPU(model, policy) \
6cbd7ee1
DB		 1828 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1829 (unsigned long)&policy }
93f0822d
DB		 1830
1831static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2f49afc2
RW		 1832 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1833 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
f2c4db1b 1834 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
2f49afc2
RW		 1835 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1836 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1837 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1838 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1839 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1840 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1841 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1842 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1843 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1844 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1845 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1846 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1847 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1848 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1849 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
dbd49b85 1850 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
f2c4db1b 1851 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs),
d8de7a44 1852 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
93f0822d
DB		 1853 {}
1854};
1855MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1856
29327c84 1857static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2f49afc2
RW		 1858 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1859 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1860 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
2f86dc4c
DB		 1861 {}
1862};
1863
6e978b22 1864static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2f49afc2 1865 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
6e978b22
SP		 1866 {}
1867};
1868
41ab43c9
SP		 1869static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1870 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1871 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1872 {}
1873};
1874
93f0822d
DB		 1875static int intel_pstate_init_cpu(unsigned int cpunum)
1876{
93f0822d
DB		 1877 struct cpudata *cpu;
1878
eae48f04
SP		 1879 cpu = all_cpu_data[cpunum];
1880
1881 if (!cpu) {
c5a2ee7d 1882 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
eae48f04
SP		 1883 if (!cpu)
1884 return -ENOMEM;
1885
1886 all_cpu_data[cpunum] = cpu;
eae48f04 1887
984edbdc
SP		 1888 cpu->epp_default = -EINVAL;
1889 cpu->epp_powersave = -EINVAL;
1890 cpu->epp_saved = -EINVAL;
eae48f04 1891 }
93f0822d
DB		 1892
1893 cpu = all_cpu_data[cpunum];
1894
93f0822d 1895 cpu->cpu = cpunum;
ba88d433 1896
a4675fbc 1897 if (hwp_active) {
6e978b22
SP		 1898 const struct x86_cpu_id *id;
1899
1900 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1901 if (id)
1902 intel_pstate_disable_ee(cpunum);
1903
ba88d433 1904 intel_pstate_hwp_enable(cpu);
41ab43c9
SP		 1905
1906 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
01e61a42 1907 if (id && intel_pstate_acpi_pm_profile_server())
41ab43c9 1908 hwp_boost = true;
a4675fbc 1909 }
ba88d433 1910
179e8471 1911 intel_pstate_get_cpu_pstates(cpu);
016c8150 1912
4836df17 1913 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1914
1915 return 0;
1916}
1917
febce40f 1918static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1919{
febce40f
RW		 1920 struct cpudata *cpu = all_cpu_data[cpu_num];
1921
e0efd5be 1922 if (hwp_active && !hwp_boost)
62611cb9
LB		 1923 return;
1924
5ab666e0
RW		 1925 if (cpu->update_util_set)
1926 return;
1927
febce40f
RW		 1928 /* Prevent intel_pstate_update_util() from using stale data. */
1929 cpu->sample.time = 0;
67dd9bf4 1930 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
e0efd5be
SP		 1931 (hwp_active ?
1932 intel_pstate_update_util_hwp :
1933 intel_pstate_update_util));
4578ee7e 1934 cpu->update_util_set = true;
bb6ab52f
RW		 1935}
1936
1937static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1938{
4578ee7e
CY		 1939 struct cpudata *cpu_data = all_cpu_data[cpu];
1940
1941 if (!cpu_data->update_util_set)
1942 return;
1943
0bed612b 1944 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1945 cpu_data->update_util_set = false;
09659af3 1946 synchronize_rcu();
bb6ab52f
RW		 1947}
1948
80b120ca
RW		 1949static int intel_pstate_get_max_freq(struct cpudata *cpu)
1950{
1951 return global.turbo_disabled || global.no_turbo ?
1952 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1953}
1954
eae48f04 1955static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
c5a2ee7d 1956 struct cpudata *cpu)
eae48f04 1957{
80b120ca 1958 int max_freq = intel_pstate_get_max_freq(cpu);
e4c204ce 1959 int32_t max_policy_perf, min_policy_perf;
1a4fe38a 1960 int max_state, turbo_max;
a410c03d 1961
1a4fe38a
SP		 1962 /*
1963 * HWP needs some special consideration, because on BDX the
1964 * HWP_REQUEST uses abstract value to represent performance
1965 * rather than pure ratios.
1966 */
1967 if (hwp_active) {
1968 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1969 } else {
a8e1942d
RW		 1970 max_state = global.no_turbo || global.turbo_disabled ?
1971 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1a4fe38a
SP		 1972 turbo_max = cpu->pstate.turbo_pstate;
1973 }
1974
1975 max_policy_perf = max_state * policy->max / max_freq;
5879f877 1976 if (policy->max == policy->min) {
e4c204ce 1977 min_policy_perf = max_policy_perf;
5879f877 1978 } else {
1a4fe38a 1979 min_policy_perf = max_state * policy->min / max_freq;
e4c204ce
RW		 1980 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1981 0, max_policy_perf);
5879f877 1982 }
eae48f04 1983
1a4fe38a
SP		 1984 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1985 policy->cpu, max_state,
1986 min_policy_perf, max_policy_perf);
1987
e4c204ce 1988 /* Normalize user input to [min_perf, max_perf] */
c5a2ee7d 1989 if (per_cpu_limits) {
1a4fe38a
SP		 1990 cpu->min_perf_ratio = min_policy_perf;
1991 cpu->max_perf_ratio = max_policy_perf;
c5a2ee7d
RW		 1992 } else {
1993 int32_t global_min, global_max;
1994
1995 /* Global limits are in percent of the maximum turbo P-state. */
1a4fe38a
SP		 1996 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1997 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
c5a2ee7d 1998 global_min = clamp_t(int32_t, global_min, 0, global_max);
eae48f04 1999
1a4fe38a
SP		 2000 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2001 global_min, global_max);
c5a2ee7d 2002
1a4fe38a
SP		 2003 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2004 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2005 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2006 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
eae48f04 2007
1a4fe38a
SP		 2008 /* Make sure min_perf <= max_perf */
2009 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2010 cpu->max_perf_ratio);
eae48f04 2011
1a4fe38a
SP		 2012 }
2013 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2014 cpu->max_perf_ratio,
2015 cpu->min_perf_ratio);
eae48f04
SP		 2016}
2017
93f0822d
DB		 2018static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2019{
3be9200d
SP		 2020 struct cpudata *cpu;
2021
d3929b83
DB		 2022 if (!policy->cpuinfo.max_freq)
2023 return -ENODEV;
2024
2c2c1af4
SP		 2025 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2026 policy->cpuinfo.max_freq, policy->max);
2027
a6c6ead1 2028 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 2029 cpu->policy = policy->policy;
2030
b59fe540
SP		 2031 mutex_lock(&intel_pstate_limits_lock);
2032
c5a2ee7d 2033 intel_pstate_update_perf_limits(policy, cpu);
a240c4aa 2034
2f1d407a 2035 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 2036 /*
2037 * NOHZ_FULL CPUs need this as the governor callback may not
2038 * be invoked on them.
2039 */
2040 intel_pstate_clear_update_util_hook(policy->cpu);
2041 intel_pstate_max_within_limits(cpu);
82b4e03e
LB		 2042 } else {
2043 intel_pstate_set_update_util_hook(policy->cpu);
a6c6ead1
RW		 2044 }
2045
e0efd5be
SP		 2046 if (hwp_active) {
2047 /*
2048 * When hwp_boost was active before and dynamically it
2049 * was turned off, in that case we need to clear the
2050 * update util hook.
2051 */
2052 if (!hwp_boost)
2053 intel_pstate_clear_update_util_hook(policy->cpu);
2bfc4cbb 2054 intel_pstate_hwp_set(policy->cpu);
e0efd5be 2055 }
2f86dc4c 2056
b59fe540
SP		 2057 mutex_unlock(&intel_pstate_limits_lock);
2058
93f0822d
DB		 2059 return 0;
2060}
2061
80b120ca
RW		 2062static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2063 struct cpudata *cpu)
2064{
d3264f75
SP		 2065 if (!hwp_active &&
2066 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
80b120ca
RW		 2067 policy->max < policy->cpuinfo.max_freq &&
2068 policy->max > cpu->pstate.max_freq) {
2069 pr_debug("policy->max > max non turbo frequency\n");
2070 policy->max = policy->cpuinfo.max_freq;
2071 }
2072}
2073
93f0822d
DB		 2074static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2075{
7d9a8a9f 2076 struct cpudata *cpu = all_cpu_data[policy->cpu];
7d9a8a9f
SP		 2077
2078 update_turbo_state();
80b120ca
RW		 2079 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2080 intel_pstate_get_max_freq(cpu));
93f0822d 2081
285cb990 2082 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 2083 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 2084 return -EINVAL;
2085
80b120ca
RW		 2086 intel_pstate_adjust_policy_max(policy, cpu);
2087
93f0822d
DB		 2088 return 0;
2089}
2090
001c76f0
RW		 2091static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2092{
2093 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2094}
2095
bb18008f 2096static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 2097{
001c76f0 2098 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 2099
001c76f0 2100 intel_pstate_clear_update_util_hook(policy->cpu);
af3b7379 2101 if (hwp_active) {
984edbdc 2102 intel_pstate_hwp_save_state(policy);
af3b7379
SP		 2103 intel_pstate_hwp_force_min_perf(policy->cpu);
2104 } else {
001c76f0 2105 intel_cpufreq_stop_cpu(policy);
af3b7379 2106 }
001c76f0 2107}
bb18008f 2108
001c76f0
RW		 2109static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2110{
2111 intel_pstate_exit_perf_limits(policy);
a4675fbc 2112
001c76f0 2113 policy->fast_switch_possible = false;
2f86dc4c 2114
001c76f0 2115 return 0;
93f0822d
DB		 2116}
2117
001c76f0 2118static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2119{
93f0822d 2120 struct cpudata *cpu;
52e0a509 2121 int rc;
93f0822d
DB		 2122
2123 rc = intel_pstate_init_cpu(policy->cpu);
2124 if (rc)
2125 return rc;
2126
2127 cpu = all_cpu_data[policy->cpu];
2128
1a4fe38a
SP		 2129 cpu->max_perf_ratio = 0xFF;
2130 cpu->min_perf_ratio = 0;
93f0822d 2131
b27580b0
DB		 2132 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2133 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 2134
2135 /* cpuinfo and default policy values */
b27580b0 2136 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e 2137 update_turbo_state();
7de32556 2138 policy->cpuinfo.max_freq = global.turbo_disabled ?
983e600e
SP		 2139 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2140 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2141
eea033d0
SP		 2142 if (hwp_active) {
2143 unsigned int max_freq;
2144
2145 max_freq = global.turbo_disabled ?
2146 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2147 if (max_freq < policy->cpuinfo.max_freq)
2148 policy->cpuinfo.max_freq = max_freq;
2149 }
2150
9522a2ff 2151 intel_pstate_init_acpi_perf_limits(policy);
93f0822d 2152
001c76f0
RW		 2153 policy->fast_switch_possible = true;
2154
93f0822d
DB		 2155 return 0;
2156}
2157
001c76f0 2158static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2159{
001c76f0
RW		 2160 int ret = __intel_pstate_cpu_init(policy);
2161
2162 if (ret)
2163 return ret;
2164
7de32556 2165 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
001c76f0
RW		 2166 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2167 else
2168 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 2169
2170 return 0;
2171}
2172
001c76f0 2173static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2174 .flags = CPUFREQ_CONST_LOOPS,
2175 .verify = intel_pstate_verify_policy,
2176 .setpolicy = intel_pstate_set_policy,
984edbdc 2177 .suspend = intel_pstate_hwp_save_state,
8442885f 2178 .resume = intel_pstate_resume,
93f0822d 2179 .init = intel_pstate_cpu_init,
9522a2ff 2180 .exit = intel_pstate_cpu_exit,
bb18008f 2181 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 2182 .name = "intel_pstate",
93f0822d
DB		 2183};
2184
001c76f0
RW		 2185static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2186{
2187 struct cpudata *cpu = all_cpu_data[policy->cpu];
001c76f0
RW		 2188
2189 update_turbo_state();
80b120ca
RW		 2190 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2191 intel_pstate_get_max_freq(cpu));
001c76f0 2192
80b120ca 2193 intel_pstate_adjust_policy_max(policy, cpu);
001c76f0 2194
c5a2ee7d
RW		 2195 intel_pstate_update_perf_limits(policy, cpu);
2196
001c76f0
RW		 2197 return 0;
2198}
2199
50e9ffab
DS		 2200/* Use of trace in passive mode:
2201 *
2202 * In passive mode the trace core_busy field (also known as the
2203 * performance field, and lablelled as such on the graphs; also known as
2204 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2205 * driver call was via the normal or fast switch path. Various graphs
2206 * output from the intel_pstate_tracer.py utility that include core_busy
2207 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2208 * so we use 10 to indicate the the normal path through the driver, and
2209 * 90 to indicate the fast switch path through the driver.
2210 * The scaled_busy field is not used, and is set to 0.
2211 */
2212
2213#define INTEL_PSTATE_TRACE_TARGET 10
2214#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2215
2216static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2217{
2218 struct sample *sample;
2219
2220 if (!trace_pstate_sample_enabled())
2221 return;
2222
2223 if (!intel_pstate_sample(cpu, ktime_get()))
2224 return;
2225
2226 sample = &cpu->sample;
2227 trace_pstate_sample(trace_type,
2228 0,
2229 old_pstate,
2230 cpu->pstate.current_pstate,
2231 sample->mperf,
2232 sample->aperf,
2233 sample->tsc,
2234 get_avg_frequency(cpu),
2235 fp_toint(cpu->iowait_boost * 100));
2236}
2237
001c76f0
RW		 2238static int intel_cpufreq_target(struct cpufreq_policy *policy,
2239 unsigned int target_freq,
2240 unsigned int relation)
2241{
2242 struct cpudata *cpu = all_cpu_data[policy->cpu];
2243 struct cpufreq_freqs freqs;
50e9ffab 2244 int target_pstate, old_pstate;
001c76f0 2245
64897b20
RW		 2246 update_turbo_state();
2247
001c76f0 2248 freqs.old = policy->cur;
64897b20 2249 freqs.new = target_freq;
001c76f0
RW		 2250
2251 cpufreq_freq_transition_begin(policy, &freqs);
2252 switch (relation) {
2253 case CPUFREQ_RELATION_L:
2254 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2255 break;
2256 case CPUFREQ_RELATION_H:
2257 target_pstate = freqs.new / cpu->pstate.scaling;
2258 break;
2259 default:
2260 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2261 break;
2262 }
2263 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2264 old_pstate = cpu->pstate.current_pstate;
001c76f0
RW		 2265 if (target_pstate != cpu->pstate.current_pstate) {
2266 cpu->pstate.current_pstate = target_pstate;
2267 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2268 pstate_funcs.get_val(cpu, target_pstate));
2269 }
64078299 2270 freqs.new = target_pstate * cpu->pstate.scaling;
50e9ffab 2271 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
001c76f0
RW		 2272 cpufreq_freq_transition_end(policy, &freqs, false);
2273
2274 return 0;
2275}
2276
2277static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2278 unsigned int target_freq)
2279{
2280 struct cpudata *cpu = all_cpu_data[policy->cpu];
50e9ffab 2281 int target_pstate, old_pstate;
001c76f0 2282
64897b20
RW		 2283 update_turbo_state();
2284
001c76f0 2285 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
64078299 2286 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2287 old_pstate = cpu->pstate.current_pstate;
001c76f0 2288 intel_pstate_update_pstate(cpu, target_pstate);
50e9ffab 2289 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
64078299 2290 return target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2291}
2292
2293static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2294{
2295 int ret = __intel_pstate_cpu_init(policy);
2296
2297 if (ret)
2298 return ret;
2299
2300 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
1b72e7fd 2301 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
001c76f0
RW		 2302 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2303 policy->cur = policy->cpuinfo.min_freq;
2304
2305 return 0;
2306}
2307
2308static struct cpufreq_driver intel_cpufreq = {
2309 .flags = CPUFREQ_CONST_LOOPS,
2310 .verify = intel_cpufreq_verify_policy,
2311 .target = intel_cpufreq_target,
2312 .fast_switch = intel_cpufreq_fast_switch,
2313 .init = intel_cpufreq_cpu_init,
2314 .exit = intel_pstate_cpu_exit,
2315 .stop_cpu = intel_cpufreq_stop_cpu,
2316 .name = "intel_cpufreq",
2317};
2318
ee8df89a 2319static struct cpufreq_driver *default_driver = &intel_pstate;
001c76f0 2320
fb1fe104
RW		 2321static void intel_pstate_driver_cleanup(void)
2322{
2323 unsigned int cpu;
2324
2325 get_online_cpus();
2326 for_each_online_cpu(cpu) {
2327 if (all_cpu_data[cpu]) {
2328 if (intel_pstate_driver == &intel_pstate)
2329 intel_pstate_clear_update_util_hook(cpu);
2330
2331 kfree(all_cpu_data[cpu]);
2332 all_cpu_data[cpu] = NULL;
2333 }
2334 }
2335 put_online_cpus();
ee8df89a 2336 intel_pstate_driver = NULL;
fb1fe104
RW		 2337}
2338
ee8df89a 2339static int intel_pstate_register_driver(struct cpufreq_driver *driver)
fb1fe104
RW		 2340{
2341 int ret;
2342
c5a2ee7d
RW		 2343 memset(&global, 0, sizeof(global));
2344 global.max_perf_pct = 100;
c3a49c89 2345
ee8df89a 2346 intel_pstate_driver = driver;
fb1fe104
RW		 2347 ret = cpufreq_register_driver(intel_pstate_driver);
2348 if (ret) {
2349 intel_pstate_driver_cleanup();
2350 return ret;
2351 }
2352
c5a2ee7d
RW		 2353 global.min_perf_pct = min_perf_pct_min();
2354
fb1fe104
RW		 2355 return 0;
2356}
2357
2358static int intel_pstate_unregister_driver(void)
2359{
2360 if (hwp_active)
2361 return -EBUSY;
2362
fb1fe104
RW		 2363 cpufreq_unregister_driver(intel_pstate_driver);
2364 intel_pstate_driver_cleanup();
2365
2366 return 0;
2367}
2368
2369static ssize_t intel_pstate_show_status(char *buf)
2370{
ee8df89a 2371 if (!intel_pstate_driver)
fb1fe104
RW		 2372 return sprintf(buf, "off\n");
2373
2374 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2375 "active" : "passive");
2376}
2377
2378static int intel_pstate_update_status(const char *buf, size_t size)
2379{
2380 int ret;
2381
2382 if (size == 3 && !strncmp(buf, "off", size))
ee8df89a 2383 return intel_pstate_driver ?
fb1fe104
RW		 2384 intel_pstate_unregister_driver() : -EINVAL;
2385
2386 if (size == 6 && !strncmp(buf, "active", size)) {
ee8df89a 2387 if (intel_pstate_driver) {
fb1fe104
RW		 2388 if (intel_pstate_driver == &intel_pstate)
2389 return 0;
2390
2391 ret = intel_pstate_unregister_driver();
2392 if (ret)
2393 return ret;
2394 }
2395
ee8df89a 2396 return intel_pstate_register_driver(&intel_pstate);
fb1fe104
RW		 2397 }
2398
2399 if (size == 7 && !strncmp(buf, "passive", size)) {
ee8df89a 2400 if (intel_pstate_driver) {
0042b2c0 2401 if (intel_pstate_driver == &intel_cpufreq)
fb1fe104
RW		 2402 return 0;
2403
2404 ret = intel_pstate_unregister_driver();
2405 if (ret)
2406 return ret;
2407 }
2408
ee8df89a 2409 return intel_pstate_register_driver(&intel_cpufreq);
fb1fe104
RW		 2410 }
2411
2412 return -EINVAL;
2413}
2414
eed43609
JZ		 2415static int no_load __initdata;
2416static int no_hwp __initdata;
2417static int hwp_only __initdata;
29327c84 2418static unsigned int force_load __initdata;
6be26498 2419
29327c84 2420static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2421{
016c8150 2422 if (!pstate_funcs.get_max() ||
c410833a
SK		 2423 !pstate_funcs.get_min() ||
2424 !pstate_funcs.get_turbo())
b563b4e3
DB		 2425 return -ENODEV;
2426
b563b4e3
DB		 2427 return 0;
2428}
016c8150 2429
29327c84 2430static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2431{
2432 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2433 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2434 pstate_funcs.get_min = funcs->get_min;
2435 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2436 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2437 pstate_funcs.get_val = funcs->get_val;
007bea09 2438 pstate_funcs.get_vid = funcs->get_vid;
6e34e1f2 2439 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
016c8150
DB		 2440}
2441
9522a2ff 2442#ifdef CONFIG_ACPI
fbbcdc07 2443
29327c84 2444static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2445{
2446 int i;
2447
2448 for_each_possible_cpu(i) {
2449 acpi_status status;
2450 union acpi_object *pss;
2451 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2452 struct acpi_processor *pr = per_cpu(processors, i);
2453
2454 if (!pr)
2455 continue;
2456
2457 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2458 if (ACPI_FAILURE(status))
2459 continue;
2460
2461 pss = buffer.pointer;
2462 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2463 kfree(pss);
2464 return false;
2465 }
2466
2467 kfree(pss);
2468 }
2469
076b862c 2470 pr_debug("ACPI _PSS not found\n");
fbbcdc07
AH		 2471 return true;
2472}
2473
95d6c085
RW		 2474static bool __init intel_pstate_no_acpi_pcch(void)
2475{
2476 acpi_status status;
2477 acpi_handle handle;
2478
2479 status = acpi_get_handle(NULL, "\\_SB", &handle);
2480 if (ACPI_FAILURE(status))
076b862c
EV		 2481 goto not_found;
2482
2483 if (acpi_has_method(handle, "PCCH"))
2484 return false;
95d6c085 2485
076b862c
EV		 2486not_found:
2487 pr_debug("ACPI PCCH not found\n");
2488 return true;
95d6c085
RW		 2489}
2490
29327c84 2491static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2492{
2493 int i;
2494
2495 for_each_possible_cpu(i) {
2496 struct acpi_processor *pr = per_cpu(processors, i);
2497
2498 if (!pr)
2499 continue;
2500 if (acpi_has_method(pr->handle, "_PPC"))
2501 return true;
2502 }
076b862c 2503 pr_debug("ACPI _PPC not found\n");
966916ea 2504 return false;
2505}
2506
2507enum {
2508 PSS,
2509 PPC,
2510};
2511
fbbcdc07 2512/* Hardware vendor-specific info that has its own power management modes */
5e932321
TK		 2513static struct acpi_platform_list plat_info[] __initdata = {
2514 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2515 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2516 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2517 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2518 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2519 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2520 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2521 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2522 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2523 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2524 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2525 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2526 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2527 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2528 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2529 { } /* End */
fbbcdc07
AH		 2530};
2531
29327c84 2532static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07 2533{
2f86dc4c
DB		 2534 const struct x86_cpu_id *id;
2535 u64 misc_pwr;
5e932321 2536 int idx;
2f86dc4c
DB		 2537
2538 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2539 if (id) {
2540 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
076b862c
EV		 2541 if (misc_pwr & (1 << 8)) {
2542 pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
2f86dc4c 2543 return true;
076b862c 2544 }
2f86dc4c 2545 }
fbbcdc07 2546
5e932321
TK		 2547 idx = acpi_match_platform_list(plat_info);
2548 if (idx < 0)
fbbcdc07
AH		 2549 return false;
2550
5e932321
TK		 2551 switch (plat_info[idx].data) {
2552 case PSS:
95d6c085
RW		 2553 if (!intel_pstate_no_acpi_pss())
2554 return false;
2555
2556 return intel_pstate_no_acpi_pcch();
5e932321
TK		 2557 case PPC:
2558 return intel_pstate_has_acpi_ppc() && !force_load;
fbbcdc07
AH		 2559 }
2560
2561 return false;
2562}
d0ea59e1
RW		 2563
2564static void intel_pstate_request_control_from_smm(void)
2565{
2566 /*
2567 * It may be unsafe to request P-states control from SMM if _PPC support
2568 * has not been enabled.
2569 */
2570 if (acpi_ppc)
2571 acpi_processor_pstate_control();
2572}
fbbcdc07
AH		 2573#else /* CONFIG_ACPI not enabled */
2574static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2575static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2576static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2577#endif /* CONFIG_ACPI */
2578
ff7c9917
SP		 2579#define INTEL_PSTATE_HWP_BROADWELL 0x01
2580
2581#define ICPU_HWP(model, hwp_mode) \
2582 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2583
7791e4aa 2584static const struct x86_cpu_id hwp_support_ids[] __initconst = {
ff7c9917
SP		 2585 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2586 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2587 ICPU_HWP(X86_MODEL_ANY, 0),
7791e4aa
SP		 2588 {}
2589};
2590
93f0822d
DB		 2591static int __init intel_pstate_init(void)
2592{
ff7c9917 2593 const struct x86_cpu_id *id;
eb5139d1 2594 int rc;
93f0822d 2595
6be26498
DB		 2596 if (no_load)
2597 return -ENODEV;
2598
ff7c9917
SP		 2599 id = x86_match_cpu(hwp_support_ids);
2600 if (id) {
2f49afc2 2601 copy_cpu_funcs(&core_funcs);
c4f3f70c 2602 if (!no_hwp) {
eb5139d1 2603 hwp_active++;
ff7c9917 2604 hwp_mode_bdw = id->driver_data;
eb5139d1
RW		 2605 intel_pstate.attr = hwp_cpufreq_attrs;
2606 goto hwp_cpu_matched;
2607 }
2608 } else {
eb5139d1 2609 id = x86_match_cpu(intel_pstate_cpu_ids);
076b862c
EV		 2610 if (!id) {
2611 pr_info("CPU ID not supported\n");
eb5139d1 2612 return -ENODEV;
076b862c 2613 }
93f0822d 2614
2f49afc2 2615 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
eb5139d1 2616 }
016c8150 2617
076b862c
EV		 2618 if (intel_pstate_msrs_not_valid()) {
2619 pr_info("Invalid MSRs\n");
b563b4e3 2620 return -ENODEV;
076b862c 2621 }
b563b4e3 2622
7791e4aa
SP		 2623hwp_cpu_matched:
2624 /*
2625 * The Intel pstate driver will be ignored if the platform
2626 * firmware has its own power management modes.
2627 */
076b862c
EV		 2628 if (intel_pstate_platform_pwr_mgmt_exists()) {
2629 pr_info("P-states controlled by the platform\n");
7791e4aa 2630 return -ENODEV;
076b862c 2631 }
7791e4aa 2632
fb1fe104
RW		 2633 if (!hwp_active && hwp_only)
2634 return -ENOTSUPP;
2635
4836df17 2636 pr_info("Intel P-state driver initializing\n");
93f0822d 2637
fad953ce 2638 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
93f0822d
DB		 2639 if (!all_cpu_data)
2640 return -ENOMEM;
93f0822d 2641
d0ea59e1
RW		 2642 intel_pstate_request_control_from_smm();
2643
93f0822d 2644 intel_pstate_sysfs_expose_params();
b69880f9 2645
0c30b65b 2646 mutex_lock(&intel_pstate_driver_lock);
ee8df89a 2647 rc = intel_pstate_register_driver(default_driver);
0c30b65b 2648 mutex_unlock(&intel_pstate_driver_lock);
fb1fe104
RW		 2649 if (rc)
2650 return rc;
366430b5 2651
7791e4aa 2652 if (hwp_active)
4836df17 2653 pr_info("HWP enabled\n");
7791e4aa 2654
fb1fe104 2655 return 0;
93f0822d
DB		 2656}
2657device_initcall(intel_pstate_init);
2658
6be26498
DB		 2659static int __init intel_pstate_setup(char *str)
2660{
2661 if (!str)
2662 return -EINVAL;
2663
001c76f0 2664 if (!strcmp(str, "disable")) {
6be26498 2665 no_load = 1;
001c76f0
RW		 2666 } else if (!strcmp(str, "passive")) {
2667 pr_info("Passive mode enabled\n");
ee8df89a 2668 default_driver = &intel_cpufreq;
001c76f0
RW		 2669 no_hwp = 1;
2670 }
539342f6 2671 if (!strcmp(str, "no_hwp")) {
4836df17 2672 pr_info("HWP disabled\n");
2f86dc4c 2673 no_hwp = 1;
539342f6 2674 }
aa4ea34d
EZ		 2675 if (!strcmp(str, "force"))
2676 force_load = 1;
d64c3b0b
KCA		 2677 if (!strcmp(str, "hwp_only"))
2678 hwp_only = 1;
eae48f04
SP		 2679 if (!strcmp(str, "per_cpu_perf_limits"))
2680 per_cpu_limits = true;
9522a2ff
SP		 2681
2682#ifdef CONFIG_ACPI
2683 if (!strcmp(str, "support_acpi_ppc"))
2684 acpi_ppc = true;
2685#endif
2686
6be26498
DB		 2687 return 0;
2688}
2689early_param("intel_pstate", intel_pstate_setup);
2690
93f0822d
DB		 2691MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2692MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2693MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)