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net: stmmac: move the EST structure to struct stmmac_priv
[linux-block.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
b886d83c 1// SPDX-License-Identifier: GPL-2.0-only
93f0822d 2/*
d1b68485 3 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
93f0822d
DB		 7 */
8
4836df17
JP		 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
93f0822d
DB		 11#include <linux/kernel.h>
12#include <linux/kernel_stat.h>
13#include <linux/module.h>
14#include <linux/ktime.h>
15#include <linux/hrtimer.h>
16#include <linux/tick.h>
17#include <linux/slab.h>
55687da1 18#include <linux/sched/cpufreq.h>
93f0822d
DB		 19#include <linux/list.h>
20#include <linux/cpu.h>
21#include <linux/cpufreq.h>
22#include <linux/sysfs.h>
23#include <linux/types.h>
24#include <linux/fs.h>
fbbcdc07 25#include <linux/acpi.h>
d6472302 26#include <linux/vmalloc.h>
da5c504c 27#include <linux/pm_qos.h>
240a8da6 28#include <linux/bitfield.h>
93f0822d
DB		 29#include <trace/events/power.h>
30
f5c8cf2a 31#include <asm/cpu.h>
93f0822d
DB		 32#include <asm/div64.h>
33#include <asm/msr.h>
34#include <asm/cpu_device_id.h>
64df1fdf 35#include <asm/cpufeature.h>
5b20c944 36#include <asm/intel-family.h>
57577c99 37#include "../drivers/thermal/intel/thermal_interrupt.h"
93f0822d 38
d77d4888 39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
eabd22c6 40
001c76f0 41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
f6ebbcf0 42#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
1b72e7fd 43#define INTEL_CPUFREQ_TRANSITION_DELAY 500
001c76f0 44
9522a2ff
SP		 45#ifdef CONFIG_ACPI
46#include <acpi/processor.h>
17669006 47#include <acpi/cppc_acpi.h>
9522a2ff
SP		 48#endif
49
f0fe3cd7 50#define FRAC_BITS 8
93f0822d
DB		 51#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 53
b8bd1581
RW		 54#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
55
a1c9787d
RW		 56#define EXT_BITS 6
57#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 58#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
59#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 60
93f0822d
DB		 61static inline int32_t mul_fp(int32_t x, int32_t y)
62{
63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
64}
65
7180dddf 66static inline int32_t div_fp(s64 x, s64 y)
93f0822d 67{
7180dddf 68 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 69}
70
d022a65e
DB		 71static inline int ceiling_fp(int32_t x)
72{
73 int mask, ret;
74
75 ret = fp_toint(x);
76 mask = (1 << FRAC_BITS) - 1;
77 if (x & mask)
78 ret += 1;
79 return ret;
80}
81
a1c9787d
RW		 82static inline u64 mul_ext_fp(u64 x, u64 y)
83{
84 return (x * y) >> EXT_FRAC_BITS;
85}
86
87static inline u64 div_ext_fp(u64 x, u64 y)
88{
89 return div64_u64(x << EXT_FRAC_BITS, y);
90}
91
13ad7701
SP		 92/**
93 * struct sample - Store performance sample
a1c9787d 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 97 * P state. This can be different than core_avg_perf
13ad7701
SP		 98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
104 * current sample
13ad7701
SP		 105 * @time: Current time from scheduler
106 *
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
109 */
93f0822d 110struct sample {
a1c9787d 111 int32_t core_avg_perf;
157386b6 112 int32_t busy_scaled;
93f0822d
DB		 113 u64 aperf;
114 u64 mperf;
4055fad3 115 u64 tsc;
a4675fbc 116 u64 time;
93f0822d
DB		 117};
118
13ad7701
SP		 119/**
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
eb3693f0
RW		 127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
128 * @scaling: Scaling factor between performance and frequency
13ad7701 129 * @turbo_pstate: Max Turbo P state possible for this platform
eb3693f0 130 * @min_freq: @min_pstate frequency in cpufreq units
001c76f0
RW		 131 * @max_freq: @max_pstate frequency in cpufreq units
132 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 133 *
134 * Stores the per cpu model P state limits and current P state.
135 */
93f0822d
DB		 136struct pstate_data {
137 int current_pstate;
138 int min_pstate;
139 int max_pstate;
3bcc6fa9 140 int max_pstate_physical;
eb3693f0 141 int perf_ctl_scaling;
b27580b0 142 int scaling;
93f0822d 143 int turbo_pstate;
eb3693f0 144 unsigned int min_freq;
001c76f0
RW		 145 unsigned int max_freq;
146 unsigned int turbo_freq;
93f0822d
DB		 147};
148
13ad7701
SP		 149/**
150 * struct vid_data - Stores voltage information data
151 * @min: VID data for this platform corresponding to
152 * the lowest P state
153 * @max: VID data corresponding to the highest P State.
154 * @turbo: VID data for turbo P state
155 * @ratio: Ratio of (vid max - vid min) /
156 * (max P state - Min P State)
157 *
158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
159 * This data is used in Atom platforms, where in addition to target P state,
160 * the voltage data needs to be specified to select next P State.
161 */
007bea09 162struct vid_data {
21855ff5
DB		 163 int min;
164 int max;
165 int turbo;
007bea09
DB		 166 int32_t ratio;
167};
168
c5a2ee7d
RW		 169/**
170 * struct global_params - Global parameters, mostly tunable via sysfs.
171 * @no_turbo: Whether or not to use turbo P-states.
731e6b97 172 * @turbo_disabled: Whether or not turbo P-states are available at all,
c5a2ee7d
RW		 173 * based on the MSR_IA32_MISC_ENABLE value and whether or
174 * not the maximum reported turbo P-state is different from
175 * the maximum reported non-turbo one.
9083e498 176 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
c5a2ee7d
RW		 177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * P-state capacity.
179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
180 * P-state capacity.
181 */
182struct global_params {
183 bool no_turbo;
184 bool turbo_disabled;
9083e498 185 bool turbo_disabled_mf;
c5a2ee7d
RW		 186 int max_perf_pct;
187 int min_perf_pct;
eae48f04
SP		 188};
189
13ad7701
SP		 190/**
191 * struct cpudata - Per CPU instance data storage
192 * @cpu: CPU number for this instance data
2f1d407a 193 * @policy: CPUFreq policy value
13ad7701 194 * @update_util: CPUFreq utility callback information
4578ee7e 195 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 196 * @iowait_boost: iowait-related boost fraction
197 * @last_update: Time of the last update.
13ad7701
SP		 198 * @pstate: Stores P state limits for this CPU
199 * @vid: Stores VID limits for this CPU
13ad7701 200 * @last_sample_time: Last Sample time
23a522e3 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
13ad7701
SP		 202 * @prev_aperf: Last APERF value read from APERF MSR
203 * @prev_mperf: Last MPERF value read from MPERF MSR
204 * @prev_tsc: Last timestamp counter (TSC) value
13ad7701 205 * @sample: Storage for storing last Sample data
1a4fe38a
SP		 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
9522a2ff
SP		 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS
209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 210 * @epp_powersave: Last saved HWP energy performance preference
211 * (EPP) or energy performance bias (EPB),
212 * when policy switched to performance
8442885f 213 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 214 * @epp_default: Power on default HWP energy performance
215 * preference/bias
f6ebbcf0 216 * @epp_cached Cached HWP energy-performance preference value
e0efd5be
SP		 217 * @hwp_req_cached: Cached value of the last HWP Request MSR
218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
52ccc431
SP		 219 * @last_io_update: Last time when IO wake flag was set
220 * @sched_flags: Store scheduler flags for possible cross CPU update
e0efd5be 221 * @hwp_boost_min: Last HWP boosted min performance
4adcf2e5 222 * @suspended: Whether or not the driver has been suspended.
57577c99 223 * @hwp_notify_work: workqueue for HWP notifications.
13ad7701
SP		 224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
93f0822d
DB		 227struct cpudata {
228 int cpu;
229
2f1d407a 230 unsigned int policy;
a4675fbc 231 struct update_util_data update_util;
4578ee7e 232 bool update_util_set;
93f0822d 233
93f0822d 234 struct pstate_data pstate;
007bea09 235 struct vid_data vid;
93f0822d 236
09c448d3 237 u64 last_update;
a4675fbc 238 u64 last_sample_time;
6e34e1f2 239 u64 aperf_mperf_shift;
93f0822d
DB		 240 u64 prev_aperf;
241 u64 prev_mperf;
4055fad3 242 u64 prev_tsc;
d37e2b76 243 struct sample sample;
1a4fe38a
SP		 244 int32_t min_perf_ratio;
245 int32_t max_perf_ratio;
9522a2ff
SP		 246#ifdef CONFIG_ACPI
247 struct acpi_processor_performance acpi_perf_data;
248 bool valid_pss_table;
249#endif
09c448d3 250 unsigned int iowait_boost;
984edbdc 251 s16 epp_powersave;
8442885f 252 s16 epp_policy;
984edbdc 253 s16 epp_default;
f6ebbcf0 254 s16 epp_cached;
e0efd5be
SP		 255 u64 hwp_req_cached;
256 u64 hwp_cap_cached;
52ccc431
SP		 257 u64 last_io_update;
258 unsigned int sched_flags;
e0efd5be 259 u32 hwp_boost_min;
4adcf2e5 260 bool suspended;
57577c99 261 struct delayed_work hwp_notify_work;
93f0822d
DB		 262};
263
264static struct cpudata **all_cpu_data;
13ad7701 265
13ad7701
SP		 266/**
267 * struct pstate_funcs - Per CPU model specific callbacks
268 * @get_max: Callback to get maximum non turbo effective P state
269 * @get_max_physical: Callback to get maximum non turbo physical P state
270 * @get_min: Callback to get minimum P state
271 * @get_turbo: Callback to get turbo P state
272 * @get_scaling: Callback to get frequency scaling factor
46573fd6 273 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
8f23d1f1 274 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
13ad7701
SP		 275 * @get_val: Callback to convert P state to actual MSR write value
276 * @get_vid: Callback to get VID data for Atom platforms
13ad7701
SP		 277 *
278 * Core and Atom CPU models have different way to get P State limits. This
279 * structure is used to store those callbacks.
280 */
016c8150 281struct pstate_funcs {
8dbab94d
RW		 282 int (*get_max)(int cpu);
283 int (*get_max_physical)(int cpu);
284 int (*get_min)(int cpu);
285 int (*get_turbo)(int cpu);
b27580b0 286 int (*get_scaling)(void);
46573fd6 287 int (*get_cpu_scaling)(int cpu);
6e34e1f2 288 int (*get_aperf_mperf_shift)(void);
fdfdb2b1 289 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 290 void (*get_vid)(struct cpudata *);
93f0822d
DB		 291};
292
4a7cb7a9 293static struct pstate_funcs pstate_funcs __read_mostly;
5c439053 294
4a7cb7a9 295static int hwp_active __read_mostly;
ff7c9917 296static int hwp_mode_bdw __read_mostly;
eae48f04 297static bool per_cpu_limits __read_mostly;
e0efd5be 298static bool hwp_boost __read_mostly;
21cdb6c1 299static bool hwp_forced __read_mostly;
016c8150 300
ee8df89a 301static struct cpufreq_driver *intel_pstate_driver __read_mostly;
0c30b65b 302
bde4f5ff
SP		 303#define HYBRID_SCALING_FACTOR 78741
304#define HYBRID_SCALING_FACTOR_MTL 80000
305
306static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
0fcfc9e5
SP		 307
308static inline int core_get_scaling(void)
309{
310 return 100000;
311}
312
9522a2ff
SP		 313#ifdef CONFIG_ACPI
314static bool acpi_ppc;
315#endif
13ad7701 316
c5a2ee7d 317static struct global_params global;
93f0822d 318
0c30b65b 319static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 320static DEFINE_MUTEX(intel_pstate_limits_lock);
321
9522a2ff 322#ifdef CONFIG_ACPI
2b3ec765 323
01e61a42 324static bool intel_pstate_acpi_pm_profile_server(void)
2b3ec765
SP		 325{
326 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
327 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
328 return true;
329
01e61a42
SP		 330 return false;
331}
332
333static bool intel_pstate_get_ppc_enable_status(void)
334{
335 if (intel_pstate_acpi_pm_profile_server())
336 return true;
337
2b3ec765
SP		 338 return acpi_ppc;
339}
340
17669006
RW		 341#ifdef CONFIG_ACPI_CPPC_LIB
342
343/* The work item is needed to avoid CPU hotplug locking issues */
344static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
345{
346 sched_set_itmt_support();
347}
348
349static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
350
03c83982
SP		 351#define CPPC_MAX_PERF U8_MAX
352
17669006
RW		 353static void intel_pstate_set_itmt_prio(int cpu)
354{
355 struct cppc_perf_caps cppc_perf;
356 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
357 int ret;
358
359 ret = cppc_get_perf_caps(cpu, &cppc_perf);
360 if (ret)
361 return;
362
03c83982
SP		 363 /*
364 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
365 * In this case we can't use CPPC.highest_perf to enable ITMT.
366 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
367 */
368 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
369 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
370
17669006
RW		 371 /*
372 * The priorities can be set regardless of whether or not
373 * sched_set_itmt_support(true) has been called and it is valid to
374 * update them at any time after it has been called.
375 */
376 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
377
378 if (max_highest_perf <= min_highest_perf) {
379 if (cppc_perf.highest_perf > max_highest_perf)
380 max_highest_perf = cppc_perf.highest_perf;
381
382 if (cppc_perf.highest_perf < min_highest_perf)
383 min_highest_perf = cppc_perf.highest_perf;
384
385 if (max_highest_perf > min_highest_perf) {
386 /*
387 * This code can be run during CPU online under the
388 * CPU hotplug locks, so sched_set_itmt_support()
389 * cannot be called from here. Queue up a work item
390 * to invoke it.
391 */
392 schedule_work(&sched_itmt_work);
393 }
394 }
395}
86d333a8 396
8df71a7d 397static int intel_pstate_get_cppc_guaranteed(int cpu)
86d333a8
SP		 398{
399 struct cppc_perf_caps cppc_perf;
400 int ret;
401
402 ret = cppc_get_perf_caps(cpu, &cppc_perf);
403 if (ret)
404 return ret;
405
92a3e426
SP		 406 if (cppc_perf.guaranteed_perf)
407 return cppc_perf.guaranteed_perf;
408
409 return cppc_perf.nominal_perf;
86d333a8 410}
0fcfc9e5
SP		 411
412static int intel_pstate_cppc_get_scaling(int cpu)
413{
414 struct cppc_perf_caps cppc_perf;
415 int ret;
416
417 ret = cppc_get_perf_caps(cpu, &cppc_perf);
418
419 /*
420 * If the nominal frequency and the nominal performance are not
421 * zero and the ratio between them is not 100, return the hybrid
422 * scaling factor.
423 */
424 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
425 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
bde4f5ff 426 return hybrid_scaling_factor;
0fcfc9e5
SP		 427
428 return core_get_scaling();
429}
430
5906056e 431#else /* CONFIG_ACPI_CPPC_LIB */
8df71a7d 432static inline void intel_pstate_set_itmt_prio(int cpu)
17669006
RW		 433{
434}
5906056e 435#endif /* CONFIG_ACPI_CPPC_LIB */
17669006 436
9522a2ff
SP		 437static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
438{
439 struct cpudata *cpu;
9522a2ff
SP		 440 int ret;
441 int i;
442
17669006
RW		 443 if (hwp_active) {
444 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 445 return;
17669006 446 }
e59a8f7f 447
2b3ec765 448 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 449 return;
450
451 cpu = all_cpu_data[policy->cpu];
452
453 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
454 policy->cpu);
455 if (ret)
456 return;
457
458 /*
459 * Check if the control value in _PSS is for PERF_CTL MSR, which should
460 * guarantee that the states returned by it map to the states in our
461 * list directly.
462 */
463 if (cpu->acpi_perf_data.control_register.space_id !=
464 ACPI_ADR_SPACE_FIXED_HARDWARE)
465 goto err;
466
467 /*
468 * If there is only one entry _PSS, simply ignore _PSS and continue as
469 * usual without taking _PSS into account
470 */
471 if (cpu->acpi_perf_data.state_count < 2)
472 goto err;
473
474 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
475 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
476 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
477 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
478 (u32) cpu->acpi_perf_data.states[i].core_frequency,
479 (u32) cpu->acpi_perf_data.states[i].power,
480 (u32) cpu->acpi_perf_data.states[i].control);
481 }
482
9522a2ff 483 cpu->valid_pss_table = true;
6cacd115 484 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 485
486 return;
487
488 err:
489 cpu->valid_pss_table = false;
490 acpi_processor_unregister_performance(policy->cpu);
491}
492
493static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
494{
495 struct cpudata *cpu;
496
497 cpu = all_cpu_data[policy->cpu];
498 if (!cpu->valid_pss_table)
499 return;
500
501 acpi_processor_unregister_performance(policy->cpu);
502}
5906056e 503#else /* CONFIG_ACPI */
7a3ba767 504static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 505{
506}
507
7a3ba767 508static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 509{
510}
01e61a42
SP		 511
512static inline bool intel_pstate_acpi_pm_profile_server(void)
513{
514 return false;
515}
5906056e
DB		 516#endif /* CONFIG_ACPI */
517
518#ifndef CONFIG_ACPI_CPPC_LIB
8df71a7d 519static inline int intel_pstate_get_cppc_guaranteed(int cpu)
5906056e
DB		 520{
521 return -ENOTSUPP;
522}
0fcfc9e5
SP		 523
524static int intel_pstate_cppc_get_scaling(int cpu)
525{
526 return core_get_scaling();
527}
5906056e 528#endif /* CONFIG_ACPI_CPPC_LIB */
9522a2ff 529
192cdb1c
RW		 530static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
531 unsigned int relation)
532{
533 if (freq == cpu->pstate.turbo_freq)
534 return cpu->pstate.turbo_pstate;
535
536 if (freq == cpu->pstate.max_freq)
537 return cpu->pstate.max_pstate;
538
539 switch (relation) {
540 case CPUFREQ_RELATION_H:
541 return freq / cpu->pstate.scaling;
542 case CPUFREQ_RELATION_C:
543 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
544 }
545
546 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
547}
548
549static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
550{
551 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
552}
553
eb3693f0 554/**
46573fd6 555 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
eb3693f0
RW		 556 * @cpu: Target CPU.
557 *
558 * On hybrid processors, HWP may expose more performance levels than there are
559 * P-states accessible through the PERF_CTL interface. If that happens, the
560 * scaling factor between HWP performance levels and CPU frequency will be less
561 * than the scaling factor between P-state values and CPU frequency.
562 *
46573fd6 563 * In that case, adjust the CPU parameters used in computations accordingly.
eb3693f0 564 */
46573fd6 565static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
eb3693f0 566{
eb3693f0
RW		 567 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
568 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
8dbab94d 569 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
46573fd6 570 int scaling = cpu->pstate.scaling;
192cdb1c 571 int freq;
eb3693f0
RW		 572
573 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
eb3693f0
RW		 574 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
575 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
eb3693f0
RW		 576 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
577 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
46573fd6 578 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
eb3693f0 579
f5c8cf2a
RW		 580 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
581 perf_ctl_scaling);
eb3693f0
RW		 582 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
583 perf_ctl_scaling);
584
192cdb1c
RW		 585 freq = perf_ctl_max_phys * perf_ctl_scaling;
586 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
eb3693f0 587
192cdb1c
RW		 588 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
589 cpu->pstate.min_freq = freq;
eb3693f0
RW		 590 /*
591 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
592 * the effective range of HWP performance levels.
593 */
192cdb1c 594 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
eb3693f0
RW		 595}
596
4521e1a0
GM		 597static inline void update_turbo_state(void)
598{
599 u64 misc_en;
4521e1a0 600
4521e1a0 601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
37b6ddba 602 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
4521e1a0
GM		 603}
604
c5a2ee7d
RW		 605static int min_perf_pct_min(void)
606{
607 struct cpudata *cpu = all_cpu_data[0];
57caf4ec 608 int turbo_pstate = cpu->pstate.turbo_pstate;
c5a2ee7d 609
57caf4ec 610 return turbo_pstate ?
d4436c0d 611 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
c5a2ee7d
RW		 612}
613
8442885f
SP		 614static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
615{
616 u64 epb;
617 int ret;
618
108ec36b 619 if (!boot_cpu_has(X86_FEATURE_EPB))
8442885f
SP		 620 return -ENXIO;
621
622 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
623 if (ret)
624 return (s16)ret;
625
626 return (s16)(epb & 0x0f);
627}
628
629static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
630{
631 s16 epp;
632
108ec36b 633 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
984edbdc
SP		 634 /*
635 * When hwp_req_data is 0, means that caller didn't read
636 * MSR_HWP_REQUEST, so need to read and get EPP.
637 */
638 if (!hwp_req_data) {
639 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
640 &hwp_req_data);
641 if (epp)
642 return epp;
643 }
8442885f 644 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 645 } else {
8442885f
SP		 646 /* When there is no EPP present, HWP uses EPB settings */
647 epp = intel_pstate_get_epb(cpu_data);
984edbdc 648 }
8442885f
SP		 649
650 return epp;
651}
652
984edbdc 653static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 654{
655 u64 epb;
984edbdc 656 int ret;
8442885f 657
108ec36b 658 if (!boot_cpu_has(X86_FEATURE_EPB))
984edbdc 659 return -ENXIO;
8442885f 660
984edbdc
SP		 661 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
662 if (ret)
663 return ret;
8442885f
SP		 664
665 epb = (epb & ~0x0f) | pref;
666 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 667
668 return 0;
8442885f
SP		 669}
670
984edbdc
SP		 671/*
672 * EPP/EPB display strings corresponding to EPP index in the
673 * energy_perf_strings[]
674 * index String
675 *-------------------------------------
676 * 0 default
677 * 1 performance
678 * 2 balance_performance
679 * 3 balance_power
680 * 4 power
681 */
b6e6f8be
SP		 682
683enum energy_perf_value_index {
684 EPP_INDEX_DEFAULT = 0,
685 EPP_INDEX_PERFORMANCE,
686 EPP_INDEX_BALANCE_PERFORMANCE,
687 EPP_INDEX_BALANCE_POWERSAVE,
688 EPP_INDEX_POWERSAVE,
689};
690
984edbdc 691static const char * const energy_perf_strings[] = {
b6e6f8be
SP		 692 [EPP_INDEX_DEFAULT] = "default",
693 [EPP_INDEX_PERFORMANCE] = "performance",
694 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
695 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
696 [EPP_INDEX_POWERSAVE] = "power",
984edbdc
SP		 697 NULL
698};
b6e6f8be
SP		 699static unsigned int epp_values[] = {
700 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
701 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
702 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
703 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
704 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
3cedbc5a 705};
984edbdc 706
f473bf39 707static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
984edbdc
SP		 708{
709 s16 epp;
710 int index = -EINVAL;
711
f473bf39 712 *raw_epp = 0;
984edbdc
SP		 713 epp = intel_pstate_get_epp(cpu_data, 0);
714 if (epp < 0)
715 return epp;
716
108ec36b 717 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
b6e6f8be
SP		 718 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
719 return EPP_INDEX_PERFORMANCE;
720 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
721 return EPP_INDEX_BALANCE_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
723 return EPP_INDEX_BALANCE_POWERSAVE;
724 if (epp == epp_values[EPP_INDEX_POWERSAVE])
725 return EPP_INDEX_POWERSAVE;
f473bf39
SP		 726 *raw_epp = epp;
727 return 0;
108ec36b 728 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
984edbdc
SP		 729 /*
730 * Range:
731 * 0x00-0x03 : Performance
732 * 0x04-0x07 : Balance performance
733 * 0x08-0x0B : Balance power
734 * 0x0C-0x0F : Power
735 * The EPB is a 4 bit value, but our ranges restrict the
736 * value which can be set. Here only using top two bits
737 * effectively.
738 */
739 index = (epp >> 2) + 1;
740 }
741
742 return index;
743}
744
f6ebbcf0
RW		 745static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
746{
c27a0ccc
RW		 747 int ret;
748
f6ebbcf0
RW		 749 /*
750 * Use the cached HWP Request MSR value, because in the active mode the
751 * register itself may be updated by intel_pstate_hwp_boost_up() or
752 * intel_pstate_hwp_boost_down() at any time.
753 */
754 u64 value = READ_ONCE(cpu->hwp_req_cached);
755
756 value &= ~GENMASK_ULL(31, 24);
757 value |= (u64)epp << 24;
758 /*
759 * The only other updater of hwp_req_cached in the active mode,
760 * intel_pstate_hwp_set(), is called under the same lock as this
761 * function, so it cannot run in parallel with the update below.
762 */
763 WRITE_ONCE(cpu->hwp_req_cached, value);
c27a0ccc
RW		 764 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
765 if (!ret)
766 cpu->epp_cached = epp;
767
768 return ret;
f6ebbcf0
RW		 769}
770
984edbdc 771static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
f473bf39
SP		 772 int pref_index, bool use_raw,
773 u32 raw_epp)
984edbdc
SP		 774{
775 int epp = -EINVAL;
776 int ret;
777
778 if (!pref_index)
779 epp = cpu_data->epp_default;
780
108ec36b 781 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
3a957176
RW		 782 if (use_raw)
783 epp = raw_epp;
784 else if (epp == -EINVAL)
b6e6f8be 785 epp = epp_values[pref_index];
984edbdc 786
b388eb58
RW		 787 /*
788 * To avoid confusion, refuse to set EPP to any values different
789 * from 0 (performance) if the current policy is "performance",
790 * because those values would be overridden.
791 */
792 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
793 return -EBUSY;
794
f6ebbcf0 795 ret = intel_pstate_set_epp(cpu_data, epp);
984edbdc
SP		 796 } else {
797 if (epp == -EINVAL)
798 epp = (pref_index - 1) << 2;
799 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
800 }
984edbdc
SP		 801
802 return ret;
803}
804
805static ssize_t show_energy_performance_available_preferences(
806 struct cpufreq_policy *policy, char *buf)
807{
808 int i = 0;
809 int ret = 0;
810
811 while (energy_perf_strings[i] != NULL)
812 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
813
814 ret += sprintf(&buf[ret], "\n");
815
816 return ret;
817}
818
819cpufreq_freq_attr_ro(energy_performance_available_preferences);
820
f6ebbcf0
RW		 821static struct cpufreq_driver intel_pstate;
822
984edbdc
SP		 823static ssize_t store_energy_performance_preference(
824 struct cpufreq_policy *policy, const char *buf, size_t count)
825{
f6ebbcf0 826 struct cpudata *cpu = all_cpu_data[policy->cpu];
984edbdc 827 char str_preference[21];
f473bf39 828 bool raw = false;
3a957176 829 ssize_t ret;
3ff79754 830 u32 epp = 0;
984edbdc
SP		 831
832 ret = sscanf(buf, "%20s", str_preference);
833 if (ret != 1)
834 return -EINVAL;
835
1111b783 836 ret = match_string(energy_perf_strings, -1, str_preference);
f473bf39
SP		 837 if (ret < 0) {
838 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
839 return ret;
840
841 ret = kstrtouint(buf, 10, &epp);
842 if (ret)
843 return ret;
844
3a957176
RW		 845 if (epp > 255)
846 return -EINVAL;
847
f473bf39
SP		 848 raw = true;
849 }
850
f6ebbcf0
RW		 851 /*
852 * This function runs with the policy R/W semaphore held, which
853 * guarantees that the driver pointer will not change while it is
854 * running.
855 */
856 if (!intel_pstate_driver)
857 return -EAGAIN;
858
3a957176
RW		 859 mutex_lock(&intel_pstate_limits_lock);
860
f6ebbcf0
RW		 861 if (intel_pstate_driver == &intel_pstate) {
862 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
863 } else {
864 /*
865 * In the passive mode the governor needs to be stopped on the
866 * target CPU before the EPP update and restarted after it,
867 * which is super-heavy-weight, so make sure it is worth doing
868 * upfront.
869 */
870 if (!raw)
b6e6f8be 871 epp = ret ? epp_values[ret] : cpu->epp_default;
f6ebbcf0
RW		 872
873 if (cpu->epp_cached != epp) {
874 int err;
875
876 cpufreq_stop_governor(policy);
877 ret = intel_pstate_set_epp(cpu, epp);
878 err = cpufreq_start_governor(policy);
c27a0ccc 879 if (!ret)
f6ebbcf0 880 ret = err;
03f44ffb
TK		 881 } else {
882 ret = 0;
f6ebbcf0
RW		 883 }
884 }
3a957176
RW		 885
886 mutex_unlock(&intel_pstate_limits_lock);
984edbdc 887
f6ebbcf0 888 return ret ?: count;
984edbdc
SP		 889}
890
891static ssize_t show_energy_performance_preference(
892 struct cpufreq_policy *policy, char *buf)
893{
894 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
f473bf39 895 int preference, raw_epp;
984edbdc 896
f473bf39 897 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
984edbdc
SP		 898 if (preference < 0)
899 return preference;
900
f473bf39
SP		 901 if (raw_epp)
902 return sprintf(buf, "%d\n", raw_epp);
903 else
904 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
984edbdc
SP		 905}
906
907cpufreq_freq_attr_rw(energy_performance_preference);
908
86d333a8
SP		 909static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
910{
eb3693f0
RW		 911 struct cpudata *cpu = all_cpu_data[policy->cpu];
912 int ratio, freq;
86d333a8 913
8df71a7d 914 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
86d333a8 915 if (ratio <= 0) {
eb3693f0
RW		 916 u64 cap;
917
86d333a8
SP		 918 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
919 ratio = HWP_GUARANTEED_PERF(cap);
920 }
921
eb3693f0
RW		 922 freq = ratio * cpu->pstate.scaling;
923 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
924 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
86d333a8 925
eb3693f0 926 return sprintf(buf, "%d\n", freq);
86d333a8
SP		 927}
928
929cpufreq_freq_attr_ro(base_frequency);
930
984edbdc
SP		 931static struct freq_attr *hwp_cpufreq_attrs[] = {
932 &energy_performance_preference,
933 &energy_performance_available_preferences,
86d333a8 934 &base_frequency,
984edbdc
SP		 935 NULL,
936};
937
de5bcf40 938static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
2f86dc4c 939{
1a4fe38a 940 u64 cap;
74da56ce 941
a45ee4d4
RW		 942 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
943 WRITE_ONCE(cpu->hwp_cap_cached, cap);
de5bcf40
RW		 944 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
945 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
946}
1a4fe38a 947
de5bcf40
RW		 948static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
949{
eb3693f0
RW		 950 int scaling = cpu->pstate.scaling;
951
de5bcf40 952 __intel_pstate_get_hwp_cap(cpu);
eb3693f0
RW		 953
954 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
955 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
956 if (scaling != cpu->pstate.perf_ctl_scaling) {
957 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
958
959 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
960 perf_ctl_scaling);
961 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
962 perf_ctl_scaling);
963 }
1a4fe38a
SP		 964}
965
966static void intel_pstate_hwp_set(unsigned int cpu)
967{
968 struct cpudata *cpu_data = all_cpu_data[cpu];
969 int max, min;
970 u64 value;
971 s16 epp;
972
973 max = cpu_data->max_perf_ratio;
974 min = cpu_data->min_perf_ratio;
eae48f04 975
2bfc4cbb
RW		 976 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
977 min = max;
3f8ed54a 978
2bfc4cbb 979 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
2f86dc4c 980
2bfc4cbb
RW		 981 value &= ~HWP_MIN_PERF(~0L);
982 value |= HWP_MIN_PERF(min);
8442885f 983
2bfc4cbb
RW		 984 value &= ~HWP_MAX_PERF(~0L);
985 value |= HWP_MAX_PERF(max);
8442885f 986
2bfc4cbb
RW		 987 if (cpu_data->epp_policy == cpu_data->policy)
988 goto skip_epp;
8442885f 989
2bfc4cbb 990 cpu_data->epp_policy = cpu_data->policy;
984edbdc 991
2bfc4cbb
RW		 992 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
993 epp = intel_pstate_get_epp(cpu_data, value);
994 cpu_data->epp_powersave = epp;
995 /* If EPP read was failed, then don't try to write */
996 if (epp < 0)
997 goto skip_epp;
8442885f 998
2bfc4cbb
RW		 999 epp = 0;
1000 } else {
1001 /* skip setting EPP, when saved value is invalid */
1002 if (cpu_data->epp_powersave < 0)
1003 goto skip_epp;
8442885f 1004
2bfc4cbb
RW		 1005 /*
1006 * No need to restore EPP when it is not zero. This
1007 * means:
1008 * - Policy is not changed
1009 * - user has manually changed
1010 * - Error reading EPB
1011 */
1012 epp = intel_pstate_get_epp(cpu_data, value);
1013 if (epp)
1014 goto skip_epp;
8442885f 1015
2bfc4cbb
RW		 1016 epp = cpu_data->epp_powersave;
1017 }
108ec36b 1018 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
2bfc4cbb
RW		 1019 value &= ~GENMASK_ULL(31, 24);
1020 value |= (u64)epp << 24;
1021 } else {
1022 intel_pstate_set_epb(cpu, epp);
2f86dc4c 1023 }
2bfc4cbb 1024skip_epp:
e0efd5be 1025 WRITE_ONCE(cpu_data->hwp_req_cached, value);
2bfc4cbb 1026 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
41cfd64c 1027}
2f86dc4c 1028
57577c99
SP		 1029static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1030
4adcf2e5 1031static void intel_pstate_hwp_offline(struct cpudata *cpu)
af3b7379 1032{
4adcf2e5 1033 u64 value = READ_ONCE(cpu->hwp_req_cached);
af3b7379
SP		 1034 int min_perf;
1035
57577c99
SP		 1036 intel_pstate_disable_hwp_interrupt(cpu);
1037
4adcf2e5
RW		 1038 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1039 /*
1040 * In case the EPP has been set to "performance" by the
1041 * active mode "performance" scaling algorithm, replace that
1042 * temporary value with the cached EPP one.
1043 */
1044 value &= ~GENMASK_ULL(31, 24);
1045 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
ed38eb49
RW		 1046 /*
1047 * However, make sure that EPP will be set to "performance" when
1048 * the CPU is brought back online again and the "performance"
1049 * scaling algorithm is still in effect.
1050 */
1051 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
4adcf2e5
RW		 1052 }
1053
dbea75fe
RW		 1054 /*
1055 * Clear the desired perf field in the cached HWP request value to
1056 * prevent nonzero desired values from being leaked into the active
1057 * mode.
1058 */
1059 value &= ~HWP_DESIRED_PERF(~0L);
1060 WRITE_ONCE(cpu->hwp_req_cached, value);
1061
af3b7379 1062 value &= ~GENMASK_ULL(31, 0);
9dd04ec6 1063 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
af3b7379
SP		 1064
1065 /* Set hwp_max = hwp_min */
1066 value |= HWP_MAX_PERF(min_perf);
1067 value |= HWP_MIN_PERF(min_perf);
1068
c31432fa 1069 /* Set EPP to min */
108ec36b 1070 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
af3b7379 1071 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
af3b7379 1072
4adcf2e5 1073 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
984edbdc
SP		 1074}
1075
ed7bde7a
SP		 1076#define POWER_CTL_EE_ENABLE 1
1077#define POWER_CTL_EE_DISABLE 2
1078
1079static int power_ctl_ee_state;
1080
1081static void set_power_ctl_ee_state(bool input)
1082{
1083 u64 power_ctl;
1084
1085 mutex_lock(&intel_pstate_driver_lock);
1086 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1087 if (input) {
1088 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1089 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1090 } else {
1091 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1092 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1093 }
1094 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1095 mutex_unlock(&intel_pstate_driver_lock);
1096}
1097
70f6bf2a
CY		 1098static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1099
4adcf2e5
RW		 1100static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1101{
1102 intel_pstate_hwp_enable(cpu);
1103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1104}
1105
1106static int intel_pstate_suspend(struct cpufreq_policy *policy)
1107{
1108 struct cpudata *cpu = all_cpu_data[policy->cpu];
1109
1110 pr_debug("CPU %d suspending\n", cpu->cpu);
1111
1112 cpu->suspended = true;
1113
57577c99
SP		 1114 /* disable HWP interrupt and cancel any pending work */
1115 intel_pstate_disable_hwp_interrupt(cpu);
1116
4adcf2e5
RW		 1117 return 0;
1118}
1119
8442885f
SP		 1120static int intel_pstate_resume(struct cpufreq_policy *policy)
1121{
4adcf2e5
RW		 1122 struct cpudata *cpu = all_cpu_data[policy->cpu];
1123
1124 pr_debug("CPU %d resuming\n", cpu->cpu);
ed7bde7a
SP		 1125
1126 /* Only restore if the system default is changed */
1127 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1128 set_power_ctl_ee_state(true);
1129 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1130 set_power_ctl_ee_state(false);
1131
4adcf2e5
RW		 1132 if (cpu->suspended && hwp_active) {
1133 mutex_lock(&intel_pstate_limits_lock);
8442885f 1134
4adcf2e5
RW		 1135 /* Re-enable HWP, because "online" has not done that. */
1136 intel_pstate_hwp_reenable(cpu);
70f6bf2a 1137
4adcf2e5
RW		 1138 mutex_unlock(&intel_pstate_limits_lock);
1139 }
aa439248 1140
4adcf2e5 1141 cpu->suspended = false;
aa439248 1142
5f98ced1 1143 return 0;
8442885f
SP		 1144}
1145
111b8b3f 1146static void intel_pstate_update_policies(void)
41cfd64c 1147{
111b8b3f
RW		 1148 int cpu;
1149
1150 for_each_possible_cpu(cpu)
1151 cpufreq_update_policy(cpu);
2f86dc4c
DB		 1152}
1153
dfeeedc1
RW		 1154static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1155 struct cpufreq_policy *policy)
1156{
1157 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1158 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1159 refresh_frequency_limits(policy);
1160}
1161
9083e498
RW		 1162static void intel_pstate_update_max_freq(unsigned int cpu)
1163{
1164 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
9083e498
RW		 1165
1166 if (!policy)
1167 return;
1168
dfeeedc1 1169 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
9083e498
RW		 1170
1171 cpufreq_cpu_release(policy);
1172}
1173
5a25e3f7
RW		 1174static void intel_pstate_update_limits(unsigned int cpu)
1175{
1176 mutex_lock(&intel_pstate_driver_lock);
1177
1178 update_turbo_state();
1179 /*
1180 * If turbo has been turned on or off globally, policy limits for
1181 * all CPUs need to be updated to reflect that.
1182 */
9083e498
RW		 1183 if (global.turbo_disabled_mf != global.turbo_disabled) {
1184 global.turbo_disabled_mf = global.turbo_disabled;
918229cd 1185 arch_set_max_freq_ratio(global.turbo_disabled);
9083e498
RW		 1186 for_each_possible_cpu(cpu)
1187 intel_pstate_update_max_freq(cpu);
5a25e3f7
RW		 1188 } else {
1189 cpufreq_update_policy(cpu);
1190 }
1191
1192 mutex_unlock(&intel_pstate_driver_lock);
1193}
1194
93f0822d
DB		 1195/************************** sysfs begin ************************/
1196#define show_one(file_name, object) \
1197 static ssize_t show_##file_name \
625c85a6 1198 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
93f0822d 1199 { \
7de32556 1200 return sprintf(buf, "%u\n", global.object); \
93f0822d
DB		 1201 }
1202
fb1fe104
RW		 1203static ssize_t intel_pstate_show_status(char *buf);
1204static int intel_pstate_update_status(const char *buf, size_t size);
1205
1206static ssize_t show_status(struct kobject *kobj,
625c85a6 1207 struct kobj_attribute *attr, char *buf)
fb1fe104
RW		 1208{
1209 ssize_t ret;
1210
1211 mutex_lock(&intel_pstate_driver_lock);
1212 ret = intel_pstate_show_status(buf);
1213 mutex_unlock(&intel_pstate_driver_lock);
1214
1215 return ret;
1216}
1217
625c85a6 1218static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
fb1fe104
RW		 1219 const char *buf, size_t count)
1220{
1221 char *p = memchr(buf, '\n', count);
1222 int ret;
1223
1224 mutex_lock(&intel_pstate_driver_lock);
1225 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1226 mutex_unlock(&intel_pstate_driver_lock);
1227
1228 return ret < 0 ? ret : count;
1229}
1230
d01b1f48 1231static ssize_t show_turbo_pct(struct kobject *kobj,
625c85a6 1232 struct kobj_attribute *attr, char *buf)
d01b1f48
KCA		 1233{
1234 struct cpudata *cpu;
1235 int total, no_turbo, turbo_pct;
1236 uint32_t turbo_fp;
1237
0c30b65b
RW		 1238 mutex_lock(&intel_pstate_driver_lock);
1239
ee8df89a 1240 if (!intel_pstate_driver) {
0c30b65b
RW		 1241 mutex_unlock(&intel_pstate_driver_lock);
1242 return -EAGAIN;
1243 }
1244
d01b1f48
KCA		 1245 cpu = all_cpu_data[0];
1246
1247 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1248 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 1249 turbo_fp = div_fp(no_turbo, total);
d01b1f48 1250 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 1251
1252 mutex_unlock(&intel_pstate_driver_lock);
1253
d01b1f48
KCA		 1254 return sprintf(buf, "%u\n", turbo_pct);
1255}
1256
0522424e 1257static ssize_t show_num_pstates(struct kobject *kobj,
625c85a6 1258 struct kobj_attribute *attr, char *buf)
0522424e
KCA		 1259{
1260 struct cpudata *cpu;
1261 int total;
1262
0c30b65b
RW		 1263 mutex_lock(&intel_pstate_driver_lock);
1264
ee8df89a 1265 if (!intel_pstate_driver) {
0c30b65b
RW		 1266 mutex_unlock(&intel_pstate_driver_lock);
1267 return -EAGAIN;
1268 }
1269
0522424e
KCA		 1270 cpu = all_cpu_data[0];
1271 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 1272
1273 mutex_unlock(&intel_pstate_driver_lock);
1274
0522424e
KCA		 1275 return sprintf(buf, "%u\n", total);
1276}
1277
4521e1a0 1278static ssize_t show_no_turbo(struct kobject *kobj,
625c85a6 1279 struct kobj_attribute *attr, char *buf)
4521e1a0
GM		 1280{
1281 ssize_t ret;
1282
0c30b65b
RW		 1283 mutex_lock(&intel_pstate_driver_lock);
1284
ee8df89a 1285 if (!intel_pstate_driver) {
0c30b65b
RW		 1286 mutex_unlock(&intel_pstate_driver_lock);
1287 return -EAGAIN;
1288 }
1289
4521e1a0 1290 update_turbo_state();
7de32556
RW		 1291 if (global.turbo_disabled)
1292 ret = sprintf(buf, "%u\n", global.turbo_disabled);
4521e1a0 1293 else
7de32556 1294 ret = sprintf(buf, "%u\n", global.no_turbo);
4521e1a0 1295
0c30b65b
RW		 1296 mutex_unlock(&intel_pstate_driver_lock);
1297
4521e1a0
GM		 1298 return ret;
1299}
1300
625c85a6 1301static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
c410833a 1302 const char *buf, size_t count)
93f0822d
DB		 1303{
1304 unsigned int input;
1305 int ret;
845c1cbe 1306
93f0822d
DB		 1307 ret = sscanf(buf, "%u", &input);
1308 if (ret != 1)
1309 return -EINVAL;
4521e1a0 1310
0c30b65b
RW		 1311 mutex_lock(&intel_pstate_driver_lock);
1312
ee8df89a 1313 if (!intel_pstate_driver) {
0c30b65b
RW		 1314 mutex_unlock(&intel_pstate_driver_lock);
1315 return -EAGAIN;
1316 }
1317
a410c03d
SP		 1318 mutex_lock(&intel_pstate_limits_lock);
1319
4521e1a0 1320 update_turbo_state();
7de32556 1321 if (global.turbo_disabled) {
8c539776 1322 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 1323 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 1324 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 1325 return -EPERM;
dd5fbf70 1326 }
2f86dc4c 1327
7de32556 1328 global.no_turbo = clamp_t(int, input, 0, 1);
111b8b3f 1329
c5a2ee7d
RW		 1330 if (global.no_turbo) {
1331 struct cpudata *cpu = all_cpu_data[0];
1332 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1333
1334 /* Squash the global minimum into the permitted range. */
1335 if (global.min_perf_pct > pct)
1336 global.min_perf_pct = pct;
1337 }
1338
cd59b4be
RW		 1339 mutex_unlock(&intel_pstate_limits_lock);
1340
7de32556 1341 intel_pstate_update_policies();
addca285 1342 arch_set_max_freq_ratio(global.no_turbo);
7de32556 1343
0c30b65b
RW		 1344 mutex_unlock(&intel_pstate_driver_lock);
1345
93f0822d
DB		 1346 return count;
1347}
1348
3000ce3c 1349static void update_qos_request(enum freq_qos_req_type type)
da5c504c 1350{
3000ce3c 1351 struct freq_qos_request *req;
da5c504c 1352 struct cpufreq_policy *policy;
de5bcf40 1353 int i;
da5c504c
VK		 1354
1355 for_each_possible_cpu(i) {
1356 struct cpudata *cpu = all_cpu_data[i];
de5bcf40 1357 unsigned int freq, perf_pct;
da5c504c
VK		 1358
1359 policy = cpufreq_cpu_get(i);
1360 if (!policy)
1361 continue;
1362
1363 req = policy->driver_data;
1364 cpufreq_cpu_put(policy);
1365
1366 if (!req)
1367 continue;
1368
1369 if (hwp_active)
de5bcf40 1370 intel_pstate_get_hwp_cap(cpu);
da5c504c 1371
3000ce3c 1372 if (type == FREQ_QOS_MIN) {
da5c504c
VK		 1373 perf_pct = global.min_perf_pct;
1374 } else {
1375 req++;
1376 perf_pct = global.max_perf_pct;
1377 }
1378
de5bcf40 1379 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
da5c504c 1380
3000ce3c 1381 if (freq_qos_update_request(req, freq) < 0)
da5c504c
VK		 1382 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1383 }
1384}
1385
625c85a6 1386static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
c410833a 1387 const char *buf, size_t count)
93f0822d
DB		 1388{
1389 unsigned int input;
1390 int ret;
845c1cbe 1391
93f0822d
DB		 1392 ret = sscanf(buf, "%u", &input);
1393 if (ret != 1)
1394 return -EINVAL;
1395
0c30b65b
RW		 1396 mutex_lock(&intel_pstate_driver_lock);
1397
ee8df89a 1398 if (!intel_pstate_driver) {
0c30b65b
RW		 1399 mutex_unlock(&intel_pstate_driver_lock);
1400 return -EAGAIN;
1401 }
1402
a410c03d
SP		 1403 mutex_lock(&intel_pstate_limits_lock);
1404
c5a2ee7d 1405 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
111b8b3f 1406
cd59b4be
RW		 1407 mutex_unlock(&intel_pstate_limits_lock);
1408
da5c504c
VK		 1409 if (intel_pstate_driver == &intel_pstate)
1410 intel_pstate_update_policies();
1411 else
3000ce3c 1412 update_qos_request(FREQ_QOS_MAX);
7de32556 1413
0c30b65b
RW		 1414 mutex_unlock(&intel_pstate_driver_lock);
1415
93f0822d
DB		 1416 return count;
1417}
1418
625c85a6 1419static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
c410833a 1420 const char *buf, size_t count)
93f0822d
DB		 1421{
1422 unsigned int input;
1423 int ret;
845c1cbe 1424
93f0822d
DB		 1425 ret = sscanf(buf, "%u", &input);
1426 if (ret != 1)
1427 return -EINVAL;
a0475992 1428
0c30b65b
RW		 1429 mutex_lock(&intel_pstate_driver_lock);
1430
ee8df89a 1431 if (!intel_pstate_driver) {
0c30b65b
RW		 1432 mutex_unlock(&intel_pstate_driver_lock);
1433 return -EAGAIN;
1434 }
1435
a410c03d
SP		 1436 mutex_lock(&intel_pstate_limits_lock);
1437
c5a2ee7d
RW		 1438 global.min_perf_pct = clamp_t(int, input,
1439 min_perf_pct_min(), global.max_perf_pct);
111b8b3f 1440
cd59b4be
RW		 1441 mutex_unlock(&intel_pstate_limits_lock);
1442
da5c504c
VK		 1443 if (intel_pstate_driver == &intel_pstate)
1444 intel_pstate_update_policies();
1445 else
3000ce3c 1446 update_qos_request(FREQ_QOS_MIN);
7de32556 1447
0c30b65b
RW		 1448 mutex_unlock(&intel_pstate_driver_lock);
1449
93f0822d
DB		 1450 return count;
1451}
1452
aaaece3d 1453static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
625c85a6 1454 struct kobj_attribute *attr, char *buf)
aaaece3d
SP		 1455{
1456 return sprintf(buf, "%u\n", hwp_boost);
1457}
1458
625c85a6
VK		 1459static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1460 struct kobj_attribute *b,
aaaece3d
SP		 1461 const char *buf, size_t count)
1462{
1463 unsigned int input;
1464 int ret;
1465
1466 ret = kstrtouint(buf, 10, &input);
1467 if (ret)
1468 return ret;
1469
1470 mutex_lock(&intel_pstate_driver_lock);
1471 hwp_boost = !!input;
1472 intel_pstate_update_policies();
1473 mutex_unlock(&intel_pstate_driver_lock);
1474
1475 return count;
1476}
1477
ed7bde7a
SP		 1478static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1479 char *buf)
1480{
1481 u64 power_ctl;
1482 int enable;
1483
1484 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1485 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1486 return sprintf(buf, "%d\n", !enable);
1487}
1488
1489static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1490 const char *buf, size_t count)
1491{
1492 bool input;
1493 int ret;
1494
1495 ret = kstrtobool(buf, &input);
1496 if (ret)
1497 return ret;
1498
1499 set_power_ctl_ee_state(input);
1500
1501 return count;
1502}
1503
93f0822d
DB		 1504show_one(max_perf_pct, max_perf_pct);
1505show_one(min_perf_pct, min_perf_pct);
1506
fb1fe104 1507define_one_global_rw(status);
93f0822d
DB		 1508define_one_global_rw(no_turbo);
1509define_one_global_rw(max_perf_pct);
1510define_one_global_rw(min_perf_pct);
d01b1f48 1511define_one_global_ro(turbo_pct);
0522424e 1512define_one_global_ro(num_pstates);
aaaece3d 1513define_one_global_rw(hwp_dynamic_boost);
ed7bde7a 1514define_one_global_rw(energy_efficiency);
93f0822d
DB		 1515
1516static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1517 &status.attr,
93f0822d 1518 &no_turbo.attr,
93f0822d
DB		 1519 NULL
1520};
1521
106c9c77 1522static const struct attribute_group intel_pstate_attr_group = {
93f0822d
DB		 1523 .attrs = intel_pstate_attributes,
1524};
93f0822d 1525
ed7bde7a
SP		 1526static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1527
f6ebbcf0
RW		 1528static struct kobject *intel_pstate_kobject;
1529
317dd50e 1530static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1531{
2744a63c 1532 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
93f0822d
DB		 1533 int rc;
1534
2744a63c
GKH		 1535 if (dev_root) {
1536 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1537 put_device(dev_root);
1538 }
eae48f04
SP		 1539 if (WARN_ON(!intel_pstate_kobject))
1540 return;
1541
2d8d1f18 1542 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1543 if (WARN_ON(rc))
1544 return;
1545
c3d175e4
RW		 1546 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1547 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1548 WARN_ON(rc);
1549
1550 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1551 WARN_ON(rc);
1552 }
1553
eae48f04
SP		 1554 /*
1555 * If per cpu limits are enforced there are no global limits, so
1556 * return without creating max/min_perf_pct attributes
1557 */
1558 if (per_cpu_limits)
1559 return;
1560
1561 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1562 WARN_ON(rc);
1563
1564 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1565 WARN_ON(rc);
1566
ed7bde7a
SP		 1567 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1568 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1569 WARN_ON(rc);
1570 }
93f0822d 1571}
f6ebbcf0 1572
cdc1719c
CY		 1573static void __init intel_pstate_sysfs_remove(void)
1574{
1575 if (!intel_pstate_kobject)
1576 return;
1577
1578 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1579
c3d175e4
RW		 1580 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1581 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1582 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1583 }
1584
cdc1719c
CY		 1585 if (!per_cpu_limits) {
1586 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1587 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1588
1589 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1590 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1591 }
1592
1593 kobject_put(intel_pstate_kobject);
1594}
1595
f6ebbcf0
RW		 1596static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1597{
1598 int rc;
1599
1600 if (!hwp_active)
1601 return;
1602
1603 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1604 WARN_ON_ONCE(rc);
1605}
1606
1607static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1608{
1609 if (!hwp_active)
1610 return;
1611
1612 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1613}
1614
93f0822d 1615/************************** sysfs end ************************/
2f86dc4c 1616
57577c99
SP		 1617static void intel_pstate_notify_work(struct work_struct *work)
1618{
1619 struct cpudata *cpudata =
1620 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
dfeeedc1
RW		 1621 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1622
1623 if (policy) {
1624 intel_pstate_get_hwp_cap(cpudata);
1625 __intel_pstate_update_max_freq(cpudata, policy);
1626
1627 cpufreq_cpu_release(policy);
1628 }
57577c99 1629
57577c99
SP		 1630 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1631}
1632
1633static DEFINE_SPINLOCK(hwp_notify_lock);
1634static cpumask_t hwp_intr_enable_mask;
1635
1636void notify_hwp_interrupt(void)
1637{
1638 unsigned int this_cpu = smp_processor_id();
1639 struct cpudata *cpudata;
1640 unsigned long flags;
1641 u64 value;
1642
1643 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1644 return;
1645
1646 rdmsrl_safe(MSR_HWP_STATUS, &value);
1647 if (!(value & 0x01))
1648 return;
1649
1650 spin_lock_irqsave(&hwp_notify_lock, flags);
1651
1652 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1653 goto ack_intr;
1654
1655 /*
1656 * Currently we never free all_cpu_data. And we can't reach here
1657 * without this allocated. But for safety for future changes, added
1658 * check.
1659 */
1660 if (unlikely(!READ_ONCE(all_cpu_data)))
1661 goto ack_intr;
1662
1663 /*
1664 * The free is done during cleanup, when cpufreq registry is failed.
1665 * We wouldn't be here if it fails on init or switch status. But for
1666 * future changes, added check.
1667 */
1668 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1669 if (unlikely(!cpudata))
1670 goto ack_intr;
1671
1672 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1673
1674 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1675
1676 return;
1677
1678ack_intr:
1679 wrmsrl_safe(MSR_HWP_STATUS, 0);
1680 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1681}
1682
1683static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1684{
1685 unsigned long flags;
1686
55210556
SP		 1687 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1688 return;
1689
57577c99
SP		 1690 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1691 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1692
1693 spin_lock_irqsave(&hwp_notify_lock, flags);
1694 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1695 cancel_delayed_work(&cpudata->hwp_notify_work);
1696 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1697}
1698
1699static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1700{
1701 /* Enable HWP notification interrupt for guaranteed performance change */
1702 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1703 unsigned long flags;
1704
1705 spin_lock_irqsave(&hwp_notify_lock, flags);
1706 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1707 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1708 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1709
1710 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1711 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
074d0cdf 1712 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
57577c99
SP		 1713 }
1714}
1715
3d13058e
SP		 1716static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1717{
1718 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1719
3d13058e 1720 /*
21cdb6c1
SP		 1721 * If the EPP is set by firmware, which means that firmware enabled HWP
1722 * - Is equal or less than 0x80 (default balance_perf EPP)
3d13058e
SP		 1723 * - But less performance oriented than performance EPP
1724 * then use this as new balance_perf EPP.
1725 */
21cdb6c1 1726 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
3d13058e
SP		 1727 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1728 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1729 return;
1730 }
1731
2719675f
SP		 1732 /*
1733 * If this CPU gen doesn't call for change in balance_perf
1734 * EPP return.
1735 */
1736 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1737 return;
1738
3d13058e
SP		 1739 /*
1740 * Use hard coded value per gen to update the balance_perf
1741 * and default EPP.
1742 */
1743 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1744 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1745}
1746
ba88d433 1747static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1748{
57577c99 1749 /* First disable HWP notification interrupt till we activate again */
108ec36b 1750 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
da7de91c 1751 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1752
ba88d433 1753 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
57577c99
SP		 1754
1755 intel_pstate_enable_hwp_interrupt(cpudata);
b6e6f8be
SP		 1756
1757 if (cpudata->epp_default >= 0)
1758 return;
1759
3d13058e 1760 intel_pstate_update_epp_defaults(cpudata);
2f86dc4c
DB		 1761}
1762
8dbab94d 1763static int atom_get_min_pstate(int not_used)
19e77c28
DB		 1764{
1765 u64 value;
845c1cbe 1766
92134bdb 1767 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1768 return (value >> 8) & 0x7F;
19e77c28
DB		 1769}
1770
8dbab94d 1771static int atom_get_max_pstate(int not_used)
19e77c28
DB		 1772{
1773 u64 value;
845c1cbe 1774
92134bdb 1775 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1776 return (value >> 16) & 0x7F;
19e77c28 1777}
93f0822d 1778
8dbab94d 1779static int atom_get_turbo_pstate(int not_used)
61d8d2ab
DB		 1780{
1781 u64 value;
845c1cbe 1782
92134bdb 1783 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1784 return value & 0x7F;
61d8d2ab
DB		 1785}
1786
fdfdb2b1 1787static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1788{
1789 u64 val;
1790 int32_t vid_fp;
1791 u32 vid;
1792
144c8e17 1793 val = (u64)pstate << 8;
7de32556 1794 if (global.no_turbo && !global.turbo_disabled)
007bea09
DB		 1795 val |= (u64)1 << 32;
1796
1797 vid_fp = cpudata->vid.min + mul_fp(
1798 int_tofp(pstate - cpudata->pstate.min_pstate),
1799 cpudata->vid.ratio);
1800
1801 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1802 vid = ceiling_fp(vid_fp);
007bea09 1803
21855ff5
DB		 1804 if (pstate > cpudata->pstate.max_pstate)
1805 vid = cpudata->vid.turbo;
1806
fdfdb2b1 1807 return val | vid;
007bea09
DB		 1808}
1809
1421df63 1810static int silvermont_get_scaling(void)
b27580b0
DB		 1811{
1812 u64 value;
1813 int i;
1421df63
PL		 1814 /* Defined in Table 35-6 from SDM (Sept 2015) */
1815 static int silvermont_freq_table[] = {
1816 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1817
1818 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1819 i = value & 0x7;
1820 WARN_ON(i > 4);
b27580b0 1821
1421df63
PL		 1822 return silvermont_freq_table[i];
1823}
b27580b0 1824
1421df63
PL		 1825static int airmont_get_scaling(void)
1826{
1827 u64 value;
1828 int i;
1829 /* Defined in Table 35-10 from SDM (Sept 2015) */
1830 static int airmont_freq_table[] = {
1831 83300, 100000, 133300, 116700, 80000,
1832 93300, 90000, 88900, 87500};
1833
1834 rdmsrl(MSR_FSB_FREQ, value);
1835 i = value & 0xF;
1836 WARN_ON(i > 8);
1837
1838 return airmont_freq_table[i];
b27580b0
DB		 1839}
1840
938d21a2 1841static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1842{
1843 u64 value;
1844
92134bdb 1845 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1846 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1847 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1848 cpudata->vid.ratio = div_fp(
1849 cpudata->vid.max - cpudata->vid.min,
1850 int_tofp(cpudata->pstate.max_pstate -
1851 cpudata->pstate.min_pstate));
21855ff5 1852
92134bdb 1853 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1854 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1855}
1856
8dbab94d 1857static int core_get_min_pstate(int cpu)
93f0822d
DB		 1858{
1859 u64 value;
845c1cbe 1860
8dbab94d 1861 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
93f0822d
DB		 1862 return (value >> 40) & 0xFF;
1863}
1864
8dbab94d 1865static int core_get_max_pstate_physical(int cpu)
93f0822d
DB		 1866{
1867 u64 value;
845c1cbe 1868
8dbab94d 1869 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
93f0822d
DB		 1870 return (value >> 8) & 0xFF;
1871}
1872
8dbab94d 1873static int core_get_tdp_ratio(int cpu, u64 plat_info)
8fc7554a
SP		 1874{
1875 /* Check how many TDP levels present */
1876 if (plat_info & 0x600000000) {
1877 u64 tdp_ctrl;
1878 u64 tdp_ratio;
1879 int tdp_msr;
1880 int err;
1881
1882 /* Get the TDP level (0, 1, 2) to get ratios */
8dbab94d 1883 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
8fc7554a
SP		 1884 if (err)
1885 return err;
1886
1887 /* TDP MSR are continuous starting at 0x648 */
1888 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
8dbab94d 1889 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
8fc7554a
SP		 1890 if (err)
1891 return err;
1892
1893 /* For level 1 and 2, bits[23:16] contain the ratio */
1894 if (tdp_ctrl & 0x03)
1895 tdp_ratio >>= 16;
1896
1897 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1898 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1899
1900 return (int)tdp_ratio;
1901 }
1902
1903 return -ENXIO;
1904}
1905
8dbab94d 1906static int core_get_max_pstate(int cpu)
93f0822d 1907{
6a35fc2d
SP		 1908 u64 tar;
1909 u64 plat_info;
1910 int max_pstate;
8fc7554a 1911 int tdp_ratio;
6a35fc2d
SP		 1912 int err;
1913
8dbab94d 1914 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
6a35fc2d
SP		 1915 max_pstate = (plat_info >> 8) & 0xFF;
1916
8dbab94d 1917 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
8fc7554a
SP		 1918 if (tdp_ratio <= 0)
1919 return max_pstate;
1920
1921 if (hwp_active) {
1922 /* Turbo activation ratio is not used on HWP platforms */
1923 return tdp_ratio;
1924 }
1925
8dbab94d 1926 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
6a35fc2d 1927 if (!err) {
8fc7554a
SP		 1928 int tar_levels;
1929
6a35fc2d 1930 /* Do some sanity checking for safety */
8fc7554a
SP		 1931 tar_levels = tar & 0xff;
1932 if (tdp_ratio - 1 == tar_levels) {
1933 max_pstate = tar_levels;
1934 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1935 }
1936 }
845c1cbe 1937
6a35fc2d 1938 return max_pstate;
93f0822d
DB		 1939}
1940
8dbab94d 1941static int core_get_turbo_pstate(int cpu)
93f0822d
DB		 1942{
1943 u64 value;
1944 int nont, ret;
845c1cbe 1945
8dbab94d
RW		 1946 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1947 nont = core_get_max_pstate(cpu);
285cb990 1948 ret = (value) & 255;
93f0822d
DB		 1949 if (ret <= nont)
1950 ret = nont;
1951 return ret;
1952}
1953
fdfdb2b1 1954static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1955{
1956 u64 val;
1957
144c8e17 1958 val = (u64)pstate << 8;
7de32556 1959 if (global.no_turbo && !global.turbo_disabled)
016c8150
DB		 1960 val |= (u64)1 << 32;
1961
fdfdb2b1 1962 return val;
016c8150
DB		 1963}
1964
6e34e1f2
SP		 1965static int knl_get_aperf_mperf_shift(void)
1966{
1967 return 10;
1968}
1969
8dbab94d 1970static int knl_get_turbo_pstate(int cpu)
b34ef932
DC		 1971{
1972 u64 value;
1973 int nont, ret;
1974
8dbab94d
RW		 1975 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1976 nont = core_get_max_pstate(cpu);
b34ef932
DC		 1977 ret = (((value) >> 8) & 0xFF);
1978 if (ret <= nont)
1979 ret = nont;
1980 return ret;
1981}
1982
f5c8cf2a 1983static void hybrid_get_type(void *data)
46573fd6 1984{
f5c8cf2a
RW		 1985 u8 *cpu_type = data;
1986
1987 *cpu_type = get_this_hybrid_cpu_type();
46573fd6
RW		 1988}
1989
0fcfc9e5 1990static int hwp_get_cpu_scaling(int cpu)
46573fd6 1991{
f5c8cf2a 1992 u8 cpu_type = 0;
46573fd6 1993
f5c8cf2a
RW		 1994 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1995 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1996 if (cpu_type == 0x40)
bde4f5ff 1997 return hybrid_scaling_factor;
46573fd6 1998
0fcfc9e5
SP		 1999 /* Use default core scaling for E-cores */
2000 if (cpu_type == 0x20)
2001 return core_get_scaling();
2002
2003 /*
2004 * If reached here, this system is either non-hybrid (like Tiger
2005 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2006 * no E cores (in which case CPUID for hybrid support is 0).
2007 *
2008 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2009 * so the default core scaling will be used for them.
2010 */
2011 return intel_pstate_cppc_get_scaling(cpu);
46573fd6 2012}
46573fd6 2013
a6c6ead1 2014static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 2015{
bc95a454
RW		 2016 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2017 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 2018 /*
2019 * Generally, there is no guarantee that this code will always run on
2020 * the CPU being updated, so force the register update to run on the
2021 * right CPU.
2022 */
2023 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2024 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 2025}
2026
a6c6ead1
RW		 2027static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2028{
2029 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2030}
2031
2032static void intel_pstate_max_within_limits(struct cpudata *cpu)
2033{
fa93b51c 2034 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
a6c6ead1
RW		 2035
2036 update_turbo_state();
b02aabe8 2037 intel_pstate_set_pstate(cpu, pstate);
a6c6ead1
RW		 2038}
2039
93f0822d
DB		 2040static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2041{
8dbab94d 2042 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
46573fd6 2043 int perf_ctl_scaling = pstate_funcs.get_scaling();
eb3693f0 2044
8dbab94d 2045 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
eb3693f0
RW		 2046 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2047 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
ff7c9917
SP		 2048
2049 if (hwp_active && !hwp_mode_bdw) {
de5bcf40 2050 __intel_pstate_get_hwp_cap(cpu);
eb3693f0 2051
46573fd6
RW		 2052 if (pstate_funcs.get_cpu_scaling) {
2053 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2054 if (cpu->pstate.scaling != perf_ctl_scaling)
2055 intel_pstate_hybrid_hwp_adjust(cpu);
2056 } else {
eb3693f0 2057 cpu->pstate.scaling = perf_ctl_scaling;
46573fd6 2058 }
ff7c9917 2059 } else {
eb3693f0 2060 cpu->pstate.scaling = perf_ctl_scaling;
8dbab94d
RW		 2061 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2062 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
ff7c9917 2063 }
de5bcf40 2064
eb3693f0
RW		 2065 if (cpu->pstate.scaling == perf_ctl_scaling) {
2066 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2067 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2068 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2069 }
93f0822d 2070
6e34e1f2
SP		 2071 if (pstate_funcs.get_aperf_mperf_shift)
2072 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2073
007bea09
DB		 2074 if (pstate_funcs.get_vid)
2075 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 2076
2077 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 2078}
2079
e0efd5be
SP		 2080/*
2081 * Long hold time will keep high perf limits for long time,
2082 * which negatively impacts perf/watt for some workloads,
2083 * like specpower. 3ms is based on experiements on some
2084 * workoads.
2085 */
2086static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2087
2088static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2089{
2090 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
9dd04ec6 2091 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
e0efd5be
SP		 2092 u32 max_limit = (hwp_req & 0xff00) >> 8;
2093 u32 min_limit = (hwp_req & 0xff);
2094 u32 boost_level1;
2095
2096 /*
2097 * Cases to consider (User changes via sysfs or boot time):
2098 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2099 * No boost, return.
2100 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2101 * Should result in one level boost only for P0.
2102 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2103 * Should result in two level boost:
2104 * (min + p1)/2 and P1.
2105 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2106 * Should result in three level boost:
2107 * (min + p1)/2, P1 and P0.
2108 */
2109
2110 /* If max and min are equal or already at max, nothing to boost */
2111 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2112 return;
2113
2114 if (!cpu->hwp_boost_min)
2115 cpu->hwp_boost_min = min_limit;
2116
2117 /* level at half way mark between min and guranteed */
9dd04ec6 2118 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
e0efd5be
SP		 2119
2120 if (cpu->hwp_boost_min < boost_level1)
2121 cpu->hwp_boost_min = boost_level1;
9dd04ec6
RW		 2122 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2123 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2124 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2125 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
e0efd5be
SP		 2126 cpu->hwp_boost_min = max_limit;
2127 else
2128 return;
2129
2130 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2131 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2132 cpu->last_update = cpu->sample.time;
2133}
2134
2135static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2136{
2137 if (cpu->hwp_boost_min) {
2138 bool expired;
2139
2140 /* Check if we are idle for hold time to boost down */
2141 expired = time_after64(cpu->sample.time, cpu->last_update +
2142 hwp_boost_hold_time_ns);
2143 if (expired) {
2144 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2145 cpu->hwp_boost_min = 0;
2146 }
2147 }
2148 cpu->last_update = cpu->sample.time;
2149}
2150
52ccc431
SP		 2151static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2152 u64 time)
2153{
2154 cpu->sample.time = time;
2155
2156 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2157 bool do_io = false;
2158
2159 cpu->sched_flags = 0;
2160 /*
2161 * Set iowait_boost flag and update time. Since IO WAIT flag
2162 * is set all the time, we can't just conclude that there is
2163 * some IO bound activity is scheduled on this CPU with just
2164 * one occurrence. If we receive at least two in two
2165 * consecutive ticks, then we treat as boost candidate.
2166 */
2167 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2168 do_io = true;
2169
2170 cpu->last_io_update = time;
2171
2172 if (do_io)
2173 intel_pstate_hwp_boost_up(cpu);
2174
2175 } else {
2176 intel_pstate_hwp_boost_down(cpu);
2177 }
2178}
2179
e0efd5be
SP		 2180static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2181 u64 time, unsigned int flags)
2182{
52ccc431
SP		 2183 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2184
2185 cpu->sched_flags |= flags;
2186
2187 if (smp_processor_id() == cpu->cpu)
2188 intel_pstate_update_util_hwp_local(cpu, time);
e0efd5be
SP		 2189}
2190
a1c9787d 2191static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 2192{
6b17ddb2 2193 struct sample *sample = &cpu->sample;
e66c1768 2194
a1c9787d 2195 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 2196}
2197
4fec7ad5 2198static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 2199{
93f0822d 2200 u64 aperf, mperf;
4ab60c3f 2201 unsigned long flags;
4055fad3 2202 u64 tsc;
93f0822d 2203
4ab60c3f 2204 local_irq_save(flags);
93f0822d
DB		 2205 rdmsrl(MSR_IA32_APERF, aperf);
2206 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 2207 tsc = rdtsc();
4fec7ad5 2208 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 2209 local_irq_restore(flags);
4fec7ad5 2210 return false;
8e601a9f 2211 }
4ab60c3f 2212 local_irq_restore(flags);
b69880f9 2213
c4ee841f 2214 cpu->last_sample_time = cpu->sample.time;
a4675fbc 2215 cpu->sample.time = time;
d37e2b76
DB		 2216 cpu->sample.aperf = aperf;
2217 cpu->sample.mperf = mperf;
4055fad3 2218 cpu->sample.tsc = tsc;
d37e2b76
DB		 2219 cpu->sample.aperf -= cpu->prev_aperf;
2220 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 2221 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 2222
93f0822d
DB		 2223 cpu->prev_aperf = aperf;
2224 cpu->prev_mperf = mperf;
4055fad3 2225 cpu->prev_tsc = tsc;
febce40f
RW		 2226 /*
2227 * First time this function is invoked in a given cycle, all of the
2228 * previous sample data fields are equal to zero or stale and they must
2229 * be populated with meaningful numbers for things to work, so assume
2230 * that sample.time will always be reset before setting the utilization
2231 * update hook and make the caller skip the sample then.
2232 */
eabd22c6
RW		 2233 if (cpu->last_sample_time) {
2234 intel_pstate_calc_avg_perf(cpu);
2235 return true;
2236 }
2237 return false;
93f0822d
DB		 2238}
2239
8fa520af
PL		 2240static inline int32_t get_avg_frequency(struct cpudata *cpu)
2241{
c587c79f 2242 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
8fa520af
PL		 2243}
2244
bdcaa23f
PL		 2245static inline int32_t get_avg_pstate(struct cpudata *cpu)
2246{
8edb0a6e
RW		 2247 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2248 cpu->sample.core_avg_perf);
bdcaa23f
PL		 2249}
2250
d77d4888 2251static inline int32_t get_target_pstate(struct cpudata *cpu)
e70eed2b
PL		 2252{
2253 struct sample *sample = &cpu->sample;
b8bd1581 2254 int32_t busy_frac;
0843e83c 2255 int target, avg_pstate;
e70eed2b 2256
6e34e1f2
SP		 2257 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2258 sample->tsc);
63d1d656 2259
b8bd1581
RW		 2260 if (busy_frac < cpu->iowait_boost)
2261 busy_frac = cpu->iowait_boost;
63d1d656 2262
09c448d3 2263 sample->busy_scaled = busy_frac * 100;
0843e83c 2264
7de32556 2265 target = global.no_turbo || global.turbo_disabled ?
0843e83c
RW		 2266 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2267 target += target >> 2;
2268 target = mul_fp(target, busy_frac);
2269 if (target < cpu->pstate.min_pstate)
2270 target = cpu->pstate.min_pstate;
2271
2272 /*
2273 * If the average P-state during the previous cycle was higher than the
2274 * current target, add 50% of the difference to the target to reduce
2275 * possible performance oscillations and offset possible performance
2276 * loss related to moving the workload from one CPU to another within
2277 * a package/module.
2278 */
2279 avg_pstate = get_avg_pstate(cpu);
2280 if (avg_pstate > target)
2281 target += (avg_pstate - target) >> 1;
2282
2283 return target;
e70eed2b
PL		 2284}
2285
001c76f0 2286static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1 2287{
fa93b51c
RW		 2288 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2289 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
fdfdb2b1 2290
b02aabe8 2291 return clamp_t(int, pstate, min_pstate, max_pstate);
001c76f0
RW		 2292}
2293
2294static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2295{
fdfdb2b1
RW		 2296 if (pstate == cpu->pstate.current_pstate)
2297 return;
2298
bc95a454 2299 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 2300 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2301}
2302
a891283e 2303static void intel_pstate_adjust_pstate(struct cpudata *cpu)
93f0822d 2304{
67dd9bf4 2305 int from = cpu->pstate.current_pstate;
4055fad3 2306 struct sample *sample;
a891283e 2307 int target_pstate;
4055fad3 2308
001c76f0
RW		 2309 update_turbo_state();
2310
d77d4888 2311 target_pstate = get_target_pstate(cpu);
64078299
RW		 2312 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2313 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1 2314 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 2315
2316 sample = &cpu->sample;
a1c9787d 2317 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 2318 fp_toint(sample->busy_scaled),
4055fad3
DS		 2319 from,
2320 cpu->pstate.current_pstate,
2321 sample->mperf,
2322 sample->aperf,
2323 sample->tsc,
3ba7bcaa
SP		 2324 get_avg_frequency(cpu),
2325 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 2326}
2327
a4675fbc 2328static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 2329 unsigned int flags)
93f0822d 2330{
a4675fbc 2331 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 2332 u64 delta_ns;
2333
674e7541
VK		 2334 /* Don't allow remote callbacks */
2335 if (smp_processor_id() != cpu->cpu)
2336 return;
2337
b8bd1581 2338 delta_ns = time - cpu->last_update;
eabd22c6 2339 if (flags & SCHED_CPUFREQ_IOWAIT) {
b8bd1581
RW		 2340 /* Start over if the CPU may have been idle. */
2341 if (delta_ns > TICK_NSEC) {
2342 cpu->iowait_boost = ONE_EIGHTH_FP;
8e3b4039 2343 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
b8bd1581
RW		 2344 cpu->iowait_boost <<= 1;
2345 if (cpu->iowait_boost > int_tofp(1))
2346 cpu->iowait_boost = int_tofp(1);
2347 } else {
2348 cpu->iowait_boost = ONE_EIGHTH_FP;
2349 }
eabd22c6
RW		 2350 } else if (cpu->iowait_boost) {
2351 /* Clear iowait_boost if the CPU may have been idle. */
eabd22c6
RW		 2352 if (delta_ns > TICK_NSEC)
2353 cpu->iowait_boost = 0;
b8bd1581
RW		 2354 else
2355 cpu->iowait_boost >>= 1;
09c448d3 2356 }
eabd22c6 2357 cpu->last_update = time;
09c448d3 2358 delta_ns = time - cpu->sample.time;
d77d4888 2359 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
eabd22c6 2360 return;
4fec7ad5 2361
a891283e
RW		 2362 if (intel_pstate_sample(cpu, time))
2363 intel_pstate_adjust_pstate(cpu);
67dd9bf4 2364}
eabd22c6 2365
2f49afc2
RW		 2366static struct pstate_funcs core_funcs = {
2367 .get_max = core_get_max_pstate,
2368 .get_max_physical = core_get_max_pstate_physical,
2369 .get_min = core_get_min_pstate,
2370 .get_turbo = core_get_turbo_pstate,
2371 .get_scaling = core_get_scaling,
2372 .get_val = core_get_val,
de4a76cb
RW		 2373};
2374
2f49afc2
RW		 2375static const struct pstate_funcs silvermont_funcs = {
2376 .get_max = atom_get_max_pstate,
2377 .get_max_physical = atom_get_max_pstate,
2378 .get_min = atom_get_min_pstate,
2379 .get_turbo = atom_get_turbo_pstate,
2380 .get_val = atom_get_val,
2381 .get_scaling = silvermont_get_scaling,
2382 .get_vid = atom_get_vid,
de4a76cb
RW		 2383};
2384
2f49afc2
RW		 2385static const struct pstate_funcs airmont_funcs = {
2386 .get_max = atom_get_max_pstate,
2387 .get_max_physical = atom_get_max_pstate,
2388 .get_min = atom_get_min_pstate,
2389 .get_turbo = atom_get_turbo_pstate,
2390 .get_val = atom_get_val,
2391 .get_scaling = airmont_get_scaling,
2392 .get_vid = atom_get_vid,
de4a76cb
RW		 2393};
2394
2f49afc2
RW		 2395static const struct pstate_funcs knl_funcs = {
2396 .get_max = core_get_max_pstate,
2397 .get_max_physical = core_get_max_pstate_physical,
2398 .get_min = core_get_min_pstate,
2399 .get_turbo = knl_get_turbo_pstate,
6e34e1f2 2400 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2f49afc2
RW		 2401 .get_scaling = core_get_scaling,
2402 .get_val = core_get_val,
de4a76cb
RW		 2403};
2404
b11d77fa
TG		 2405#define X86_MATCH(model, policy) \
2406 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2407 X86_FEATURE_APERFMPERF, &policy)
93f0822d
DB		 2408
2409static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
b11d77fa
TG		 2410 X86_MATCH(SANDYBRIDGE, core_funcs),
2411 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2412 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2413 X86_MATCH(IVYBRIDGE, core_funcs),
2414 X86_MATCH(HASWELL, core_funcs),
2415 X86_MATCH(BROADWELL, core_funcs),
2416 X86_MATCH(IVYBRIDGE_X, core_funcs),
2417 X86_MATCH(HASWELL_X, core_funcs),
2418 X86_MATCH(HASWELL_L, core_funcs),
2419 X86_MATCH(HASWELL_G, core_funcs),
2420 X86_MATCH(BROADWELL_G, core_funcs),
2421 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2422 X86_MATCH(SKYLAKE_L, core_funcs),
2423 X86_MATCH(BROADWELL_X, core_funcs),
2424 X86_MATCH(SKYLAKE, core_funcs),
2425 X86_MATCH(BROADWELL_D, core_funcs),
2426 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2427 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2428 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2429 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2430 X86_MATCH(SKYLAKE_X, core_funcs),
706c5328 2431 X86_MATCH(COMETLAKE, core_funcs),
fbdc21e9 2432 X86_MATCH(ICELAKE_X, core_funcs),
71bb5c82 2433 X86_MATCH(TIGERLAKE, core_funcs),
df51f287 2434 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
e9501315 2435 X86_MATCH(EMERALDRAPIDS_X, core_funcs),
93f0822d
DB		 2436 {}
2437};
2438MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2439
29327c84 2440static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
b11d77fa
TG		 2441 X86_MATCH(BROADWELL_D, core_funcs),
2442 X86_MATCH(BROADWELL_X, core_funcs),
2443 X86_MATCH(SKYLAKE_X, core_funcs),
cd23f02f 2444 X86_MATCH(ICELAKE_X, core_funcs),
bbd67f1b 2445 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2f86dc4c
DB		 2446 {}
2447};
2448
6e978b22 2449static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
b11d77fa 2450 X86_MATCH(KABYLAKE, core_funcs),
6e978b22
SP		 2451 {}
2452};
2453
93f0822d
DB		 2454static int intel_pstate_init_cpu(unsigned int cpunum)
2455{
93f0822d
DB		 2456 struct cpudata *cpu;
2457
eae48f04
SP		 2458 cpu = all_cpu_data[cpunum];
2459
2460 if (!cpu) {
c5a2ee7d 2461 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
eae48f04
SP		 2462 if (!cpu)
2463 return -ENOMEM;
2464
57577c99 2465 WRITE_ONCE(all_cpu_data[cpunum], cpu);
eae48f04 2466
55671ea3 2467 cpu->cpu = cpunum;
93f0822d 2468
55671ea3 2469 cpu->epp_default = -EINVAL;
ba88d433 2470
55671ea3 2471 if (hwp_active) {
55671ea3 2472 intel_pstate_hwp_enable(cpu);
41ab43c9 2473
1f5e62f5 2474 if (intel_pstate_acpi_pm_profile_server())
55671ea3
RW		 2475 hwp_boost = true;
2476 }
2477 } else if (hwp_active) {
2478 /*
2479 * Re-enable HWP in case this happens after a resume from ACPI
2480 * S3 if the CPU was offline during the whole system/resume
2481 * cycle.
2482 */
2483 intel_pstate_hwp_reenable(cpu);
a4675fbc 2484 }
ba88d433 2485
55671ea3
RW		 2486 cpu->epp_powersave = -EINVAL;
2487 cpu->epp_policy = 0;
2488
179e8471 2489 intel_pstate_get_cpu_pstates(cpu);
016c8150 2490
4836df17 2491 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 2492
2493 return 0;
2494}
2495
febce40f 2496static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 2497{
febce40f
RW		 2498 struct cpudata *cpu = all_cpu_data[cpu_num];
2499
e0efd5be 2500 if (hwp_active && !hwp_boost)
62611cb9
LB		 2501 return;
2502
5ab666e0
RW		 2503 if (cpu->update_util_set)
2504 return;
2505
febce40f
RW		 2506 /* Prevent intel_pstate_update_util() from using stale data. */
2507 cpu->sample.time = 0;
67dd9bf4 2508 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
e0efd5be
SP		 2509 (hwp_active ?
2510 intel_pstate_update_util_hwp :
2511 intel_pstate_update_util));
4578ee7e 2512 cpu->update_util_set = true;
bb6ab52f
RW		 2513}
2514
2515static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2516{
4578ee7e
CY		 2517 struct cpudata *cpu_data = all_cpu_data[cpu];
2518
2519 if (!cpu_data->update_util_set)
2520 return;
2521
0bed612b 2522 cpufreq_remove_update_util_hook(cpu);
4578ee7e 2523 cpu_data->update_util_set = false;
09659af3 2524 synchronize_rcu();
bb6ab52f
RW		 2525}
2526
80b120ca
RW		 2527static int intel_pstate_get_max_freq(struct cpudata *cpu)
2528{
2529 return global.turbo_disabled || global.no_turbo ?
2530 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2531}
2532
1e4f63ae
RW		 2533static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2534 unsigned int policy_min,
2535 unsigned int policy_max)
eae48f04 2536{
eb3693f0 2537 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
e4c204ce 2538 int32_t max_policy_perf, min_policy_perf;
a410c03d 2539
eb3693f0
RW		 2540 max_policy_perf = policy_max / perf_ctl_scaling;
2541 if (policy_max == policy_min) {
2542 min_policy_perf = max_policy_perf;
2543 } else {
2544 min_policy_perf = policy_min / perf_ctl_scaling;
2545 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2546 0, max_policy_perf);
2547 }
2548
1a4fe38a 2549 /*
de5bcf40
RW		 2550 * HWP needs some special consideration, because HWP_REQUEST uses
2551 * abstract values to represent performance rather than pure ratios.
1a4fe38a 2552 */
458b03f8 2553 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
458b03f8
RW		 2554 int freq;
2555
2556 freq = max_policy_perf * perf_ctl_scaling;
192cdb1c 2557 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
458b03f8 2558 freq = min_policy_perf * perf_ctl_scaling;
192cdb1c 2559 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
5879f877 2560 }
eae48f04 2561
b989bc0f
RW		 2562 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2563 cpu->cpu, min_policy_perf, max_policy_perf);
1a4fe38a 2564
e4c204ce 2565 /* Normalize user input to [min_perf, max_perf] */
c5a2ee7d 2566 if (per_cpu_limits) {
1a4fe38a
SP		 2567 cpu->min_perf_ratio = min_policy_perf;
2568 cpu->max_perf_ratio = max_policy_perf;
c5a2ee7d 2569 } else {
b989bc0f 2570 int turbo_max = cpu->pstate.turbo_pstate;
c5a2ee7d
RW		 2571 int32_t global_min, global_max;
2572
2573 /* Global limits are in percent of the maximum turbo P-state. */
1a4fe38a
SP		 2574 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2575 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
c5a2ee7d 2576 global_min = clamp_t(int32_t, global_min, 0, global_max);
eae48f04 2577
1e4f63ae 2578 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
1a4fe38a 2579 global_min, global_max);
c5a2ee7d 2580
1a4fe38a
SP		 2581 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2582 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2583 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2584 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
eae48f04 2585
1a4fe38a
SP		 2586 /* Make sure min_perf <= max_perf */
2587 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2588 cpu->max_perf_ratio);
eae48f04 2589
1a4fe38a 2590 }
1e4f63ae 2591 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
1a4fe38a
SP		 2592 cpu->max_perf_ratio,
2593 cpu->min_perf_ratio);
eae48f04
SP		 2594}
2595
93f0822d
DB		 2596static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2597{
3be9200d
SP		 2598 struct cpudata *cpu;
2599
d3929b83
DB		 2600 if (!policy->cpuinfo.max_freq)
2601 return -ENODEV;
2602
2c2c1af4
SP		 2603 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2604 policy->cpuinfo.max_freq, policy->max);
2605
a6c6ead1 2606 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 2607 cpu->policy = policy->policy;
2608
b59fe540
SP		 2609 mutex_lock(&intel_pstate_limits_lock);
2610
1e4f63ae 2611 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
a240c4aa 2612
2f1d407a 2613 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 2614 /*
2615 * NOHZ_FULL CPUs need this as the governor callback may not
2616 * be invoked on them.
2617 */
2618 intel_pstate_clear_update_util_hook(policy->cpu);
2619 intel_pstate_max_within_limits(cpu);
82b4e03e
LB		 2620 } else {
2621 intel_pstate_set_update_util_hook(policy->cpu);
a6c6ead1
RW		 2622 }
2623
e0efd5be
SP		 2624 if (hwp_active) {
2625 /*
2626 * When hwp_boost was active before and dynamically it
2627 * was turned off, in that case we need to clear the
2628 * update util hook.
2629 */
2630 if (!hwp_boost)
2631 intel_pstate_clear_update_util_hook(policy->cpu);
2bfc4cbb 2632 intel_pstate_hwp_set(policy->cpu);
e0efd5be 2633 }
d51847ac
DS		 2634 /*
2635 * policy->cur is never updated with the intel_pstate driver, but it
2636 * is used as a stale frequency value. So, keep it within limits.
2637 */
2638 policy->cur = policy->min;
2f86dc4c 2639
b59fe540
SP		 2640 mutex_unlock(&intel_pstate_limits_lock);
2641
93f0822d
DB		 2642 return 0;
2643}
2644
1e4f63ae
RW		 2645static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2646 struct cpufreq_policy_data *policy)
80b120ca 2647{
d3264f75
SP		 2648 if (!hwp_active &&
2649 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
80b120ca
RW		 2650 policy->max < policy->cpuinfo.max_freq &&
2651 policy->max > cpu->pstate.max_freq) {
2652 pr_debug("policy->max > max non turbo frequency\n");
2653 policy->max = policy->cpuinfo.max_freq;
2654 }
2655}
2656
d5a2a6bb
RW		 2657static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2658 struct cpufreq_policy_data *policy)
93f0822d 2659{
e40ad84c
RW		 2660 int max_freq;
2661
7d9a8a9f 2662 update_turbo_state();
e40ad84c 2663 if (hwp_active) {
de5bcf40
RW		 2664 intel_pstate_get_hwp_cap(cpu);
2665 max_freq = global.no_turbo || global.turbo_disabled ?
2666 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
e40ad84c
RW		 2667 } else {
2668 max_freq = intel_pstate_get_max_freq(cpu);
2669 }
2670 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
93f0822d 2671
1e4f63ae 2672 intel_pstate_adjust_policy_max(cpu, policy);
d5a2a6bb
RW		 2673}
2674
2675static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2676{
2677 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
80b120ca 2678
93f0822d
DB		 2679 return 0;
2680}
2681
49d6feef 2682static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
001c76f0 2683{
4adcf2e5
RW		 2684 struct cpudata *cpu = all_cpu_data[policy->cpu];
2685
2686 pr_debug("CPU %d going offline\n", cpu->cpu);
2687
2688 if (cpu->suspended)
2689 return 0;
2690
2691 /*
2692 * If the CPU is an SMT thread and it goes offline with the performance
2693 * settings different from the minimum, it will prevent its sibling
2694 * from getting to lower performance levels, so force the minimum
2695 * performance on CPU offline to prevent that from happening.
2696 */
f6ebbcf0 2697 if (hwp_active)
4adcf2e5 2698 intel_pstate_hwp_offline(cpu);
f6ebbcf0 2699 else
4adcf2e5
RW		 2700 intel_pstate_set_min_pstate(cpu);
2701
2702 intel_pstate_exit_perf_limits(policy);
2703
2704 return 0;
2705}
2706
2707static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2708{
2709 struct cpudata *cpu = all_cpu_data[policy->cpu];
2710
2711 pr_debug("CPU %d going online\n", cpu->cpu);
2712
2713 intel_pstate_init_acpi_perf_limits(policy);
2714
2715 if (hwp_active) {
2716 /*
2717 * Re-enable HWP and clear the "suspended" flag to let "resume"
2718 * know that it need not do that.
2719 */
2720 intel_pstate_hwp_reenable(cpu);
2721 cpu->suspended = false;
2722 }
2723
2724 return 0;
001c76f0
RW		 2725}
2726
49d6feef 2727static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
93f0822d 2728{
001c76f0 2729 intel_pstate_clear_update_util_hook(policy->cpu);
49d6feef
RW		 2730
2731 return intel_cpufreq_cpu_offline(policy);
001c76f0 2732}
bb18008f 2733
001c76f0
RW		 2734static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2735{
4adcf2e5 2736 pr_debug("CPU %d exiting\n", policy->cpu);
a4675fbc 2737
001c76f0 2738 policy->fast_switch_possible = false;
2f86dc4c 2739
001c76f0 2740 return 0;
93f0822d
DB		 2741}
2742
001c76f0 2743static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2744{
93f0822d 2745 struct cpudata *cpu;
52e0a509 2746 int rc;
93f0822d
DB		 2747
2748 rc = intel_pstate_init_cpu(policy->cpu);
2749 if (rc)
2750 return rc;
2751
2752 cpu = all_cpu_data[policy->cpu];
2753
1a4fe38a
SP		 2754 cpu->max_perf_ratio = 0xFF;
2755 cpu->min_perf_ratio = 0;
93f0822d 2756
93f0822d 2757 /* cpuinfo and default policy values */
eb3693f0 2758 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
983e600e 2759 update_turbo_state();
9083e498 2760 global.turbo_disabled_mf = global.turbo_disabled;
7de32556 2761 policy->cpuinfo.max_freq = global.turbo_disabled ?
eea033d0 2762 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
de5bcf40
RW		 2763
2764 policy->min = policy->cpuinfo.min_freq;
2765 policy->max = policy->cpuinfo.max_freq;
eea033d0 2766
9522a2ff 2767 intel_pstate_init_acpi_perf_limits(policy);
93f0822d 2768
001c76f0
RW		 2769 policy->fast_switch_possible = true;
2770
93f0822d
DB		 2771 return 0;
2772}
2773
001c76f0 2774static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2775{
001c76f0
RW		 2776 int ret = __intel_pstate_cpu_init(policy);
2777
2778 if (ret)
2779 return ret;
2780
5ac54113
RW		 2781 /*
2782 * Set the policy to powersave to provide a valid fallback value in case
2783 * the default cpufreq governor is neither powersave nor performance.
2784 */
2785 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff 2786
c27a0ccc
RW		 2787 if (hwp_active) {
2788 struct cpudata *cpu = all_cpu_data[policy->cpu];
2789
2790 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2791 }
2792
9522a2ff
SP		 2793 return 0;
2794}
2795
001c76f0 2796static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2797 .flags = CPUFREQ_CONST_LOOPS,
2798 .verify = intel_pstate_verify_policy,
2799 .setpolicy = intel_pstate_set_policy,
4adcf2e5 2800 .suspend = intel_pstate_suspend,
8442885f 2801 .resume = intel_pstate_resume,
93f0822d 2802 .init = intel_pstate_cpu_init,
9522a2ff 2803 .exit = intel_pstate_cpu_exit,
4adcf2e5
RW		 2804 .offline = intel_pstate_cpu_offline,
2805 .online = intel_pstate_cpu_online,
5a25e3f7 2806 .update_limits = intel_pstate_update_limits,
93f0822d 2807 .name = "intel_pstate",
93f0822d
DB		 2808};
2809
1e4f63ae 2810static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
001c76f0
RW		 2811{
2812 struct cpudata *cpu = all_cpu_data[policy->cpu];
001c76f0 2813
d5a2a6bb 2814 intel_pstate_verify_cpu_policy(cpu, policy);
1e4f63ae 2815 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
c5a2ee7d 2816
001c76f0
RW		 2817 return 0;
2818}
2819
50e9ffab
DS		 2820/* Use of trace in passive mode:
2821 *
2822 * In passive mode the trace core_busy field (also known as the
2823 * performance field, and lablelled as such on the graphs; also known as
2824 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2825 * driver call was via the normal or fast switch path. Various graphs
2826 * output from the intel_pstate_tracer.py utility that include core_busy
2827 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
75a8d877 2828 * so we use 10 to indicate the normal path through the driver, and
50e9ffab
DS		 2829 * 90 to indicate the fast switch path through the driver.
2830 * The scaled_busy field is not used, and is set to 0.
2831 */
2832
2833#define INTEL_PSTATE_TRACE_TARGET 10
2834#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2835
2836static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2837{
2838 struct sample *sample;
2839
2840 if (!trace_pstate_sample_enabled())
2841 return;
2842
2843 if (!intel_pstate_sample(cpu, ktime_get()))
2844 return;
2845
2846 sample = &cpu->sample;
2847 trace_pstate_sample(trace_type,
2848 0,
2849 old_pstate,
2850 cpu->pstate.current_pstate,
2851 sample->mperf,
2852 sample->aperf,
2853 sample->tsc,
2854 get_avg_frequency(cpu),
2855 fp_toint(cpu->iowait_boost * 100));
2856}
2857
597ffbc8 2858static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
a365ab6b 2859 u32 desired, bool fast_switch)
f6ebbcf0
RW		 2860{
2861 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2862
2863 value &= ~HWP_MIN_PERF(~0L);
a365ab6b 2864 value |= HWP_MIN_PERF(min);
f6ebbcf0 2865
f6ebbcf0 2866 value &= ~HWP_MAX_PERF(~0L);
a365ab6b
RW		 2867 value |= HWP_MAX_PERF(max);
2868
2869 value &= ~HWP_DESIRED_PERF(~0L);
2870 value |= HWP_DESIRED_PERF(desired);
f6ebbcf0
RW		 2871
2872 if (value == prev)
2873 return;
2874
2875 WRITE_ONCE(cpu->hwp_req_cached, value);
2876 if (fast_switch)
2877 wrmsrl(MSR_HWP_REQUEST, value);
2878 else
2879 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2880}
2881
597ffbc8 2882static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
f6ebbcf0
RW		 2883 u32 target_pstate, bool fast_switch)
2884{
2885 if (fast_switch)
2886 wrmsrl(MSR_IA32_PERF_CTL,
2887 pstate_funcs.get_val(cpu, target_pstate));
2888 else
2889 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2890 pstate_funcs.get_val(cpu, target_pstate));
2891}
2892
fcb3a1ab
RW		 2893static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2894 int target_pstate, bool fast_switch)
f6ebbcf0 2895{
fcb3a1ab 2896 struct cpudata *cpu = all_cpu_data[policy->cpu];
f6ebbcf0
RW		 2897 int old_pstate = cpu->pstate.current_pstate;
2898
2899 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
a365ab6b
RW		 2900 if (hwp_active) {
2901 int max_pstate = policy->strict_target ?
2902 target_pstate : cpu->max_perf_ratio;
2903
597ffbc8 2904 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
a365ab6b
RW		 2905 fast_switch);
2906 } else if (target_pstate != old_pstate) {
597ffbc8 2907 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
a365ab6b 2908 }
2554c32f
RW		 2909
2910 cpu->pstate.current_pstate = target_pstate;
f6ebbcf0
RW		 2911
2912 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2913 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2914
2915 return target_pstate;
2916}
2917
001c76f0
RW		 2918static int intel_cpufreq_target(struct cpufreq_policy *policy,
2919 unsigned int target_freq,
2920 unsigned int relation)
2921{
2922 struct cpudata *cpu = all_cpu_data[policy->cpu];
2923 struct cpufreq_freqs freqs;
f6ebbcf0 2924 int target_pstate;
001c76f0 2925
64897b20
RW		 2926 update_turbo_state();
2927
001c76f0 2928 freqs.old = policy->cur;
64897b20 2929 freqs.new = target_freq;
001c76f0
RW		 2930
2931 cpufreq_freq_transition_begin(policy, &freqs);
f6ebbcf0 2932
192cdb1c 2933 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
fcb3a1ab 2934 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
f6ebbcf0 2935
64078299 2936 freqs.new = target_pstate * cpu->pstate.scaling;
f6ebbcf0 2937
001c76f0
RW		 2938 cpufreq_freq_transition_end(policy, &freqs, false);
2939
2940 return 0;
2941}
2942
2943static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2944 unsigned int target_freq)
2945{
2946 struct cpudata *cpu = all_cpu_data[policy->cpu];
f6ebbcf0 2947 int target_pstate;
001c76f0 2948
64897b20
RW		 2949 update_turbo_state();
2950
192cdb1c 2951 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
f6ebbcf0 2952
fcb3a1ab 2953 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
f6ebbcf0 2954
64078299 2955 return target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2956}
2957
a365ab6b
RW		 2958static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2959 unsigned long min_perf,
2960 unsigned long target_perf,
2961 unsigned long capacity)
2962{
2963 struct cpudata *cpu = all_cpu_data[cpunum];
17ffd358 2964 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
a365ab6b
RW		 2965 int old_pstate = cpu->pstate.current_pstate;
2966 int cap_pstate, min_pstate, max_pstate, target_pstate;
2967
2968 update_turbo_state();
17ffd358
RW		 2969 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2970 HWP_HIGHEST_PERF(hwp_cap);
a365ab6b
RW		 2971
2972 /* Optimization: Avoid unnecessary divisions. */
2973
2974 target_pstate = cap_pstate;
2975 if (target_perf < capacity)
2976 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2977
2978 min_pstate = cap_pstate;
2979 if (min_perf < capacity)
2980 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2981
2982 if (min_pstate < cpu->pstate.min_pstate)
2983 min_pstate = cpu->pstate.min_pstate;
2984
2985 if (min_pstate < cpu->min_perf_ratio)
2986 min_pstate = cpu->min_perf_ratio;
2987
f0a0fc10
DS		 2988 if (min_pstate > cpu->max_perf_ratio)
2989 min_pstate = cpu->max_perf_ratio;
2990
a365ab6b
RW		 2991 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2992 if (max_pstate < min_pstate)
2993 max_pstate = min_pstate;
2994
2995 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2996
597ffbc8 2997 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
a365ab6b
RW		 2998
2999 cpu->pstate.current_pstate = target_pstate;
3000 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3001}
3002
001c76f0
RW		 3003static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3004{
3000ce3c 3005 struct freq_qos_request *req;
da5c504c
VK		 3006 struct cpudata *cpu;
3007 struct device *dev;
de5bcf40 3008 int ret, freq;
da5c504c
VK		 3009
3010 dev = get_cpu_device(policy->cpu);
3011 if (!dev)
3012 return -ENODEV;
001c76f0 3013
da5c504c 3014 ret = __intel_pstate_cpu_init(policy);
001c76f0
RW		 3015 if (ret)
3016 return ret;
3017
3018 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3019 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3020 policy->cur = policy->cpuinfo.min_freq;
3021
da5c504c
VK		 3022 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3023 if (!req) {
3024 ret = -ENOMEM;
3025 goto pstate_exit;
3026 }
3027
3028 cpu = all_cpu_data[policy->cpu];
3029
f6ebbcf0
RW		 3030 if (hwp_active) {
3031 u64 value;
3032
f6ebbcf0 3033 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
de5bcf40
RW		 3034
3035 intel_pstate_get_hwp_cap(cpu);
3036
f6ebbcf0
RW		 3037 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3038 WRITE_ONCE(cpu->hwp_req_cached, value);
de5bcf40 3039
c27a0ccc 3040 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
f6ebbcf0 3041 } else {
f6ebbcf0
RW		 3042 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3043 }
da5c504c 3044
de5bcf40 3045 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
da5c504c 3046
3000ce3c 3047 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
de5bcf40 3048 freq);
da5c504c
VK		 3049 if (ret < 0) {
3050 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3051 goto free_req;
3052 }
3053
de5bcf40
RW		 3054 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3055
3000ce3c 3056 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
de5bcf40 3057 freq);
da5c504c
VK		 3058 if (ret < 0) {
3059 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3060 goto remove_min_req;
3061 }
3062
3063 policy->driver_data = req;
3064
001c76f0 3065 return 0;
da5c504c
VK		 3066
3067remove_min_req:
3000ce3c 3068 freq_qos_remove_request(req);
da5c504c
VK		 3069free_req:
3070 kfree(req);
3071pstate_exit:
3072 intel_pstate_exit_perf_limits(policy);
3073
3074 return ret;
3075}
3076
3077static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3078{
3000ce3c 3079 struct freq_qos_request *req;
da5c504c
VK		 3080
3081 req = policy->driver_data;
3082
3000ce3c
RW		 3083 freq_qos_remove_request(req + 1);
3084 freq_qos_remove_request(req);
da5c504c
VK		 3085 kfree(req);
3086
3087 return intel_pstate_cpu_exit(policy);
001c76f0
RW		 3088}
3089
dbea75fe
RW		 3090static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3091{
3092 intel_pstate_suspend(policy);
3093
3094 if (hwp_active) {
3095 struct cpudata *cpu = all_cpu_data[policy->cpu];
3096 u64 value = READ_ONCE(cpu->hwp_req_cached);
3097
3098 /*
3099 * Clear the desired perf field in MSR_HWP_REQUEST in case
3100 * intel_cpufreq_adjust_perf() is in use and the last value
3101 * written by it may not be suitable.
3102 */
3103 value &= ~HWP_DESIRED_PERF(~0L);
3104 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3105 WRITE_ONCE(cpu->hwp_req_cached, value);
3106 }
3107
3108 return 0;
3109}
3110
001c76f0
RW		 3111static struct cpufreq_driver intel_cpufreq = {
3112 .flags = CPUFREQ_CONST_LOOPS,
3113 .verify = intel_cpufreq_verify_policy,
3114 .target = intel_cpufreq_target,
3115 .fast_switch = intel_cpufreq_fast_switch,
3116 .init = intel_cpufreq_cpu_init,
da5c504c 3117 .exit = intel_cpufreq_cpu_exit,
49d6feef 3118 .offline = intel_cpufreq_cpu_offline,
4adcf2e5 3119 .online = intel_pstate_cpu_online,
dbea75fe 3120 .suspend = intel_cpufreq_suspend,
4adcf2e5 3121 .resume = intel_pstate_resume,
5a25e3f7 3122 .update_limits = intel_pstate_update_limits,
001c76f0
RW		 3123 .name = "intel_cpufreq",
3124};
3125
39a188b8 3126static struct cpufreq_driver *default_driver;
001c76f0 3127
fb1fe104
RW		 3128static void intel_pstate_driver_cleanup(void)
3129{
3130 unsigned int cpu;
3131
09681a07 3132 cpus_read_lock();
fb1fe104
RW		 3133 for_each_online_cpu(cpu) {
3134 if (all_cpu_data[cpu]) {
3135 if (intel_pstate_driver == &intel_pstate)
3136 intel_pstate_clear_update_util_hook(cpu);
3137
57577c99 3138 spin_lock(&hwp_notify_lock);
fb1fe104 3139 kfree(all_cpu_data[cpu]);
57577c99
SP		 3140 WRITE_ONCE(all_cpu_data[cpu], NULL);
3141 spin_unlock(&hwp_notify_lock);
fb1fe104
RW		 3142 }
3143 }
09681a07 3144 cpus_read_unlock();
f6ebbcf0 3145
ee8df89a 3146 intel_pstate_driver = NULL;
fb1fe104
RW		 3147}
3148
ee8df89a 3149static int intel_pstate_register_driver(struct cpufreq_driver *driver)
fb1fe104
RW		 3150{
3151 int ret;
3152
f6ebbcf0
RW		 3153 if (driver == &intel_pstate)
3154 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3155
c5a2ee7d
RW		 3156 memset(&global, 0, sizeof(global));
3157 global.max_perf_pct = 100;
c3a49c89 3158
ee8df89a 3159 intel_pstate_driver = driver;
fb1fe104
RW		 3160 ret = cpufreq_register_driver(intel_pstate_driver);
3161 if (ret) {
3162 intel_pstate_driver_cleanup();
3163 return ret;
3164 }
3165
c5a2ee7d
RW		 3166 global.min_perf_pct = min_perf_pct_min();
3167
fb1fe104
RW		 3168 return 0;
3169}
3170
fb1fe104
RW		 3171static ssize_t intel_pstate_show_status(char *buf)
3172{
ee8df89a 3173 if (!intel_pstate_driver)
fb1fe104
RW		 3174 return sprintf(buf, "off\n");
3175
3176 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3177 "active" : "passive");
3178}
3179
3180static int intel_pstate_update_status(const char *buf, size_t size)
3181{
43298db3
RW		 3182 if (size == 3 && !strncmp(buf, "off", size)) {
3183 if (!intel_pstate_driver)
3184 return -EINVAL;
3185
3186 if (hwp_active)
3187 return -EBUSY;
3188
55671ea3
RW		 3189 cpufreq_unregister_driver(intel_pstate_driver);
3190 intel_pstate_driver_cleanup();
fc7d1755 3191 return 0;
43298db3 3192 }
fb1fe104
RW		 3193
3194 if (size == 6 && !strncmp(buf, "active", size)) {
ee8df89a 3195 if (intel_pstate_driver) {
fb1fe104
RW		 3196 if (intel_pstate_driver == &intel_pstate)
3197 return 0;
3198
55671ea3 3199 cpufreq_unregister_driver(intel_pstate_driver);
fb1fe104
RW		 3200 }
3201
ee8df89a 3202 return intel_pstate_register_driver(&intel_pstate);
fb1fe104
RW		 3203 }
3204
3205 if (size == 7 && !strncmp(buf, "passive", size)) {
ee8df89a 3206 if (intel_pstate_driver) {
0042b2c0 3207 if (intel_pstate_driver == &intel_cpufreq)
fb1fe104
RW		 3208 return 0;
3209
55671ea3
RW		 3210 cpufreq_unregister_driver(intel_pstate_driver);
3211 intel_pstate_sysfs_hide_hwp_dynamic_boost();
fb1fe104
RW		 3212 }
3213
ee8df89a 3214 return intel_pstate_register_driver(&intel_cpufreq);
fb1fe104
RW		 3215 }
3216
3217 return -EINVAL;
3218}
3219
eed43609
JZ		 3220static int no_load __initdata;
3221static int no_hwp __initdata;
3222static int hwp_only __initdata;
29327c84 3223static unsigned int force_load __initdata;
6be26498 3224
29327c84 3225static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 3226{
8dbab94d
RW		 3227 if (!pstate_funcs.get_max(0) ||
3228 !pstate_funcs.get_min(0) ||
3229 !pstate_funcs.get_turbo(0))
b563b4e3
DB		 3230 return -ENODEV;
3231
b563b4e3
DB		 3232 return 0;
3233}
016c8150 3234
29327c84 3235static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 3236{
3237 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 3238 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 3239 pstate_funcs.get_min = funcs->get_min;
3240 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 3241 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 3242 pstate_funcs.get_val = funcs->get_val;
007bea09 3243 pstate_funcs.get_vid = funcs->get_vid;
6e34e1f2 3244 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
016c8150
DB		 3245}
3246
9522a2ff 3247#ifdef CONFIG_ACPI
fbbcdc07 3248
29327c84 3249static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 3250{
3251 int i;
3252
3253 for_each_possible_cpu(i) {
3254 acpi_status status;
3255 union acpi_object *pss;
3256 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3257 struct acpi_processor *pr = per_cpu(processors, i);
3258
3259 if (!pr)
3260 continue;
3261
3262 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3263 if (ACPI_FAILURE(status))
3264 continue;
3265
3266 pss = buffer.pointer;
3267 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3268 kfree(pss);
3269 return false;
3270 }
3271
3272 kfree(pss);
3273 }
3274
076b862c 3275 pr_debug("ACPI _PSS not found\n");
fbbcdc07
AH		 3276 return true;
3277}
3278
95d6c085
RW		 3279static bool __init intel_pstate_no_acpi_pcch(void)
3280{
3281 acpi_status status;
3282 acpi_handle handle;
3283
3284 status = acpi_get_handle(NULL, "\\_SB", &handle);
3285 if (ACPI_FAILURE(status))
076b862c
EV		 3286 goto not_found;
3287
3288 if (acpi_has_method(handle, "PCCH"))
3289 return false;
95d6c085 3290
076b862c
EV		 3291not_found:
3292 pr_debug("ACPI PCCH not found\n");
3293 return true;
95d6c085
RW		 3294}
3295
29327c84 3296static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 3297{
3298 int i;
3299
3300 for_each_possible_cpu(i) {
3301 struct acpi_processor *pr = per_cpu(processors, i);
3302
3303 if (!pr)
3304 continue;
3305 if (acpi_has_method(pr->handle, "_PPC"))
3306 return true;
3307 }
076b862c 3308 pr_debug("ACPI _PPC not found\n");
966916ea 3309 return false;
3310}
3311
3312enum {
3313 PSS,
3314 PPC,
3315};
3316
fbbcdc07 3317/* Hardware vendor-specific info that has its own power management modes */
5e932321 3318static struct acpi_platform_list plat_info[] __initdata = {
8d2eecea
JS		 3319 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3320 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
5e932321 3334 { } /* End */
fbbcdc07
AH		 3335};
3336
589bab6b
SP		 3337#define BITMASK_OOB (BIT(8) | BIT(18))
3338
29327c84 3339static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07 3340{
2f86dc4c
DB		 3341 const struct x86_cpu_id *id;
3342 u64 misc_pwr;
5e932321 3343 int idx;
2f86dc4c
DB		 3344
3345 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3346 if (id) {
3347 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
589bab6b
SP		 3348 if (misc_pwr & BITMASK_OOB) {
3349 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3350 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
2f86dc4c 3351 return true;
076b862c 3352 }
2f86dc4c 3353 }
fbbcdc07 3354
5e932321
TK		 3355 idx = acpi_match_platform_list(plat_info);
3356 if (idx < 0)
fbbcdc07
AH		 3357 return false;
3358
5e932321
TK		 3359 switch (plat_info[idx].data) {
3360 case PSS:
95d6c085
RW		 3361 if (!intel_pstate_no_acpi_pss())
3362 return false;
3363
3364 return intel_pstate_no_acpi_pcch();
5e932321
TK		 3365 case PPC:
3366 return intel_pstate_has_acpi_ppc() && !force_load;
fbbcdc07
AH		 3367 }
3368
3369 return false;
3370}
d0ea59e1
RW		 3371
3372static void intel_pstate_request_control_from_smm(void)
3373{
3374 /*
3375 * It may be unsafe to request P-states control from SMM if _PPC support
3376 * has not been enabled.
3377 */
3378 if (acpi_ppc)
3379 acpi_processor_pstate_control();
3380}
fbbcdc07
AH		 3381#else /* CONFIG_ACPI not enabled */
3382static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 3383static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 3384static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 3385#endif /* CONFIG_ACPI */
3386
ff7c9917
SP		 3387#define INTEL_PSTATE_HWP_BROADWELL 0x01
3388
b11d77fa
TG		 3389#define X86_MATCH_HWP(model, hwp_mode) \
3390 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
d9782807 3391 X86_FEATURE_HWP, hwp_mode)
ff7c9917 3392
7791e4aa 3393static const struct x86_cpu_id hwp_support_ids[] __initconst = {
b11d77fa
TG		 3394 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3395 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3396 X86_MATCH_HWP(ANY, 0),
7791e4aa
SP		 3397 {}
3398};
3399
e5af36b2
RW		 3400static bool intel_pstate_hwp_is_enabled(void)
3401{
3402 u64 value;
3403
3404 rdmsrl(MSR_PM_ENABLE, value);
3405 return !!(value & 0x1);
3406}
3407
240a8da6
SP		 3408#define POWERSAVE_MASK GENMASK(7, 0)
3409#define BALANCE_POWER_MASK GENMASK(15, 8)
3410#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3411#define PERFORMANCE_MASK GENMASK(31, 24)
3412
3413#define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3414 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3415 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3416 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3417 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3418
3419#define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3420 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3421 balance_perf, HWP_EPP_PERFORMANCE))
3422
3423static const struct x86_cpu_id intel_epp_default[] = {
b6e6f8be
SP		 3424 /*
3425 * Set EPP value as 102, this is the max suggested EPP
3426 * which can result in one core turbo frequency for
3427 * AlderLake Mobile CPUs.
3428 */
240a8da6
SP		 3429 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3430 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
1f4b7fdd
SP		 3431 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3432 HWP_EPP_BALANCE_POWERSAVE, 115, 16)),
b6e6f8be
SP		 3433 {}
3434};
3435
bde4f5ff
SP		 3436static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3437 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3438 {}
3439};
3440
93f0822d
DB		 3441static int __init intel_pstate_init(void)
3442{
57577c99 3443 static struct cpudata **_all_cpu_data;
ff7c9917 3444 const struct x86_cpu_id *id;
eb5139d1 3445 int rc;
93f0822d 3446
4ab52646
BP		 3447 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3448 return -ENODEV;
3449
ff7c9917
SP		 3450 id = x86_match_cpu(hwp_support_ids);
3451 if (id) {
21cdb6c1 3452 hwp_forced = intel_pstate_hwp_is_enabled();
d9a7e9df
DS		 3453
3454 if (hwp_forced)
3455 pr_info("HWP enabled by BIOS\n");
3456 else if (no_load)
3457 return -ENODEV;
3458
2f49afc2 3459 copy_cpu_funcs(&core_funcs);
7aa10312
RW		 3460 /*
3461 * Avoid enabling HWP for processors without EPP support,
3462 * because that means incomplete HWP implementation which is a
3463 * corner case and supporting it is generally problematic.
e5af36b2
RW		 3464 *
3465 * If HWP is enabled already, though, there is no choice but to
3466 * deal with it.
7aa10312 3467 */
d9a7e9df 3468 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
57577c99 3469 WRITE_ONCE(hwp_active, 1);
ff7c9917 3470 hwp_mode_bdw = id->driver_data;
eb5139d1 3471 intel_pstate.attr = hwp_cpufreq_attrs;
f6ebbcf0 3472 intel_cpufreq.attr = hwp_cpufreq_attrs;
e0be38ed 3473 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
a365ab6b 3474 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
f6ebbcf0
RW		 3475 if (!default_driver)
3476 default_driver = &intel_pstate;
3477
0fcfc9e5 3478 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
46573fd6 3479
eb5139d1
RW		 3480 goto hwp_cpu_matched;
3481 }
d9a7e9df 3482 pr_info("HWP not enabled\n");
eb5139d1 3483 } else {
d9a7e9df
DS		 3484 if (no_load)
3485 return -ENODEV;
3486
eb5139d1 3487 id = x86_match_cpu(intel_pstate_cpu_ids);
076b862c 3488 if (!id) {
4ab52646 3489 pr_info("CPU model not supported\n");
eb5139d1 3490 return -ENODEV;
076b862c 3491 }
93f0822d 3492
2f49afc2 3493 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
eb5139d1 3494 }
016c8150 3495
076b862c
EV		 3496 if (intel_pstate_msrs_not_valid()) {
3497 pr_info("Invalid MSRs\n");
b563b4e3 3498 return -ENODEV;
076b862c 3499 }
33aa46f2 3500 /* Without HWP start in the passive mode. */
39a188b8
RW		 3501 if (!default_driver)
3502 default_driver = &intel_cpufreq;
b563b4e3 3503
7791e4aa
SP		 3504hwp_cpu_matched:
3505 /*
3506 * The Intel pstate driver will be ignored if the platform
3507 * firmware has its own power management modes.
3508 */
076b862c
EV		 3509 if (intel_pstate_platform_pwr_mgmt_exists()) {
3510 pr_info("P-states controlled by the platform\n");
7791e4aa 3511 return -ENODEV;
076b862c 3512 }
7791e4aa 3513
fb1fe104
RW		 3514 if (!hwp_active && hwp_only)
3515 return -ENOTSUPP;
3516
4836df17 3517 pr_info("Intel P-state driver initializing\n");
93f0822d 3518
57577c99
SP		 3519 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3520 if (!_all_cpu_data)
93f0822d 3521 return -ENOMEM;
93f0822d 3522
57577c99
SP		 3523 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3524
d0ea59e1
RW		 3525 intel_pstate_request_control_from_smm();
3526
93f0822d 3527 intel_pstate_sysfs_expose_params();
b69880f9 3528
b6e6f8be 3529 if (hwp_active) {
240a8da6 3530 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
bde4f5ff 3531 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
b6e6f8be 3532
240a8da6
SP		 3533 if (id) {
3534 epp_values[EPP_INDEX_POWERSAVE] =
3535 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3536 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3537 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3538 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3539 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3540 epp_values[EPP_INDEX_PERFORMANCE] =
3541 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3542 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3543 epp_values[EPP_INDEX_POWERSAVE],
3544 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3545 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3546 epp_values[EPP_INDEX_PERFORMANCE]);
3547 }
bde4f5ff
SP		 3548
3549 if (hybrid_id) {
3550 hybrid_scaling_factor = hybrid_id->driver_data;
3551 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3552 }
3553
b6e6f8be
SP		 3554 }
3555
0c30b65b 3556 mutex_lock(&intel_pstate_driver_lock);
ee8df89a 3557 rc = intel_pstate_register_driver(default_driver);
0c30b65b 3558 mutex_unlock(&intel_pstate_driver_lock);
cdc1719c
CY		 3559 if (rc) {
3560 intel_pstate_sysfs_remove();
fb1fe104 3561 return rc;
cdc1719c 3562 }
366430b5 3563
ed7bde7a
SP		 3564 if (hwp_active) {
3565 const struct x86_cpu_id *id;
3566
3567 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3568 if (id) {
3569 set_power_ctl_ee_state(false);
3570 pr_info("Disabling energy efficiency optimization\n");
3571 }
3572
4836df17 3573 pr_info("HWP enabled\n");
eb3693f0
RW		 3574 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3575 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
ed7bde7a 3576 }
7791e4aa 3577
fb1fe104 3578 return 0;
93f0822d
DB		 3579}
3580device_initcall(intel_pstate_init);
3581
6be26498
DB		 3582static int __init intel_pstate_setup(char *str)
3583{
3584 if (!str)
3585 return -EINVAL;
3586
f6ebbcf0 3587 if (!strcmp(str, "disable"))
6be26498 3588 no_load = 1;
f6ebbcf0 3589 else if (!strcmp(str, "active"))
39a188b8 3590 default_driver = &intel_pstate;
f6ebbcf0 3591 else if (!strcmp(str, "passive"))
ee8df89a 3592 default_driver = &intel_cpufreq;
f6ebbcf0 3593
d9a7e9df 3594 if (!strcmp(str, "no_hwp"))
2f86dc4c 3595 no_hwp = 1;
d9a7e9df 3596
aa4ea34d
EZ		 3597 if (!strcmp(str, "force"))
3598 force_load = 1;
d64c3b0b
KCA		 3599 if (!strcmp(str, "hwp_only"))
3600 hwp_only = 1;
eae48f04
SP		 3601 if (!strcmp(str, "per_cpu_perf_limits"))
3602 per_cpu_limits = true;
9522a2ff
SP		 3603
3604#ifdef CONFIG_ACPI
3605 if (!strcmp(str, "support_acpi_ppc"))
3606 acpi_ppc = true;
3607#endif
3608
6be26498
DB		 3609 return 0;
3610}
3611early_param("intel_pstate", intel_pstate_setup);
3612
93f0822d
DB		 3613MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3614MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
Linux 6.x block layer and io_uring tree(s)