Commit | Line | Data |
---|---|---|
93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
d6472302 | 29 | #include <linux/vmalloc.h> |
93f0822d DB |
30 | #include <trace/events/power.h> |
31 | ||
32 | #include <asm/div64.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/cpu_device_id.h> | |
64df1fdf | 35 | #include <asm/cpufeature.h> |
93f0822d | 36 | |
61d8d2ab DB |
37 | #define BYT_RATIOS 0x66a |
38 | #define BYT_VIDS 0x66b | |
39 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 40 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 41 | |
f0fe3cd7 | 42 | #define FRAC_BITS 8 |
93f0822d DB |
43 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
44 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 45 | |
93f0822d DB |
46 | |
47 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
48 | { | |
49 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
50 | } | |
51 | ||
7180dddf | 52 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 53 | { |
7180dddf | 54 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
55 | } |
56 | ||
d022a65e DB |
57 | static inline int ceiling_fp(int32_t x) |
58 | { | |
59 | int mask, ret; | |
60 | ||
61 | ret = fp_toint(x); | |
62 | mask = (1 << FRAC_BITS) - 1; | |
63 | if (x & mask) | |
64 | ret += 1; | |
65 | return ret; | |
66 | } | |
67 | ||
93f0822d | 68 | struct sample { |
d253d2a5 | 69 | int32_t core_pct_busy; |
93f0822d DB |
70 | u64 aperf; |
71 | u64 mperf; | |
4055fad3 | 72 | u64 tsc; |
93f0822d | 73 | int freq; |
c4ee841f | 74 | ktime_t time; |
93f0822d DB |
75 | }; |
76 | ||
77 | struct pstate_data { | |
78 | int current_pstate; | |
79 | int min_pstate; | |
80 | int max_pstate; | |
b27580b0 | 81 | int scaling; |
93f0822d DB |
82 | int turbo_pstate; |
83 | }; | |
84 | ||
007bea09 | 85 | struct vid_data { |
21855ff5 DB |
86 | int min; |
87 | int max; | |
88 | int turbo; | |
007bea09 DB |
89 | int32_t ratio; |
90 | }; | |
91 | ||
93f0822d DB |
92 | struct _pid { |
93 | int setpoint; | |
94 | int32_t integral; | |
95 | int32_t p_gain; | |
96 | int32_t i_gain; | |
97 | int32_t d_gain; | |
98 | int deadband; | |
d253d2a5 | 99 | int32_t last_err; |
93f0822d DB |
100 | }; |
101 | ||
102 | struct cpudata { | |
103 | int cpu; | |
104 | ||
93f0822d DB |
105 | struct timer_list timer; |
106 | ||
93f0822d | 107 | struct pstate_data pstate; |
007bea09 | 108 | struct vid_data vid; |
93f0822d | 109 | struct _pid pid; |
93f0822d | 110 | |
c4ee841f | 111 | ktime_t last_sample_time; |
93f0822d DB |
112 | u64 prev_aperf; |
113 | u64 prev_mperf; | |
4055fad3 | 114 | u64 prev_tsc; |
d37e2b76 | 115 | struct sample sample; |
93f0822d DB |
116 | }; |
117 | ||
118 | static struct cpudata **all_cpu_data; | |
119 | struct pstate_adjust_policy { | |
120 | int sample_rate_ms; | |
121 | int deadband; | |
122 | int setpoint; | |
123 | int p_gain_pct; | |
124 | int d_gain_pct; | |
125 | int i_gain_pct; | |
126 | }; | |
127 | ||
016c8150 DB |
128 | struct pstate_funcs { |
129 | int (*get_max)(void); | |
130 | int (*get_min)(void); | |
131 | int (*get_turbo)(void); | |
b27580b0 | 132 | int (*get_scaling)(void); |
007bea09 DB |
133 | void (*set)(struct cpudata*, int pstate); |
134 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
135 | }; |
136 | ||
016c8150 DB |
137 | struct cpu_defaults { |
138 | struct pstate_adjust_policy pid_policy; | |
139 | struct pstate_funcs funcs; | |
93f0822d DB |
140 | }; |
141 | ||
016c8150 DB |
142 | static struct pstate_adjust_policy pid_params; |
143 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 144 | static int hwp_active; |
016c8150 | 145 | |
93f0822d DB |
146 | struct perf_limits { |
147 | int no_turbo; | |
dd5fbf70 | 148 | int turbo_disabled; |
93f0822d DB |
149 | int max_perf_pct; |
150 | int min_perf_pct; | |
151 | int32_t max_perf; | |
152 | int32_t min_perf; | |
d8f469e9 DB |
153 | int max_policy_pct; |
154 | int max_sysfs_pct; | |
a0475992 KCA |
155 | int min_policy_pct; |
156 | int min_sysfs_pct; | |
93f0822d DB |
157 | }; |
158 | ||
159 | static struct perf_limits limits = { | |
160 | .no_turbo = 0, | |
4521e1a0 | 161 | .turbo_disabled = 0, |
93f0822d DB |
162 | .max_perf_pct = 100, |
163 | .max_perf = int_tofp(1), | |
164 | .min_perf_pct = 0, | |
165 | .min_perf = 0, | |
d8f469e9 DB |
166 | .max_policy_pct = 100, |
167 | .max_sysfs_pct = 100, | |
a0475992 KCA |
168 | .min_policy_pct = 0, |
169 | .min_sysfs_pct = 0, | |
93f0822d DB |
170 | }; |
171 | ||
172 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
c410833a | 173 | int deadband, int integral) { |
93f0822d DB |
174 | pid->setpoint = setpoint; |
175 | pid->deadband = deadband; | |
176 | pid->integral = int_tofp(integral); | |
d98d099b | 177 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
178 | } |
179 | ||
180 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
181 | { | |
182 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
183 | } | |
184 | ||
185 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
186 | { | |
187 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
188 | } | |
189 | ||
190 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
191 | { | |
93f0822d DB |
192 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
193 | } | |
194 | ||
d253d2a5 | 195 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 196 | { |
d253d2a5 | 197 | signed int result; |
93f0822d DB |
198 | int32_t pterm, dterm, fp_error; |
199 | int32_t integral_limit; | |
200 | ||
d253d2a5 | 201 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 202 | |
d253d2a5 | 203 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
204 | return 0; |
205 | ||
206 | pterm = mul_fp(pid->p_gain, fp_error); | |
207 | ||
208 | pid->integral += fp_error; | |
209 | ||
e0d4c8f8 KCA |
210 | /* |
211 | * We limit the integral here so that it will never | |
212 | * get higher than 30. This prevents it from becoming | |
213 | * too large an input over long periods of time and allows | |
214 | * it to get factored out sooner. | |
215 | * | |
216 | * The value of 30 was chosen through experimentation. | |
217 | */ | |
93f0822d DB |
218 | integral_limit = int_tofp(30); |
219 | if (pid->integral > integral_limit) | |
220 | pid->integral = integral_limit; | |
221 | if (pid->integral < -integral_limit) | |
222 | pid->integral = -integral_limit; | |
223 | ||
d253d2a5 BS |
224 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
225 | pid->last_err = fp_error; | |
93f0822d DB |
226 | |
227 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 228 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
229 | return (signed int)fp_toint(result); |
230 | } | |
231 | ||
232 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
233 | { | |
016c8150 DB |
234 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
235 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
236 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 237 | |
2d8d1f18 | 238 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
239 | } |
240 | ||
93f0822d DB |
241 | static inline void intel_pstate_reset_all_pid(void) |
242 | { | |
243 | unsigned int cpu; | |
845c1cbe | 244 | |
93f0822d DB |
245 | for_each_online_cpu(cpu) { |
246 | if (all_cpu_data[cpu]) | |
247 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
248 | } | |
249 | } | |
250 | ||
4521e1a0 GM |
251 | static inline void update_turbo_state(void) |
252 | { | |
253 | u64 misc_en; | |
254 | struct cpudata *cpu; | |
255 | ||
256 | cpu = all_cpu_data[0]; | |
257 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
258 | limits.turbo_disabled = | |
259 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || | |
260 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
261 | } | |
262 | ||
2f86dc4c DB |
263 | #define PCT_TO_HWP(x) (x * 255 / 100) |
264 | static void intel_pstate_hwp_set(void) | |
265 | { | |
266 | int min, max, cpu; | |
267 | u64 value, freq; | |
268 | ||
269 | get_online_cpus(); | |
270 | ||
271 | for_each_online_cpu(cpu) { | |
272 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
273 | min = PCT_TO_HWP(limits.min_perf_pct); | |
274 | value &= ~HWP_MIN_PERF(~0L); | |
275 | value |= HWP_MIN_PERF(min); | |
276 | ||
277 | max = PCT_TO_HWP(limits.max_perf_pct); | |
278 | if (limits.no_turbo) { | |
279 | rdmsrl( MSR_HWP_CAPABILITIES, freq); | |
280 | max = HWP_GUARANTEED_PERF(freq); | |
281 | } | |
282 | ||
283 | value &= ~HWP_MAX_PERF(~0L); | |
284 | value |= HWP_MAX_PERF(max); | |
285 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
286 | } | |
287 | ||
288 | put_online_cpus(); | |
289 | } | |
290 | ||
93f0822d DB |
291 | /************************** debugfs begin ************************/ |
292 | static int pid_param_set(void *data, u64 val) | |
293 | { | |
294 | *(u32 *)data = val; | |
295 | intel_pstate_reset_all_pid(); | |
296 | return 0; | |
297 | } | |
845c1cbe | 298 | |
93f0822d DB |
299 | static int pid_param_get(void *data, u64 *val) |
300 | { | |
301 | *val = *(u32 *)data; | |
302 | return 0; | |
303 | } | |
2d8d1f18 | 304 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
305 | |
306 | struct pid_param { | |
307 | char *name; | |
308 | void *value; | |
309 | }; | |
310 | ||
311 | static struct pid_param pid_files[] = { | |
016c8150 DB |
312 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
313 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
314 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
315 | {"deadband", &pid_params.deadband}, | |
316 | {"setpoint", &pid_params.setpoint}, | |
317 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
318 | {NULL, NULL} |
319 | }; | |
320 | ||
317dd50e | 321 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 322 | { |
317dd50e | 323 | struct dentry *debugfs_parent; |
93f0822d DB |
324 | int i = 0; |
325 | ||
2f86dc4c DB |
326 | if (hwp_active) |
327 | return; | |
93f0822d DB |
328 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
329 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
330 | return; | |
331 | while (pid_files[i].name) { | |
332 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
333 | debugfs_parent, pid_files[i].value, |
334 | &fops_pid_param); | |
93f0822d DB |
335 | i++; |
336 | } | |
337 | } | |
338 | ||
339 | /************************** debugfs end ************************/ | |
340 | ||
341 | /************************** sysfs begin ************************/ | |
342 | #define show_one(file_name, object) \ | |
343 | static ssize_t show_##file_name \ | |
344 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
345 | { \ | |
346 | return sprintf(buf, "%u\n", limits.object); \ | |
347 | } | |
348 | ||
d01b1f48 KCA |
349 | static ssize_t show_turbo_pct(struct kobject *kobj, |
350 | struct attribute *attr, char *buf) | |
351 | { | |
352 | struct cpudata *cpu; | |
353 | int total, no_turbo, turbo_pct; | |
354 | uint32_t turbo_fp; | |
355 | ||
356 | cpu = all_cpu_data[0]; | |
357 | ||
358 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
359 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
360 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
361 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
362 | return sprintf(buf, "%u\n", turbo_pct); | |
363 | } | |
364 | ||
0522424e KCA |
365 | static ssize_t show_num_pstates(struct kobject *kobj, |
366 | struct attribute *attr, char *buf) | |
367 | { | |
368 | struct cpudata *cpu; | |
369 | int total; | |
370 | ||
371 | cpu = all_cpu_data[0]; | |
372 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
373 | return sprintf(buf, "%u\n", total); | |
374 | } | |
375 | ||
4521e1a0 GM |
376 | static ssize_t show_no_turbo(struct kobject *kobj, |
377 | struct attribute *attr, char *buf) | |
378 | { | |
379 | ssize_t ret; | |
380 | ||
381 | update_turbo_state(); | |
382 | if (limits.turbo_disabled) | |
383 | ret = sprintf(buf, "%u\n", limits.turbo_disabled); | |
384 | else | |
385 | ret = sprintf(buf, "%u\n", limits.no_turbo); | |
386 | ||
387 | return ret; | |
388 | } | |
389 | ||
93f0822d | 390 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 391 | const char *buf, size_t count) |
93f0822d DB |
392 | { |
393 | unsigned int input; | |
394 | int ret; | |
845c1cbe | 395 | |
93f0822d DB |
396 | ret = sscanf(buf, "%u", &input); |
397 | if (ret != 1) | |
398 | return -EINVAL; | |
4521e1a0 GM |
399 | |
400 | update_turbo_state(); | |
dd5fbf70 | 401 | if (limits.turbo_disabled) { |
f16255eb | 402 | pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 403 | return -EPERM; |
dd5fbf70 | 404 | } |
2f86dc4c | 405 | |
4521e1a0 GM |
406 | limits.no_turbo = clamp_t(int, input, 0, 1); |
407 | ||
2f86dc4c DB |
408 | if (hwp_active) |
409 | intel_pstate_hwp_set(); | |
410 | ||
93f0822d DB |
411 | return count; |
412 | } | |
413 | ||
414 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 415 | const char *buf, size_t count) |
93f0822d DB |
416 | { |
417 | unsigned int input; | |
418 | int ret; | |
845c1cbe | 419 | |
93f0822d DB |
420 | ret = sscanf(buf, "%u", &input); |
421 | if (ret != 1) | |
422 | return -EINVAL; | |
423 | ||
d8f469e9 DB |
424 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
425 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d | 426 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
845c1cbe | 427 | |
2f86dc4c DB |
428 | if (hwp_active) |
429 | intel_pstate_hwp_set(); | |
93f0822d DB |
430 | return count; |
431 | } | |
432 | ||
433 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 434 | const char *buf, size_t count) |
93f0822d DB |
435 | { |
436 | unsigned int input; | |
437 | int ret; | |
845c1cbe | 438 | |
93f0822d DB |
439 | ret = sscanf(buf, "%u", &input); |
440 | if (ret != 1) | |
441 | return -EINVAL; | |
a0475992 KCA |
442 | |
443 | limits.min_sysfs_pct = clamp_t(int, input, 0 , 100); | |
444 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
93f0822d DB |
445 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); |
446 | ||
2f86dc4c DB |
447 | if (hwp_active) |
448 | intel_pstate_hwp_set(); | |
93f0822d DB |
449 | return count; |
450 | } | |
451 | ||
93f0822d DB |
452 | show_one(max_perf_pct, max_perf_pct); |
453 | show_one(min_perf_pct, min_perf_pct); | |
454 | ||
455 | define_one_global_rw(no_turbo); | |
456 | define_one_global_rw(max_perf_pct); | |
457 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 458 | define_one_global_ro(turbo_pct); |
0522424e | 459 | define_one_global_ro(num_pstates); |
93f0822d DB |
460 | |
461 | static struct attribute *intel_pstate_attributes[] = { | |
462 | &no_turbo.attr, | |
463 | &max_perf_pct.attr, | |
464 | &min_perf_pct.attr, | |
d01b1f48 | 465 | &turbo_pct.attr, |
0522424e | 466 | &num_pstates.attr, |
93f0822d DB |
467 | NULL |
468 | }; | |
469 | ||
470 | static struct attribute_group intel_pstate_attr_group = { | |
471 | .attrs = intel_pstate_attributes, | |
472 | }; | |
93f0822d | 473 | |
317dd50e | 474 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 475 | { |
317dd50e | 476 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
477 | int rc; |
478 | ||
479 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
480 | &cpu_subsys.dev_root->kobj); | |
481 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 482 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
483 | BUG_ON(rc); |
484 | } | |
93f0822d | 485 | /************************** sysfs end ************************/ |
2f86dc4c | 486 | |
ba88d433 | 487 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 488 | { |
f16255eb | 489 | pr_info("intel_pstate: HWP enabled\n"); |
2f86dc4c | 490 | |
ba88d433 | 491 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
492 | } |
493 | ||
19e77c28 DB |
494 | static int byt_get_min_pstate(void) |
495 | { | |
496 | u64 value; | |
845c1cbe | 497 | |
19e77c28 | 498 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 499 | return (value >> 8) & 0x7F; |
19e77c28 DB |
500 | } |
501 | ||
502 | static int byt_get_max_pstate(void) | |
503 | { | |
504 | u64 value; | |
845c1cbe | 505 | |
19e77c28 | 506 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 507 | return (value >> 16) & 0x7F; |
19e77c28 | 508 | } |
93f0822d | 509 | |
61d8d2ab DB |
510 | static int byt_get_turbo_pstate(void) |
511 | { | |
512 | u64 value; | |
845c1cbe | 513 | |
61d8d2ab | 514 | rdmsrl(BYT_TURBO_RATIOS, value); |
c16ed060 | 515 | return value & 0x7F; |
61d8d2ab DB |
516 | } |
517 | ||
007bea09 DB |
518 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
519 | { | |
520 | u64 val; | |
521 | int32_t vid_fp; | |
522 | u32 vid; | |
523 | ||
144c8e17 | 524 | val = (u64)pstate << 8; |
dd5fbf70 | 525 | if (limits.no_turbo && !limits.turbo_disabled) |
007bea09 DB |
526 | val |= (u64)1 << 32; |
527 | ||
528 | vid_fp = cpudata->vid.min + mul_fp( | |
529 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
530 | cpudata->vid.ratio); | |
531 | ||
532 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 533 | vid = ceiling_fp(vid_fp); |
007bea09 | 534 | |
21855ff5 DB |
535 | if (pstate > cpudata->pstate.max_pstate) |
536 | vid = cpudata->vid.turbo; | |
537 | ||
007bea09 DB |
538 | val |= vid; |
539 | ||
0dd23f94 | 540 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
007bea09 DB |
541 | } |
542 | ||
b27580b0 DB |
543 | #define BYT_BCLK_FREQS 5 |
544 | static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; | |
545 | ||
546 | static int byt_get_scaling(void) | |
547 | { | |
548 | u64 value; | |
549 | int i; | |
550 | ||
551 | rdmsrl(MSR_FSB_FREQ, value); | |
552 | i = value & 0x3; | |
553 | ||
554 | BUG_ON(i > BYT_BCLK_FREQS); | |
555 | ||
556 | return byt_freq_table[i] * 100; | |
557 | } | |
558 | ||
007bea09 DB |
559 | static void byt_get_vid(struct cpudata *cpudata) |
560 | { | |
561 | u64 value; | |
562 | ||
563 | rdmsrl(BYT_VIDS, value); | |
c16ed060 DB |
564 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
565 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
566 | cpudata->vid.ratio = div_fp( |
567 | cpudata->vid.max - cpudata->vid.min, | |
568 | int_tofp(cpudata->pstate.max_pstate - | |
569 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
570 | |
571 | rdmsrl(BYT_TURBO_VIDS, value); | |
572 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
573 | } |
574 | ||
016c8150 | 575 | static int core_get_min_pstate(void) |
93f0822d DB |
576 | { |
577 | u64 value; | |
845c1cbe | 578 | |
05e99c8c | 579 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
580 | return (value >> 40) & 0xFF; |
581 | } | |
582 | ||
016c8150 | 583 | static int core_get_max_pstate(void) |
93f0822d DB |
584 | { |
585 | u64 value; | |
845c1cbe | 586 | |
05e99c8c | 587 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
588 | return (value >> 8) & 0xFF; |
589 | } | |
590 | ||
016c8150 | 591 | static int core_get_turbo_pstate(void) |
93f0822d DB |
592 | { |
593 | u64 value; | |
594 | int nont, ret; | |
845c1cbe | 595 | |
05e99c8c | 596 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 597 | nont = core_get_max_pstate(); |
285cb990 | 598 | ret = (value) & 255; |
93f0822d DB |
599 | if (ret <= nont) |
600 | ret = nont; | |
601 | return ret; | |
602 | } | |
603 | ||
b27580b0 DB |
604 | static inline int core_get_scaling(void) |
605 | { | |
606 | return 100000; | |
607 | } | |
608 | ||
007bea09 | 609 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
610 | { |
611 | u64 val; | |
612 | ||
144c8e17 | 613 | val = (u64)pstate << 8; |
dd5fbf70 | 614 | if (limits.no_turbo && !limits.turbo_disabled) |
016c8150 DB |
615 | val |= (u64)1 << 32; |
616 | ||
bb18008f | 617 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
618 | } |
619 | ||
b34ef932 DC |
620 | static int knl_get_turbo_pstate(void) |
621 | { | |
622 | u64 value; | |
623 | int nont, ret; | |
624 | ||
625 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
626 | nont = core_get_max_pstate(); | |
627 | ret = (((value) >> 8) & 0xFF); | |
628 | if (ret <= nont) | |
629 | ret = nont; | |
630 | return ret; | |
631 | } | |
632 | ||
016c8150 DB |
633 | static struct cpu_defaults core_params = { |
634 | .pid_policy = { | |
635 | .sample_rate_ms = 10, | |
636 | .deadband = 0, | |
637 | .setpoint = 97, | |
638 | .p_gain_pct = 20, | |
639 | .d_gain_pct = 0, | |
640 | .i_gain_pct = 0, | |
641 | }, | |
642 | .funcs = { | |
643 | .get_max = core_get_max_pstate, | |
644 | .get_min = core_get_min_pstate, | |
645 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 646 | .get_scaling = core_get_scaling, |
016c8150 DB |
647 | .set = core_set_pstate, |
648 | }, | |
649 | }; | |
650 | ||
19e77c28 DB |
651 | static struct cpu_defaults byt_params = { |
652 | .pid_policy = { | |
653 | .sample_rate_ms = 10, | |
654 | .deadband = 0, | |
6a82ba6d | 655 | .setpoint = 60, |
19e77c28 DB |
656 | .p_gain_pct = 14, |
657 | .d_gain_pct = 0, | |
658 | .i_gain_pct = 4, | |
659 | }, | |
660 | .funcs = { | |
661 | .get_max = byt_get_max_pstate, | |
662 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 663 | .get_turbo = byt_get_turbo_pstate, |
007bea09 | 664 | .set = byt_set_pstate, |
b27580b0 | 665 | .get_scaling = byt_get_scaling, |
007bea09 | 666 | .get_vid = byt_get_vid, |
19e77c28 DB |
667 | }, |
668 | }; | |
669 | ||
b34ef932 DC |
670 | static struct cpu_defaults knl_params = { |
671 | .pid_policy = { | |
672 | .sample_rate_ms = 10, | |
673 | .deadband = 0, | |
674 | .setpoint = 97, | |
675 | .p_gain_pct = 20, | |
676 | .d_gain_pct = 0, | |
677 | .i_gain_pct = 0, | |
678 | }, | |
679 | .funcs = { | |
680 | .get_max = core_get_max_pstate, | |
681 | .get_min = core_get_min_pstate, | |
682 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 683 | .get_scaling = core_get_scaling, |
b34ef932 DC |
684 | .set = core_set_pstate, |
685 | }, | |
686 | }; | |
687 | ||
93f0822d DB |
688 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
689 | { | |
690 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 691 | int max_perf_adj; |
93f0822d | 692 | int min_perf; |
845c1cbe | 693 | |
4521e1a0 | 694 | if (limits.no_turbo || limits.turbo_disabled) |
93f0822d DB |
695 | max_perf = cpu->pstate.max_pstate; |
696 | ||
e0d4c8f8 KCA |
697 | /* |
698 | * performance can be limited by user through sysfs, by cpufreq | |
699 | * policy, or by cpu specific default values determined through | |
700 | * experimentation. | |
701 | */ | |
7244cb62 DB |
702 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
703 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
704 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
705 | ||
706 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
2d8d1f18 | 707 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
708 | } |
709 | ||
6c1e4591 | 710 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) |
93f0822d DB |
711 | { |
712 | int max_perf, min_perf; | |
713 | ||
6c1e4591 DS |
714 | if (force) { |
715 | update_turbo_state(); | |
93f0822d | 716 | |
6c1e4591 | 717 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
93f0822d | 718 | |
6c1e4591 | 719 | pstate = clamp_t(int, pstate, min_perf, max_perf); |
93f0822d | 720 | |
6c1e4591 DS |
721 | if (pstate == cpu->pstate.current_pstate) |
722 | return; | |
723 | } | |
b27580b0 | 724 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 725 | |
93f0822d | 726 | cpu->pstate.current_pstate = pstate; |
93f0822d | 727 | |
007bea09 | 728 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
729 | } |
730 | ||
93f0822d DB |
731 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
732 | { | |
016c8150 DB |
733 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
734 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
735 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
b27580b0 | 736 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 737 | |
007bea09 DB |
738 | if (pstate_funcs.get_vid) |
739 | pstate_funcs.get_vid(cpu); | |
6c1e4591 | 740 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
741 | } |
742 | ||
6b17ddb2 | 743 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 744 | { |
6b17ddb2 | 745 | struct sample *sample = &cpu->sample; |
bf810222 | 746 | int64_t core_pct; |
93f0822d | 747 | |
bf810222 | 748 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 749 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 750 | |
fcb6a15c | 751 | sample->freq = fp_toint( |
b27580b0 DB |
752 | mul_fp(int_tofp( |
753 | cpu->pstate.max_pstate * cpu->pstate.scaling / 100), | |
754 | core_pct)); | |
fcb6a15c | 755 | |
bf810222 | 756 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
757 | } |
758 | ||
759 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
760 | { | |
93f0822d | 761 | u64 aperf, mperf; |
4ab60c3f | 762 | unsigned long flags; |
4055fad3 | 763 | u64 tsc; |
93f0822d | 764 | |
4ab60c3f | 765 | local_irq_save(flags); |
93f0822d DB |
766 | rdmsrl(MSR_IA32_APERF, aperf); |
767 | rdmsrl(MSR_IA32_MPERF, mperf); | |
4ea1636b | 768 | tsc = rdtsc(); |
4ab60c3f | 769 | local_irq_restore(flags); |
b69880f9 | 770 | |
c4ee841f DB |
771 | cpu->last_sample_time = cpu->sample.time; |
772 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
773 | cpu->sample.aperf = aperf; |
774 | cpu->sample.mperf = mperf; | |
4055fad3 | 775 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
776 | cpu->sample.aperf -= cpu->prev_aperf; |
777 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 778 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 779 | |
6b17ddb2 | 780 | intel_pstate_calc_busy(cpu); |
93f0822d | 781 | |
93f0822d DB |
782 | cpu->prev_aperf = aperf; |
783 | cpu->prev_mperf = mperf; | |
4055fad3 | 784 | cpu->prev_tsc = tsc; |
93f0822d DB |
785 | } |
786 | ||
2f86dc4c DB |
787 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
788 | { | |
789 | int delay; | |
790 | ||
791 | delay = msecs_to_jiffies(50); | |
792 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
793 | } | |
794 | ||
93f0822d DB |
795 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
796 | { | |
abf013bf | 797 | int delay; |
93f0822d | 798 | |
abf013bf | 799 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
800 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
801 | } | |
802 | ||
d253d2a5 | 803 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 804 | { |
c4ee841f | 805 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
7180dddf | 806 | s64 duration_us; |
c4ee841f | 807 | u32 sample_time; |
93f0822d | 808 | |
e0d4c8f8 KCA |
809 | /* |
810 | * core_busy is the ratio of actual performance to max | |
811 | * max_pstate is the max non turbo pstate available | |
812 | * current_pstate was the pstate that was requested during | |
813 | * the last sample period. | |
814 | * | |
815 | * We normalize core_busy, which was our actual percent | |
816 | * performance to what we requested during the last sample | |
817 | * period. The result will be a percentage of busy at a | |
818 | * specified pstate. | |
819 | */ | |
d37e2b76 | 820 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 821 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 822 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 823 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 824 | |
e0d4c8f8 KCA |
825 | /* |
826 | * Since we have a deferred timer, it will not fire unless | |
827 | * we are in C0. So, determine if the actual elapsed time | |
828 | * is significantly greater (3x) than our sample interval. If it | |
829 | * is, then we were idle for a long enough period of time | |
830 | * to adjust our busyness. | |
831 | */ | |
285cb990 | 832 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
7180dddf PB |
833 | duration_us = ktime_us_delta(cpu->sample.time, |
834 | cpu->last_sample_time); | |
c4ee841f DB |
835 | if (duration_us > sample_time * 3) { |
836 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 837 | int_tofp(duration_us)); |
c4ee841f DB |
838 | core_busy = mul_fp(core_busy, sample_ratio); |
839 | } | |
840 | ||
f0fe3cd7 | 841 | return core_busy; |
93f0822d DB |
842 | } |
843 | ||
844 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
845 | { | |
d253d2a5 | 846 | int32_t busy_scaled; |
93f0822d | 847 | struct _pid *pid; |
4b707c89 | 848 | signed int ctl; |
4055fad3 DS |
849 | int from; |
850 | struct sample *sample; | |
851 | ||
852 | from = cpu->pstate.current_pstate; | |
93f0822d DB |
853 | |
854 | pid = &cpu->pid; | |
855 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
856 | ||
857 | ctl = pid_calc(pid, busy_scaled); | |
858 | ||
4b707c89 | 859 | /* Negative values of ctl increase the pstate and vice versa */ |
6c1e4591 | 860 | intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl, true); |
4055fad3 DS |
861 | |
862 | sample = &cpu->sample; | |
863 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
864 | fp_toint(busy_scaled), | |
865 | from, | |
866 | cpu->pstate.current_pstate, | |
867 | sample->mperf, | |
868 | sample->aperf, | |
869 | sample->tsc, | |
870 | sample->freq); | |
93f0822d DB |
871 | } |
872 | ||
2f86dc4c DB |
873 | static void intel_hwp_timer_func(unsigned long __data) |
874 | { | |
875 | struct cpudata *cpu = (struct cpudata *) __data; | |
876 | ||
877 | intel_pstate_sample(cpu); | |
878 | intel_hwp_set_sample_time(cpu); | |
879 | } | |
880 | ||
93f0822d DB |
881 | static void intel_pstate_timer_func(unsigned long __data) |
882 | { | |
883 | struct cpudata *cpu = (struct cpudata *) __data; | |
884 | ||
885 | intel_pstate_sample(cpu); | |
b69880f9 | 886 | |
ca182aee | 887 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 | 888 | |
93f0822d DB |
889 | intel_pstate_set_sample_time(cpu); |
890 | } | |
891 | ||
892 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
893 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
894 | (unsigned long)&policy } | |
93f0822d DB |
895 | |
896 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
897 | ICPU(0x2a, core_params), |
898 | ICPU(0x2d, core_params), | |
19e77c28 | 899 | ICPU(0x37, byt_params), |
016c8150 DB |
900 | ICPU(0x3a, core_params), |
901 | ICPU(0x3c, core_params), | |
c7e241df | 902 | ICPU(0x3d, core_params), |
016c8150 DB |
903 | ICPU(0x3e, core_params), |
904 | ICPU(0x3f, core_params), | |
905 | ICPU(0x45, core_params), | |
906 | ICPU(0x46, core_params), | |
43f8a966 | 907 | ICPU(0x47, core_params), |
16405f98 | 908 | ICPU(0x4c, byt_params), |
7ab0256e | 909 | ICPU(0x4e, core_params), |
c7e241df | 910 | ICPU(0x4f, core_params), |
1c939123 | 911 | ICPU(0x5e, core_params), |
c7e241df | 912 | ICPU(0x56, core_params), |
b34ef932 | 913 | ICPU(0x57, knl_params), |
93f0822d DB |
914 | {} |
915 | }; | |
916 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
917 | ||
2f86dc4c DB |
918 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
919 | ICPU(0x56, core_params), | |
920 | {} | |
921 | }; | |
922 | ||
93f0822d DB |
923 | static int intel_pstate_init_cpu(unsigned int cpunum) |
924 | { | |
93f0822d DB |
925 | struct cpudata *cpu; |
926 | ||
c0348717 DB |
927 | if (!all_cpu_data[cpunum]) |
928 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
929 | GFP_KERNEL); | |
93f0822d DB |
930 | if (!all_cpu_data[cpunum]) |
931 | return -ENOMEM; | |
932 | ||
933 | cpu = all_cpu_data[cpunum]; | |
934 | ||
93f0822d | 935 | cpu->cpu = cpunum; |
ba88d433 KCA |
936 | |
937 | if (hwp_active) | |
938 | intel_pstate_hwp_enable(cpu); | |
939 | ||
179e8471 | 940 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 941 | |
93f0822d | 942 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 943 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 944 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
945 | |
946 | if (!hwp_active) | |
947 | cpu->timer.function = intel_pstate_timer_func; | |
948 | else | |
949 | cpu->timer.function = intel_hwp_timer_func; | |
950 | ||
93f0822d | 951 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 952 | intel_pstate_sample(cpu); |
93f0822d DB |
953 | |
954 | add_timer_on(&cpu->timer, cpunum); | |
955 | ||
f16255eb | 956 | pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); |
93f0822d DB |
957 | |
958 | return 0; | |
959 | } | |
960 | ||
961 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
962 | { | |
963 | struct sample *sample; | |
964 | struct cpudata *cpu; | |
965 | ||
966 | cpu = all_cpu_data[cpu_num]; | |
967 | if (!cpu) | |
968 | return 0; | |
d37e2b76 | 969 | sample = &cpu->sample; |
93f0822d DB |
970 | return sample->freq; |
971 | } | |
972 | ||
973 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
974 | { | |
d3929b83 DB |
975 | if (!policy->cpuinfo.max_freq) |
976 | return -ENODEV; | |
977 | ||
630ec286 SP |
978 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
979 | policy->max >= policy->cpuinfo.max_freq) { | |
a0475992 | 980 | limits.min_policy_pct = 100; |
93f0822d DB |
981 | limits.min_perf_pct = 100; |
982 | limits.min_perf = int_tofp(1); | |
36b4bed5 | 983 | limits.max_policy_pct = 100; |
93f0822d DB |
984 | limits.max_perf_pct = 100; |
985 | limits.max_perf = int_tofp(1); | |
4521e1a0 | 986 | limits.no_turbo = 0; |
d1b68485 | 987 | return 0; |
93f0822d | 988 | } |
2f86dc4c | 989 | |
a0475992 KCA |
990 | limits.min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
991 | limits.min_policy_pct = clamp_t(int, limits.min_policy_pct, 0 , 100); | |
992 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
d1b68485 SP |
993 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); |
994 | ||
285cb990 | 995 | limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; |
d8f469e9 DB |
996 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); |
997 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 998 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d | 999 | |
2f86dc4c DB |
1000 | if (hwp_active) |
1001 | intel_pstate_hwp_set(); | |
1002 | ||
93f0822d DB |
1003 | return 0; |
1004 | } | |
1005 | ||
1006 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1007 | { | |
be49e346 | 1008 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1009 | |
285cb990 | 1010 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1011 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1012 | return -EINVAL; |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
bb18008f | 1017 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1018 | { |
bb18008f DB |
1019 | int cpu_num = policy->cpu; |
1020 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1021 | |
f16255eb | 1022 | pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); |
bb18008f | 1023 | |
c2294a2f | 1024 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
1025 | if (hwp_active) |
1026 | return; | |
1027 | ||
6c1e4591 | 1028 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
1029 | } |
1030 | ||
2760984f | 1031 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1032 | { |
93f0822d | 1033 | struct cpudata *cpu; |
52e0a509 | 1034 | int rc; |
93f0822d DB |
1035 | |
1036 | rc = intel_pstate_init_cpu(policy->cpu); | |
1037 | if (rc) | |
1038 | return rc; | |
1039 | ||
1040 | cpu = all_cpu_data[policy->cpu]; | |
1041 | ||
dd5fbf70 | 1042 | if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) |
93f0822d DB |
1043 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1044 | else | |
1045 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1046 | ||
b27580b0 DB |
1047 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1048 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1049 | |
1050 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1051 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1052 | policy->cpuinfo.max_freq = | |
1053 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1054 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1055 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static struct cpufreq_driver intel_pstate_driver = { | |
1061 | .flags = CPUFREQ_CONST_LOOPS, | |
1062 | .verify = intel_pstate_verify_policy, | |
1063 | .setpolicy = intel_pstate_set_policy, | |
1064 | .get = intel_pstate_get, | |
1065 | .init = intel_pstate_cpu_init, | |
bb18008f | 1066 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1067 | .name = "intel_pstate", |
93f0822d DB |
1068 | }; |
1069 | ||
6be26498 | 1070 | static int __initdata no_load; |
2f86dc4c | 1071 | static int __initdata no_hwp; |
d64c3b0b | 1072 | static int __initdata hwp_only; |
aa4ea34d | 1073 | static unsigned int force_load; |
6be26498 | 1074 | |
b563b4e3 DB |
1075 | static int intel_pstate_msrs_not_valid(void) |
1076 | { | |
016c8150 | 1077 | if (!pstate_funcs.get_max() || |
c410833a SK |
1078 | !pstate_funcs.get_min() || |
1079 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1080 | return -ENODEV; |
1081 | ||
b563b4e3 DB |
1082 | return 0; |
1083 | } | |
016c8150 | 1084 | |
e0a261a2 | 1085 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1086 | { |
1087 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1088 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1089 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1090 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1091 | pid_params.deadband = policy->deadband; | |
1092 | pid_params.setpoint = policy->setpoint; | |
1093 | } | |
1094 | ||
e0a261a2 | 1095 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1096 | { |
1097 | pstate_funcs.get_max = funcs->get_max; | |
1098 | pstate_funcs.get_min = funcs->get_min; | |
1099 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1100 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1101 | pstate_funcs.set = funcs->set; |
007bea09 | 1102 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
1103 | } |
1104 | ||
fbbcdc07 AH |
1105 | #if IS_ENABLED(CONFIG_ACPI) |
1106 | #include <acpi/processor.h> | |
1107 | ||
1108 | static bool intel_pstate_no_acpi_pss(void) | |
1109 | { | |
1110 | int i; | |
1111 | ||
1112 | for_each_possible_cpu(i) { | |
1113 | acpi_status status; | |
1114 | union acpi_object *pss; | |
1115 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1116 | struct acpi_processor *pr = per_cpu(processors, i); | |
1117 | ||
1118 | if (!pr) | |
1119 | continue; | |
1120 | ||
1121 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1122 | if (ACPI_FAILURE(status)) | |
1123 | continue; | |
1124 | ||
1125 | pss = buffer.pointer; | |
1126 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1127 | kfree(pss); | |
1128 | return false; | |
1129 | } | |
1130 | ||
1131 | kfree(pss); | |
1132 | } | |
1133 | ||
1134 | return true; | |
1135 | } | |
1136 | ||
966916ea | 1137 | static bool intel_pstate_has_acpi_ppc(void) |
1138 | { | |
1139 | int i; | |
1140 | ||
1141 | for_each_possible_cpu(i) { | |
1142 | struct acpi_processor *pr = per_cpu(processors, i); | |
1143 | ||
1144 | if (!pr) | |
1145 | continue; | |
1146 | if (acpi_has_method(pr->handle, "_PPC")) | |
1147 | return true; | |
1148 | } | |
1149 | return false; | |
1150 | } | |
1151 | ||
1152 | enum { | |
1153 | PSS, | |
1154 | PPC, | |
1155 | }; | |
1156 | ||
fbbcdc07 AH |
1157 | struct hw_vendor_info { |
1158 | u16 valid; | |
1159 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1160 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1161 | int oem_pwr_table; |
fbbcdc07 AH |
1162 | }; |
1163 | ||
1164 | /* Hardware vendor-specific info that has its own power management modes */ | |
1165 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1166 | {1, "HP ", "ProLiant", PSS}, |
1167 | {1, "ORACLE", "X4-2 ", PPC}, | |
1168 | {1, "ORACLE", "X4-2L ", PPC}, | |
1169 | {1, "ORACLE", "X4-2B ", PPC}, | |
1170 | {1, "ORACLE", "X3-2 ", PPC}, | |
1171 | {1, "ORACLE", "X3-2L ", PPC}, | |
1172 | {1, "ORACLE", "X3-2B ", PPC}, | |
1173 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1174 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1175 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1176 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1177 | {1, "ORACLE", "X4170 M3", PPC}, |
1178 | {1, "ORACLE", "X4275 M3", PPC}, | |
1179 | {1, "ORACLE", "X6-2 ", PPC}, | |
1180 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1181 | {0, "", ""}, |
1182 | }; | |
1183 | ||
1184 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1185 | { | |
1186 | struct acpi_table_header hdr; | |
1187 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1188 | const struct x86_cpu_id *id; |
1189 | u64 misc_pwr; | |
1190 | ||
1191 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1192 | if (id) { | |
1193 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1194 | if ( misc_pwr & (1 << 8)) | |
1195 | return true; | |
1196 | } | |
fbbcdc07 | 1197 | |
c410833a SK |
1198 | if (acpi_disabled || |
1199 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1200 | return false; |
1201 | ||
1202 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1203 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1204 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1205 | ACPI_OEM_TABLE_ID_SIZE)) | |
1206 | switch (v_info->oem_pwr_table) { | |
1207 | case PSS: | |
1208 | return intel_pstate_no_acpi_pss(); | |
1209 | case PPC: | |
aa4ea34d EZ |
1210 | return intel_pstate_has_acpi_ppc() && |
1211 | (!force_load); | |
966916ea | 1212 | } |
fbbcdc07 AH |
1213 | } |
1214 | ||
1215 | return false; | |
1216 | } | |
1217 | #else /* CONFIG_ACPI not enabled */ | |
1218 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1219 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1220 | #endif /* CONFIG_ACPI */ |
1221 | ||
93f0822d DB |
1222 | static int __init intel_pstate_init(void) |
1223 | { | |
907cc908 | 1224 | int cpu, rc = 0; |
93f0822d | 1225 | const struct x86_cpu_id *id; |
64df1fdf | 1226 | struct cpu_defaults *cpu_def; |
93f0822d | 1227 | |
6be26498 DB |
1228 | if (no_load) |
1229 | return -ENODEV; | |
1230 | ||
93f0822d DB |
1231 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1232 | if (!id) | |
1233 | return -ENODEV; | |
1234 | ||
fbbcdc07 AH |
1235 | /* |
1236 | * The Intel pstate driver will be ignored if the platform | |
1237 | * firmware has its own power management modes. | |
1238 | */ | |
1239 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1240 | return -ENODEV; | |
1241 | ||
64df1fdf | 1242 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1243 | |
64df1fdf BP |
1244 | copy_pid_params(&cpu_def->pid_policy); |
1245 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1246 | |
b563b4e3 DB |
1247 | if (intel_pstate_msrs_not_valid()) |
1248 | return -ENODEV; | |
1249 | ||
93f0822d DB |
1250 | pr_info("Intel P-state driver initializing.\n"); |
1251 | ||
b57ffac5 | 1252 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1253 | if (!all_cpu_data) |
1254 | return -ENOMEM; | |
93f0822d | 1255 | |
64df1fdf | 1256 | if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) |
ba88d433 | 1257 | hwp_active++; |
2f86dc4c | 1258 | |
d64c3b0b KCA |
1259 | if (!hwp_active && hwp_only) |
1260 | goto out; | |
1261 | ||
93f0822d DB |
1262 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1263 | if (rc) | |
1264 | goto out; | |
1265 | ||
1266 | intel_pstate_debug_expose_params(); | |
1267 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1268 | |
93f0822d DB |
1269 | return rc; |
1270 | out: | |
907cc908 DB |
1271 | get_online_cpus(); |
1272 | for_each_online_cpu(cpu) { | |
1273 | if (all_cpu_data[cpu]) { | |
1274 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1275 | kfree(all_cpu_data[cpu]); | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | put_online_cpus(); | |
1280 | vfree(all_cpu_data); | |
93f0822d DB |
1281 | return -ENODEV; |
1282 | } | |
1283 | device_initcall(intel_pstate_init); | |
1284 | ||
6be26498 DB |
1285 | static int __init intel_pstate_setup(char *str) |
1286 | { | |
1287 | if (!str) | |
1288 | return -EINVAL; | |
1289 | ||
1290 | if (!strcmp(str, "disable")) | |
1291 | no_load = 1; | |
2f86dc4c DB |
1292 | if (!strcmp(str, "no_hwp")) |
1293 | no_hwp = 1; | |
aa4ea34d EZ |
1294 | if (!strcmp(str, "force")) |
1295 | force_load = 1; | |
d64c3b0b KCA |
1296 | if (!strcmp(str, "hwp_only")) |
1297 | hwp_only = 1; | |
6be26498 DB |
1298 | return 0; |
1299 | } | |
1300 | early_param("intel_pstate", intel_pstate_setup); | |
1301 | ||
93f0822d DB |
1302 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1303 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1304 | MODULE_LICENSE("GPL"); |