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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[linux-2.6-block.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
55687da1 22#include <linux/sched/cpufreq.h>
93f0822d
DB		 23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/debugfs.h>
fbbcdc07 30#include <linux/acpi.h>
d6472302 31#include <linux/vmalloc.h>
93f0822d
DB		 32#include <trace/events/power.h>
33
34#include <asm/div64.h>
35#include <asm/msr.h>
36#include <asm/cpu_device_id.h>
64df1fdf 37#include <asm/cpufeature.h>
5b20c944 38#include <asm/intel-family.h>
93f0822d 39
001c76f0
RW		 40#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41
9522a2ff
SP		 42#ifdef CONFIG_ACPI
43#include <acpi/processor.h>
17669006 44#include <acpi/cppc_acpi.h>
9522a2ff
SP		 45#endif
46
f0fe3cd7 47#define FRAC_BITS 8
93f0822d
DB		 48#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 50
a1c9787d
RW		 51#define EXT_BITS 6
52#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 53#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 55
93f0822d
DB		 56static inline int32_t mul_fp(int32_t x, int32_t y)
57{
58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
59}
60
7180dddf 61static inline int32_t div_fp(s64 x, s64 y)
93f0822d 62{
7180dddf 63 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 64}
65
d022a65e
DB		 66static inline int ceiling_fp(int32_t x)
67{
68 int mask, ret;
69
70 ret = fp_toint(x);
71 mask = (1 << FRAC_BITS) - 1;
72 if (x & mask)
73 ret += 1;
74 return ret;
75}
76
a1c9787d
RW		 77static inline u64 mul_ext_fp(u64 x, u64 y)
78{
79 return (x * y) >> EXT_FRAC_BITS;
80}
81
82static inline u64 div_ext_fp(u64 x, u64 y)
83{
84 return div64_u64(x << EXT_FRAC_BITS, y);
85}
86
13ad7701
SP		 87/**
88 * struct sample - Store performance sample
a1c9787d 89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 90 * performance during last sample period
91 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 92 * P state. This can be different than core_avg_perf
13ad7701
SP		 93 * to account for cpu idle period
94 * @aperf: Difference of actual performance frequency clock count
95 * read from APERF MSR between last and current sample
96 * @mperf: Difference of maximum performance frequency clock count
97 * read from MPERF MSR between last and current sample
98 * @tsc: Difference of time stamp counter between last and
99 * current sample
13ad7701
SP		 100 * @time: Current time from scheduler
101 *
102 * This structure is used in the cpudata structure to store performance sample
103 * data for choosing next P State.
104 */
93f0822d 105struct sample {
a1c9787d 106 int32_t core_avg_perf;
157386b6 107 int32_t busy_scaled;
93f0822d
DB		 108 u64 aperf;
109 u64 mperf;
4055fad3 110 u64 tsc;
a4675fbc 111 u64 time;
93f0822d
DB		 112};
113
13ad7701
SP		 114/**
115 * struct pstate_data - Store P state data
116 * @current_pstate: Current requested P state
117 * @min_pstate: Min P state possible for this platform
118 * @max_pstate: Max P state possible for this platform
119 * @max_pstate_physical:This is physical Max P state for a processor
120 * This can be higher than the max_pstate which can
121 * be limited by platform thermal design power limits
122 * @scaling: Scaling factor to convert frequency to cpufreq
123 * frequency units
124 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 125 * @max_freq: @max_pstate frequency in cpufreq units
126 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 127 *
128 * Stores the per cpu model P state limits and current P state.
129 */
93f0822d
DB		 130struct pstate_data {
131 int current_pstate;
132 int min_pstate;
133 int max_pstate;
3bcc6fa9 134 int max_pstate_physical;
b27580b0 135 int scaling;
93f0822d 136 int turbo_pstate;
001c76f0
RW		 137 unsigned int max_freq;
138 unsigned int turbo_freq;
93f0822d
DB		 139};
140
13ad7701
SP		 141/**
142 * struct vid_data - Stores voltage information data
143 * @min: VID data for this platform corresponding to
144 * the lowest P state
145 * @max: VID data corresponding to the highest P State.
146 * @turbo: VID data for turbo P state
147 * @ratio: Ratio of (vid max - vid min) /
148 * (max P state - Min P State)
149 *
150 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
151 * This data is used in Atom platforms, where in addition to target P state,
152 * the voltage data needs to be specified to select next P State.
153 */
007bea09 154struct vid_data {
21855ff5
DB		 155 int min;
156 int max;
157 int turbo;
007bea09
DB		 158 int32_t ratio;
159};
160
13ad7701
SP		 161/**
162 * struct _pid - Stores PID data
163 * @setpoint: Target set point for busyness or performance
164 * @integral: Storage for accumulated error values
165 * @p_gain: PID proportional gain
166 * @i_gain: PID integral gain
167 * @d_gain: PID derivative gain
168 * @deadband: PID deadband
169 * @last_err: Last error storage for integral part of PID calculation
170 *
171 * Stores PID coefficients and last error for PID controller.
172 */
93f0822d
DB		 173struct _pid {
174 int setpoint;
175 int32_t integral;
176 int32_t p_gain;
177 int32_t i_gain;
178 int32_t d_gain;
179 int deadband;
d253d2a5 180 int32_t last_err;
93f0822d
DB		 181};
182
eae48f04
SP		 183/**
184 * struct perf_limits - Store user and policy limits
185 * @no_turbo: User requested turbo state from intel_pstate sysfs
186 * @turbo_disabled: Platform turbo status either from msr
187 * MSR_IA32_MISC_ENABLE or when maximum available pstate
188 * matches the maximum turbo pstate
189 * @max_perf_pct: Effective maximum performance limit in percentage, this
190 * is minimum of either limits enforced by cpufreq policy
191 * or limits from user set limits via intel_pstate sysfs
192 * @min_perf_pct: Effective minimum performance limit in percentage, this
193 * is maximum of either limits enforced by cpufreq policy
194 * or limits from user set limits via intel_pstate sysfs
195 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
196 * This value is used to limit max pstate
197 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
198 * This value is used to limit min pstate
199 * @max_policy_pct: The maximum performance in percentage enforced by
200 * cpufreq setpolicy interface
201 * @max_sysfs_pct: The maximum performance in percentage enforced by
202 * intel pstate sysfs interface, unused when per cpu
203 * controls are enforced
204 * @min_policy_pct: The minimum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @min_sysfs_pct: The minimum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
209 *
210 * Storage for user and policy defined limits.
211 */
212struct perf_limits {
213 int no_turbo;
214 int turbo_disabled;
215 int max_perf_pct;
216 int min_perf_pct;
217 int32_t max_perf;
218 int32_t min_perf;
219 int max_policy_pct;
220 int max_sysfs_pct;
221 int min_policy_pct;
222 int min_sysfs_pct;
223};
224
13ad7701
SP		 225/**
226 * struct cpudata - Per CPU instance data storage
227 * @cpu: CPU number for this instance data
2f1d407a 228 * @policy: CPUFreq policy value
13ad7701 229 * @update_util: CPUFreq utility callback information
4578ee7e 230 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 231 * @iowait_boost: iowait-related boost fraction
232 * @last_update: Time of the last update.
13ad7701
SP		 233 * @pstate: Stores P state limits for this CPU
234 * @vid: Stores VID limits for this CPU
235 * @pid: Stores PID parameters for this CPU
236 * @last_sample_time: Last Sample time
237 * @prev_aperf: Last APERF value read from APERF MSR
238 * @prev_mperf: Last MPERF value read from MPERF MSR
239 * @prev_tsc: Last timestamp counter (TSC) value
240 * @prev_cummulative_iowait: IO Wait time difference from last and
241 * current sample
242 * @sample: Storage for storing last Sample data
eae48f04
SP		 243 * @perf_limits: Pointer to perf_limit unique to this CPU
244 * Not all field in the structure are applicable
245 * when per cpu controls are enforced
9522a2ff
SP		 246 * @acpi_perf_data: Stores ACPI perf information read from _PSS
247 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 248 * @epp_powersave: Last saved HWP energy performance preference
249 * (EPP) or energy performance bias (EPB),
250 * when policy switched to performance
8442885f 251 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 252 * @epp_default: Power on default HWP energy performance
253 * preference/bias
254 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
255 * operation
13ad7701
SP		 256 *
257 * This structure stores per CPU instance data for all CPUs.
258 */
93f0822d
DB		 259struct cpudata {
260 int cpu;
261
2f1d407a 262 unsigned int policy;
a4675fbc 263 struct update_util_data update_util;
4578ee7e 264 bool update_util_set;
93f0822d 265
93f0822d 266 struct pstate_data pstate;
007bea09 267 struct vid_data vid;
93f0822d 268 struct _pid pid;
93f0822d 269
09c448d3 270 u64 last_update;
a4675fbc 271 u64 last_sample_time;
93f0822d
DB		 272 u64 prev_aperf;
273 u64 prev_mperf;
4055fad3 274 u64 prev_tsc;
63d1d656 275 u64 prev_cummulative_iowait;
d37e2b76 276 struct sample sample;
eae48f04 277 struct perf_limits *perf_limits;
9522a2ff
SP		 278#ifdef CONFIG_ACPI
279 struct acpi_processor_performance acpi_perf_data;
280 bool valid_pss_table;
281#endif
09c448d3 282 unsigned int iowait_boost;
984edbdc 283 s16 epp_powersave;
8442885f 284 s16 epp_policy;
984edbdc
SP		 285 s16 epp_default;
286 s16 epp_saved;
93f0822d
DB		 287};
288
289static struct cpudata **all_cpu_data;
13ad7701
SP		 290
291/**
3954517e 292 * struct pstate_adjust_policy - Stores static PID configuration data
13ad7701
SP		 293 * @sample_rate_ms: PID calculation sample rate in ms
294 * @sample_rate_ns: Sample rate calculation in ns
295 * @deadband: PID deadband
296 * @setpoint: PID Setpoint
297 * @p_gain_pct: PID proportional gain
298 * @i_gain_pct: PID integral gain
299 * @d_gain_pct: PID derivative gain
300 *
301 * Stores per CPU model static PID configuration data.
302 */
93f0822d
DB		 303struct pstate_adjust_policy {
304 int sample_rate_ms;
a4675fbc 305 s64 sample_rate_ns;
93f0822d
DB		 306 int deadband;
307 int setpoint;
308 int p_gain_pct;
309 int d_gain_pct;
310 int i_gain_pct;
311};
312
13ad7701
SP		 313/**
314 * struct pstate_funcs - Per CPU model specific callbacks
315 * @get_max: Callback to get maximum non turbo effective P state
316 * @get_max_physical: Callback to get maximum non turbo physical P state
317 * @get_min: Callback to get minimum P state
318 * @get_turbo: Callback to get turbo P state
319 * @get_scaling: Callback to get frequency scaling factor
320 * @get_val: Callback to convert P state to actual MSR write value
321 * @get_vid: Callback to get VID data for Atom platforms
322 * @get_target_pstate: Callback to a function to calculate next P state to use
323 *
324 * Core and Atom CPU models have different way to get P State limits. This
325 * structure is used to store those callbacks.
326 */
016c8150
DB		 327struct pstate_funcs {
328 int (*get_max)(void);
3bcc6fa9 329 int (*get_max_physical)(void);
016c8150
DB		 330 int (*get_min)(void);
331 int (*get_turbo)(void);
b27580b0 332 int (*get_scaling)(void);
fdfdb2b1 333 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 334 void (*get_vid)(struct cpudata *);
157386b6 335 int32_t (*get_target_pstate)(struct cpudata *);
93f0822d
DB		 336};
337
13ad7701
SP		 338/**
339 * struct cpu_defaults- Per CPU model default config data
340 * @pid_policy: PID config data
341 * @funcs: Callback function data
342 */
016c8150
DB		 343struct cpu_defaults {
344 struct pstate_adjust_policy pid_policy;
345 struct pstate_funcs funcs;
93f0822d
DB		 346};
347
157386b6 348static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
e70eed2b 349static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
157386b6 350
4a7cb7a9
JZ		 351static struct pstate_adjust_policy pid_params __read_mostly;
352static struct pstate_funcs pstate_funcs __read_mostly;
353static int hwp_active __read_mostly;
eae48f04 354static bool per_cpu_limits __read_mostly;
016c8150 355
0c30b65b
RW		 356static bool driver_registered __read_mostly;
357
9522a2ff
SP		 358#ifdef CONFIG_ACPI
359static bool acpi_ppc;
360#endif
13ad7701 361
c3a49c89
RW		 362static struct perf_limits performance_limits;
363static struct perf_limits powersave_limits;
364static struct perf_limits *limits;
51443fbf 365
c3a49c89
RW		 366static void intel_pstate_init_limits(struct perf_limits *limits)
367{
368 memset(limits, 0, sizeof(*limits));
369 limits->max_perf_pct = 100;
370 limits->max_perf = int_ext_tofp(1);
371 limits->max_policy_pct = 100;
372 limits->max_sysfs_pct = 100;
373}
93f0822d 374
c3a49c89
RW		 375static void intel_pstate_set_performance_limits(struct perf_limits *limits)
376{
377 intel_pstate_init_limits(limits);
378 limits->min_perf_pct = 100;
379 limits->min_perf = int_ext_tofp(1);
380}
51443fbf 381
0c30b65b 382static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 383static DEFINE_MUTEX(intel_pstate_limits_lock);
384
9522a2ff 385#ifdef CONFIG_ACPI
2b3ec765
SP		 386
387static bool intel_pstate_get_ppc_enable_status(void)
388{
389 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
390 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
391 return true;
392
393 return acpi_ppc;
394}
395
17669006
RW		 396#ifdef CONFIG_ACPI_CPPC_LIB
397
398/* The work item is needed to avoid CPU hotplug locking issues */
399static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
400{
401 sched_set_itmt_support();
402}
403
404static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
405
406static void intel_pstate_set_itmt_prio(int cpu)
407{
408 struct cppc_perf_caps cppc_perf;
409 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
410 int ret;
411
412 ret = cppc_get_perf_caps(cpu, &cppc_perf);
413 if (ret)
414 return;
415
416 /*
417 * The priorities can be set regardless of whether or not
418 * sched_set_itmt_support(true) has been called and it is valid to
419 * update them at any time after it has been called.
420 */
421 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
422
423 if (max_highest_perf <= min_highest_perf) {
424 if (cppc_perf.highest_perf > max_highest_perf)
425 max_highest_perf = cppc_perf.highest_perf;
426
427 if (cppc_perf.highest_perf < min_highest_perf)
428 min_highest_perf = cppc_perf.highest_perf;
429
430 if (max_highest_perf > min_highest_perf) {
431 /*
432 * This code can be run during CPU online under the
433 * CPU hotplug locks, so sched_set_itmt_support()
434 * cannot be called from here. Queue up a work item
435 * to invoke it.
436 */
437 schedule_work(&sched_itmt_work);
438 }
439 }
440}
441#else
442static void intel_pstate_set_itmt_prio(int cpu)
443{
444}
445#endif
446
9522a2ff
SP		 447static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
448{
449 struct cpudata *cpu;
9522a2ff
SP		 450 int ret;
451 int i;
452
17669006
RW		 453 if (hwp_active) {
454 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 455 return;
17669006 456 }
e59a8f7f 457
2b3ec765 458 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 459 return;
460
461 cpu = all_cpu_data[policy->cpu];
462
463 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
464 policy->cpu);
465 if (ret)
466 return;
467
468 /*
469 * Check if the control value in _PSS is for PERF_CTL MSR, which should
470 * guarantee that the states returned by it map to the states in our
471 * list directly.
472 */
473 if (cpu->acpi_perf_data.control_register.space_id !=
474 ACPI_ADR_SPACE_FIXED_HARDWARE)
475 goto err;
476
477 /*
478 * If there is only one entry _PSS, simply ignore _PSS and continue as
479 * usual without taking _PSS into account
480 */
481 if (cpu->acpi_perf_data.state_count < 2)
482 goto err;
483
484 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
485 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
486 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
487 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
488 (u32) cpu->acpi_perf_data.states[i].core_frequency,
489 (u32) cpu->acpi_perf_data.states[i].power,
490 (u32) cpu->acpi_perf_data.states[i].control);
491 }
492
493 /*
494 * The _PSS table doesn't contain whole turbo frequency range.
495 * This just contains +1 MHZ above the max non turbo frequency,
496 * with control value corresponding to max turbo ratio. But
497 * when cpufreq set policy is called, it will call with this
498 * max frequency, which will cause a reduced performance as
499 * this driver uses real max turbo frequency as the max
500 * frequency. So correct this frequency in _PSS table to
b00345d1 501 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 502 * Also need to convert to MHz as _PSS freq is in MHz.
503 */
b00345d1 504 if (!limits->turbo_disabled)
9522a2ff
SP		 505 cpu->acpi_perf_data.states[0].core_frequency =
506 policy->cpuinfo.max_freq / 1000;
507 cpu->valid_pss_table = true;
6cacd115 508 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 509
510 return;
511
512 err:
513 cpu->valid_pss_table = false;
514 acpi_processor_unregister_performance(policy->cpu);
515}
516
517static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
518{
519 struct cpudata *cpu;
520
521 cpu = all_cpu_data[policy->cpu];
522 if (!cpu->valid_pss_table)
523 return;
524
525 acpi_processor_unregister_performance(policy->cpu);
526}
9522a2ff 527#else
7a3ba767 528static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 529{
530}
531
7a3ba767 532static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 533{
534}
535#endif
536
93f0822d 537static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
c410833a 538 int deadband, int integral) {
b54a0dfd
PL		 539 pid->setpoint = int_tofp(setpoint);
540 pid->deadband = int_tofp(deadband);
93f0822d 541 pid->integral = int_tofp(integral);
d98d099b 542 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB		 543}
544
545static inline void pid_p_gain_set(struct _pid *pid, int percent)
546{
22590efb 547 pid->p_gain = div_fp(percent, 100);
93f0822d
DB		 548}
549
550static inline void pid_i_gain_set(struct _pid *pid, int percent)
551{
22590efb 552 pid->i_gain = div_fp(percent, 100);
93f0822d
DB		 553}
554
555static inline void pid_d_gain_set(struct _pid *pid, int percent)
556{
22590efb 557 pid->d_gain = div_fp(percent, 100);
93f0822d
DB		 558}
559
d253d2a5 560static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 561{
d253d2a5 562 signed int result;
93f0822d
DB		 563 int32_t pterm, dterm, fp_error;
564 int32_t integral_limit;
565
b54a0dfd 566 fp_error = pid->setpoint - busy;
93f0822d 567
b54a0dfd 568 if (abs(fp_error) <= pid->deadband)
93f0822d
DB		 569 return 0;
570
571 pterm = mul_fp(pid->p_gain, fp_error);
572
573 pid->integral += fp_error;
574
e0d4c8f8
KCA		 575 /*
576 * We limit the integral here so that it will never
577 * get higher than 30. This prevents it from becoming
578 * too large an input over long periods of time and allows
579 * it to get factored out sooner.
580 *
581 * The value of 30 was chosen through experimentation.
582 */
93f0822d
DB		 583 integral_limit = int_tofp(30);
584 if (pid->integral > integral_limit)
585 pid->integral = integral_limit;
586 if (pid->integral < -integral_limit)
587 pid->integral = -integral_limit;
588
d253d2a5
BS		 589 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
590 pid->last_err = fp_error;
93f0822d
DB		 591
592 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
51d211e9 593 result = result + (1 << (FRAC_BITS-1));
93f0822d
DB		 594 return (signed int)fp_toint(result);
595}
596
597static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
598{
016c8150
DB		 599 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
600 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
601 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d 602
2d8d1f18 603 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
93f0822d
DB		 604}
605
93f0822d
DB		 606static inline void intel_pstate_reset_all_pid(void)
607{
608 unsigned int cpu;
845c1cbe 609
93f0822d
DB		 610 for_each_online_cpu(cpu) {
611 if (all_cpu_data[cpu])
612 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
613 }
614}
615
4521e1a0
GM		 616static inline void update_turbo_state(void)
617{
618 u64 misc_en;
619 struct cpudata *cpu;
620
621 cpu = all_cpu_data[0];
622 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
51443fbf 623 limits->turbo_disabled =
4521e1a0
GM		 624 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
625 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
626}
627
8442885f
SP		 628static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
629{
630 u64 epb;
631 int ret;
632
633 if (!static_cpu_has(X86_FEATURE_EPB))
634 return -ENXIO;
635
636 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
637 if (ret)
638 return (s16)ret;
639
640 return (s16)(epb & 0x0f);
641}
642
643static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
644{
645 s16 epp;
646
984edbdc
SP		 647 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
648 /*
649 * When hwp_req_data is 0, means that caller didn't read
650 * MSR_HWP_REQUEST, so need to read and get EPP.
651 */
652 if (!hwp_req_data) {
653 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
654 &hwp_req_data);
655 if (epp)
656 return epp;
657 }
8442885f 658 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 659 } else {
8442885f
SP		 660 /* When there is no EPP present, HWP uses EPB settings */
661 epp = intel_pstate_get_epb(cpu_data);
984edbdc 662 }
8442885f
SP		 663
664 return epp;
665}
666
984edbdc 667static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 668{
669 u64 epb;
984edbdc 670 int ret;
8442885f
SP		 671
672 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 673 return -ENXIO;
8442885f 674
984edbdc
SP		 675 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
676 if (ret)
677 return ret;
8442885f
SP		 678
679 epb = (epb & ~0x0f) | pref;
680 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 681
682 return 0;
8442885f
SP		 683}
684
984edbdc
SP		 685/*
686 * EPP/EPB display strings corresponding to EPP index in the
687 * energy_perf_strings[]
688 * index String
689 *-------------------------------------
690 * 0 default
691 * 1 performance
692 * 2 balance_performance
693 * 3 balance_power
694 * 4 power
695 */
696static const char * const energy_perf_strings[] = {
697 "default",
698 "performance",
699 "balance_performance",
700 "balance_power",
701 "power",
702 NULL
703};
704
705static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
706{
707 s16 epp;
708 int index = -EINVAL;
709
710 epp = intel_pstate_get_epp(cpu_data, 0);
711 if (epp < 0)
712 return epp;
713
714 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
715 /*
716 * Range:
717 * 0x00-0x3F : Performance
718 * 0x40-0x7F : Balance performance
719 * 0x80-0xBF : Balance power
720 * 0xC0-0xFF : Power
721 * The EPP is a 8 bit value, but our ranges restrict the
722 * value which can be set. Here only using top two bits
723 * effectively.
724 */
725 index = (epp >> 6) + 1;
726 } else if (static_cpu_has(X86_FEATURE_EPB)) {
727 /*
728 * Range:
729 * 0x00-0x03 : Performance
730 * 0x04-0x07 : Balance performance
731 * 0x08-0x0B : Balance power
732 * 0x0C-0x0F : Power
733 * The EPB is a 4 bit value, but our ranges restrict the
734 * value which can be set. Here only using top two bits
735 * effectively.
736 */
737 index = (epp >> 2) + 1;
738 }
739
740 return index;
741}
742
743static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
744 int pref_index)
745{
746 int epp = -EINVAL;
747 int ret;
748
749 if (!pref_index)
750 epp = cpu_data->epp_default;
751
752 mutex_lock(&intel_pstate_limits_lock);
753
754 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
755 u64 value;
756
757 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
758 if (ret)
759 goto return_pref;
760
761 value &= ~GENMASK_ULL(31, 24);
762
763 /*
764 * If epp is not default, convert from index into
765 * energy_perf_strings to epp value, by shifting 6
766 * bits left to use only top two bits in epp.
767 * The resultant epp need to shifted by 24 bits to
768 * epp position in MSR_HWP_REQUEST.
769 */
770 if (epp == -EINVAL)
771 epp = (pref_index - 1) << 6;
772
773 value |= (u64)epp << 24;
774 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
775 } else {
776 if (epp == -EINVAL)
777 epp = (pref_index - 1) << 2;
778 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
779 }
780return_pref:
781 mutex_unlock(&intel_pstate_limits_lock);
782
783 return ret;
784}
785
786static ssize_t show_energy_performance_available_preferences(
787 struct cpufreq_policy *policy, char *buf)
788{
789 int i = 0;
790 int ret = 0;
791
792 while (energy_perf_strings[i] != NULL)
793 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
794
795 ret += sprintf(&buf[ret], "\n");
796
797 return ret;
798}
799
800cpufreq_freq_attr_ro(energy_performance_available_preferences);
801
802static ssize_t store_energy_performance_preference(
803 struct cpufreq_policy *policy, const char *buf, size_t count)
804{
805 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
806 char str_preference[21];
807 int ret, i = 0;
808
809 ret = sscanf(buf, "%20s", str_preference);
810 if (ret != 1)
811 return -EINVAL;
812
813 while (energy_perf_strings[i] != NULL) {
814 if (!strcmp(str_preference, energy_perf_strings[i])) {
815 intel_pstate_set_energy_pref_index(cpu_data, i);
816 return count;
817 }
818 ++i;
819 }
820
821 return -EINVAL;
822}
823
824static ssize_t show_energy_performance_preference(
825 struct cpufreq_policy *policy, char *buf)
826{
827 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
828 int preference;
829
830 preference = intel_pstate_get_energy_pref_index(cpu_data);
831 if (preference < 0)
832 return preference;
833
834 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
835}
836
837cpufreq_freq_attr_rw(energy_performance_preference);
838
839static struct freq_attr *hwp_cpufreq_attrs[] = {
840 &energy_performance_preference,
841 &energy_performance_available_preferences,
842 NULL,
843};
844
111b8b3f 845static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
2f86dc4c 846{
74da56ce 847 int min, hw_min, max, hw_max, cpu, range, adj_range;
eae48f04 848 struct perf_limits *perf_limits = limits;
74da56ce
KCA		 849 u64 value, cap;
850
111b8b3f 851 for_each_cpu(cpu, policy->cpus) {
eae48f04 852 int max_perf_pct, min_perf_pct;
8442885f
SP		 853 struct cpudata *cpu_data = all_cpu_data[cpu];
854 s16 epp;
eae48f04
SP		 855
856 if (per_cpu_limits)
857 perf_limits = all_cpu_data[cpu]->perf_limits;
858
f9f4872d
SP		 859 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
860 hw_min = HWP_LOWEST_PERF(cap);
4e5d3f71
SP		 861 if (limits->no_turbo)
862 hw_max = HWP_GUARANTEED_PERF(cap);
863 else
864 hw_max = HWP_HIGHEST_PERF(cap);
f9f4872d
SP		 865 range = hw_max - hw_min;
866
eae48f04
SP		 867 max_perf_pct = perf_limits->max_perf_pct;
868 min_perf_pct = perf_limits->min_perf_pct;
869
2f86dc4c 870 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
eae48f04 871 adj_range = min_perf_pct * range / 100;
74da56ce 872 min = hw_min + adj_range;
2f86dc4c
DB		 873 value &= ~HWP_MIN_PERF(~0L);
874 value |= HWP_MIN_PERF(min);
875
eae48f04 876 adj_range = max_perf_pct * range / 100;
74da56ce 877 max = hw_min + adj_range;
2f86dc4c
DB		 878
879 value &= ~HWP_MAX_PERF(~0L);
880 value |= HWP_MAX_PERF(max);
8442885f
SP		 881
882 if (cpu_data->epp_policy == cpu_data->policy)
883 goto skip_epp;
884
885 cpu_data->epp_policy = cpu_data->policy;
886
984edbdc
SP		 887 if (cpu_data->epp_saved >= 0) {
888 epp = cpu_data->epp_saved;
889 cpu_data->epp_saved = -EINVAL;
890 goto update_epp;
891 }
892
8442885f
SP		 893 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
894 epp = intel_pstate_get_epp(cpu_data, value);
984edbdc 895 cpu_data->epp_powersave = epp;
8442885f 896 /* If EPP read was failed, then don't try to write */
984edbdc 897 if (epp < 0)
8442885f 898 goto skip_epp;
8442885f 899
8442885f
SP		 900
901 epp = 0;
902 } else {
903 /* skip setting EPP, when saved value is invalid */
984edbdc 904 if (cpu_data->epp_powersave < 0)
8442885f
SP		 905 goto skip_epp;
906
907 /*
908 * No need to restore EPP when it is not zero. This
909 * means:
910 * - Policy is not changed
911 * - user has manually changed
912 * - Error reading EPB
913 */
914 epp = intel_pstate_get_epp(cpu_data, value);
915 if (epp)
916 goto skip_epp;
917
984edbdc 918 epp = cpu_data->epp_powersave;
8442885f 919 }
984edbdc 920update_epp:
8442885f
SP		 921 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
922 value &= ~GENMASK_ULL(31, 24);
923 value |= (u64)epp << 24;
924 } else {
925 intel_pstate_set_epb(cpu, epp);
926 }
927skip_epp:
2f86dc4c
DB		 928 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
929 }
41cfd64c 930}
2f86dc4c 931
ba41e1bc
RW		 932static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
933{
934 if (hwp_active)
111b8b3f 935 intel_pstate_hwp_set(policy);
ba41e1bc
RW		 936
937 return 0;
938}
939
984edbdc
SP		 940static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
941{
942 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
943
944 if (!hwp_active)
945 return 0;
946
947 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
948
949 return 0;
950}
951
8442885f
SP		 952static int intel_pstate_resume(struct cpufreq_policy *policy)
953{
aa439248
RW		 954 int ret;
955
8442885f
SP		 956 if (!hwp_active)
957 return 0;
958
aa439248
RW		 959 mutex_lock(&intel_pstate_limits_lock);
960
8442885f 961 all_cpu_data[policy->cpu]->epp_policy = 0;
8442885f 962
aa439248
RW		 963 ret = intel_pstate_hwp_set_policy(policy);
964
965 mutex_unlock(&intel_pstate_limits_lock);
966
967 return ret;
8442885f
SP		 968}
969
111b8b3f 970static void intel_pstate_update_policies(void)
41cfd64c 971{
111b8b3f
RW		 972 int cpu;
973
974 for_each_possible_cpu(cpu)
975 cpufreq_update_policy(cpu);
2f86dc4c
DB		 976}
977
93f0822d
DB		 978/************************** debugfs begin ************************/
979static int pid_param_set(void *data, u64 val)
980{
981 *(u32 *)data = val;
982 intel_pstate_reset_all_pid();
983 return 0;
984}
845c1cbe 985
93f0822d
DB		 986static int pid_param_get(void *data, u64 *val)
987{
988 *val = *(u32 *)data;
989 return 0;
990}
2d8d1f18 991DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
93f0822d 992
fb1fe104
RW		 993static struct dentry *debugfs_parent;
994
93f0822d
DB		 995struct pid_param {
996 char *name;
997 void *value;
fb1fe104 998 struct dentry *dentry;
93f0822d
DB		 999};
1000
1001static struct pid_param pid_files[] = {
fb1fe104
RW		 1002 {"sample_rate_ms", &pid_params.sample_rate_ms, },
1003 {"d_gain_pct", &pid_params.d_gain_pct, },
1004 {"i_gain_pct", &pid_params.i_gain_pct, },
1005 {"deadband", &pid_params.deadband, },
1006 {"setpoint", &pid_params.setpoint, },
1007 {"p_gain_pct", &pid_params.p_gain_pct, },
1008 {NULL, NULL, }
93f0822d
DB		 1009};
1010
fb1fe104 1011static void intel_pstate_debug_expose_params(void)
93f0822d 1012{
fb1fe104 1013 int i;
93f0822d
DB		 1014
1015 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1016 if (IS_ERR_OR_NULL(debugfs_parent))
1017 return;
fb1fe104
RW		 1018
1019 for (i = 0; pid_files[i].name; i++) {
1020 struct dentry *dentry;
1021
1022 dentry = debugfs_create_file(pid_files[i].name, 0660,
1023 debugfs_parent, pid_files[i].value,
1024 &fops_pid_param);
1025 if (!IS_ERR(dentry))
1026 pid_files[i].dentry = dentry;
93f0822d
DB		 1027 }
1028}
1029
fb1fe104
RW		 1030static void intel_pstate_debug_hide_params(void)
1031{
1032 int i;
1033
1034 if (IS_ERR_OR_NULL(debugfs_parent))
1035 return;
1036
1037 for (i = 0; pid_files[i].name; i++) {
1038 debugfs_remove(pid_files[i].dentry);
1039 pid_files[i].dentry = NULL;
93f0822d 1040 }
fb1fe104
RW		 1041
1042 debugfs_remove(debugfs_parent);
1043 debugfs_parent = NULL;
93f0822d
DB		 1044}
1045
1046/************************** debugfs end ************************/
1047
1048/************************** sysfs begin ************************/
1049#define show_one(file_name, object) \
1050 static ssize_t show_##file_name \
1051 (struct kobject *kobj, struct attribute *attr, char *buf) \
1052 { \
51443fbf 1053 return sprintf(buf, "%u\n", limits->object); \
93f0822d
DB		 1054 }
1055
fb1fe104
RW		 1056static ssize_t intel_pstate_show_status(char *buf);
1057static int intel_pstate_update_status(const char *buf, size_t size);
1058
1059static ssize_t show_status(struct kobject *kobj,
1060 struct attribute *attr, char *buf)
1061{
1062 ssize_t ret;
1063
1064 mutex_lock(&intel_pstate_driver_lock);
1065 ret = intel_pstate_show_status(buf);
1066 mutex_unlock(&intel_pstate_driver_lock);
1067
1068 return ret;
1069}
1070
1071static ssize_t store_status(struct kobject *a, struct attribute *b,
1072 const char *buf, size_t count)
1073{
1074 char *p = memchr(buf, '\n', count);
1075 int ret;
1076
1077 mutex_lock(&intel_pstate_driver_lock);
1078 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1079 mutex_unlock(&intel_pstate_driver_lock);
1080
1081 return ret < 0 ? ret : count;
1082}
1083
d01b1f48
KCA		 1084static ssize_t show_turbo_pct(struct kobject *kobj,
1085 struct attribute *attr, char *buf)
1086{
1087 struct cpudata *cpu;
1088 int total, no_turbo, turbo_pct;
1089 uint32_t turbo_fp;
1090
0c30b65b
RW		 1091 mutex_lock(&intel_pstate_driver_lock);
1092
1093 if (!driver_registered) {
1094 mutex_unlock(&intel_pstate_driver_lock);
1095 return -EAGAIN;
1096 }
1097
d01b1f48
KCA		 1098 cpu = all_cpu_data[0];
1099
1100 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1101 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 1102 turbo_fp = div_fp(no_turbo, total);
d01b1f48 1103 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 1104
1105 mutex_unlock(&intel_pstate_driver_lock);
1106
d01b1f48
KCA		 1107 return sprintf(buf, "%u\n", turbo_pct);
1108}
1109
0522424e
KCA		 1110static ssize_t show_num_pstates(struct kobject *kobj,
1111 struct attribute *attr, char *buf)
1112{
1113 struct cpudata *cpu;
1114 int total;
1115
0c30b65b
RW		 1116 mutex_lock(&intel_pstate_driver_lock);
1117
1118 if (!driver_registered) {
1119 mutex_unlock(&intel_pstate_driver_lock);
1120 return -EAGAIN;
1121 }
1122
0522424e
KCA		 1123 cpu = all_cpu_data[0];
1124 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 1125
1126 mutex_unlock(&intel_pstate_driver_lock);
1127
0522424e
KCA		 1128 return sprintf(buf, "%u\n", total);
1129}
1130
4521e1a0
GM		 1131static ssize_t show_no_turbo(struct kobject *kobj,
1132 struct attribute *attr, char *buf)
1133{
1134 ssize_t ret;
1135
0c30b65b
RW		 1136 mutex_lock(&intel_pstate_driver_lock);
1137
1138 if (!driver_registered) {
1139 mutex_unlock(&intel_pstate_driver_lock);
1140 return -EAGAIN;
1141 }
1142
4521e1a0 1143 update_turbo_state();
51443fbf
PB		 1144 if (limits->turbo_disabled)
1145 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
4521e1a0 1146 else
51443fbf 1147 ret = sprintf(buf, "%u\n", limits->no_turbo);
4521e1a0 1148
0c30b65b
RW		 1149 mutex_unlock(&intel_pstate_driver_lock);
1150
4521e1a0
GM		 1151 return ret;
1152}
1153
93f0822d 1154static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 1155 const char *buf, size_t count)
93f0822d
DB		 1156{
1157 unsigned int input;
1158 int ret;
845c1cbe 1159
93f0822d
DB		 1160 ret = sscanf(buf, "%u", &input);
1161 if (ret != 1)
1162 return -EINVAL;
4521e1a0 1163
0c30b65b
RW		 1164 mutex_lock(&intel_pstate_driver_lock);
1165
1166 if (!driver_registered) {
1167 mutex_unlock(&intel_pstate_driver_lock);
1168 return -EAGAIN;
1169 }
1170
a410c03d
SP		 1171 mutex_lock(&intel_pstate_limits_lock);
1172
4521e1a0 1173 update_turbo_state();
51443fbf 1174 if (limits->turbo_disabled) {
4836df17 1175 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 1176 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 1177 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 1178 return -EPERM;
dd5fbf70 1179 }
2f86dc4c 1180
51443fbf 1181 limits->no_turbo = clamp_t(int, input, 0, 1);
4521e1a0 1182
b59fe540
SP		 1183 mutex_unlock(&intel_pstate_limits_lock);
1184
111b8b3f
RW		 1185 intel_pstate_update_policies();
1186
0c30b65b
RW		 1187 mutex_unlock(&intel_pstate_driver_lock);
1188
93f0822d
DB		 1189 return count;
1190}
1191
1192static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1193 const char *buf, size_t count)
93f0822d
DB		 1194{
1195 unsigned int input;
1196 int ret;
845c1cbe 1197
93f0822d
DB		 1198 ret = sscanf(buf, "%u", &input);
1199 if (ret != 1)
1200 return -EINVAL;
1201
0c30b65b
RW		 1202 mutex_lock(&intel_pstate_driver_lock);
1203
1204 if (!driver_registered) {
1205 mutex_unlock(&intel_pstate_driver_lock);
1206 return -EAGAIN;
1207 }
1208
a410c03d
SP		 1209 mutex_lock(&intel_pstate_limits_lock);
1210
51443fbf
PB		 1211 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1212 limits->max_perf_pct = min(limits->max_policy_pct,
1213 limits->max_sysfs_pct);
1214 limits->max_perf_pct = max(limits->min_policy_pct,
1215 limits->max_perf_pct);
1216 limits->max_perf_pct = max(limits->min_perf_pct,
1217 limits->max_perf_pct);
d5dd33d9 1218 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
845c1cbe 1219
b59fe540
SP		 1220 mutex_unlock(&intel_pstate_limits_lock);
1221
111b8b3f
RW		 1222 intel_pstate_update_policies();
1223
0c30b65b
RW		 1224 mutex_unlock(&intel_pstate_driver_lock);
1225
93f0822d
DB		 1226 return count;
1227}
1228
1229static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1230 const char *buf, size_t count)
93f0822d
DB		 1231{
1232 unsigned int input;
1233 int ret;
845c1cbe 1234
93f0822d
DB		 1235 ret = sscanf(buf, "%u", &input);
1236 if (ret != 1)
1237 return -EINVAL;
a0475992 1238
0c30b65b
RW		 1239 mutex_lock(&intel_pstate_driver_lock);
1240
1241 if (!driver_registered) {
1242 mutex_unlock(&intel_pstate_driver_lock);
1243 return -EAGAIN;
1244 }
1245
a410c03d
SP		 1246 mutex_lock(&intel_pstate_limits_lock);
1247
51443fbf
PB		 1248 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1249 limits->min_perf_pct = max(limits->min_policy_pct,
1250 limits->min_sysfs_pct);
1251 limits->min_perf_pct = min(limits->max_policy_pct,
1252 limits->min_perf_pct);
1253 limits->min_perf_pct = min(limits->max_perf_pct,
1254 limits->min_perf_pct);
d5dd33d9 1255 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
93f0822d 1256
b59fe540
SP		 1257 mutex_unlock(&intel_pstate_limits_lock);
1258
111b8b3f
RW		 1259 intel_pstate_update_policies();
1260
0c30b65b
RW		 1261 mutex_unlock(&intel_pstate_driver_lock);
1262
93f0822d
DB		 1263 return count;
1264}
1265
93f0822d
DB		 1266show_one(max_perf_pct, max_perf_pct);
1267show_one(min_perf_pct, min_perf_pct);
1268
fb1fe104 1269define_one_global_rw(status);
93f0822d
DB		 1270define_one_global_rw(no_turbo);
1271define_one_global_rw(max_perf_pct);
1272define_one_global_rw(min_perf_pct);
d01b1f48 1273define_one_global_ro(turbo_pct);
0522424e 1274define_one_global_ro(num_pstates);
93f0822d
DB		 1275
1276static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1277 &status.attr,
93f0822d 1278 &no_turbo.attr,
d01b1f48 1279 &turbo_pct.attr,
0522424e 1280 &num_pstates.attr,
93f0822d
DB		 1281 NULL
1282};
1283
1284static struct attribute_group intel_pstate_attr_group = {
1285 .attrs = intel_pstate_attributes,
1286};
93f0822d 1287
317dd50e 1288static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1289{
317dd50e 1290 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1291 int rc;
1292
1293 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1294 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1295 if (WARN_ON(!intel_pstate_kobject))
1296 return;
1297
2d8d1f18 1298 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1299 if (WARN_ON(rc))
1300 return;
1301
1302 /*
1303 * If per cpu limits are enforced there are no global limits, so
1304 * return without creating max/min_perf_pct attributes
1305 */
1306 if (per_cpu_limits)
1307 return;
1308
1309 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1310 WARN_ON(rc);
1311
1312 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1313 WARN_ON(rc);
1314
93f0822d 1315}
93f0822d 1316/************************** sysfs end ************************/
2f86dc4c 1317
ba88d433 1318static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1319{
f05c9665 1320 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1321 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1322 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1323
ba88d433 1324 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1325 cpudata->epp_policy = 0;
984edbdc
SP		 1326 if (cpudata->epp_default == -EINVAL)
1327 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1328}
1329
6e978b22
SP		 1330#define MSR_IA32_POWER_CTL_BIT_EE 19
1331
1332/* Disable energy efficiency optimization */
1333static void intel_pstate_disable_ee(int cpu)
1334{
1335 u64 power_ctl;
1336 int ret;
1337
1338 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1339 if (ret)
1340 return;
1341
1342 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1343 pr_info("Disabling energy efficiency optimization\n");
1344 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1345 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1346 }
1347}
1348
938d21a2 1349static int atom_get_min_pstate(void)
19e77c28
DB		 1350{
1351 u64 value;
845c1cbe 1352
92134bdb 1353 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1354 return (value >> 8) & 0x7F;
19e77c28
DB		 1355}
1356
938d21a2 1357static int atom_get_max_pstate(void)
19e77c28
DB		 1358{
1359 u64 value;
845c1cbe 1360
92134bdb 1361 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1362 return (value >> 16) & 0x7F;
19e77c28 1363}
93f0822d 1364
938d21a2 1365static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1366{
1367 u64 value;
845c1cbe 1368
92134bdb 1369 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1370 return value & 0x7F;
61d8d2ab
DB		 1371}
1372
fdfdb2b1 1373static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1374{
1375 u64 val;
1376 int32_t vid_fp;
1377 u32 vid;
1378
144c8e17 1379 val = (u64)pstate << 8;
51443fbf 1380 if (limits->no_turbo && !limits->turbo_disabled)
007bea09
DB		 1381 val |= (u64)1 << 32;
1382
1383 vid_fp = cpudata->vid.min + mul_fp(
1384 int_tofp(pstate - cpudata->pstate.min_pstate),
1385 cpudata->vid.ratio);
1386
1387 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1388 vid = ceiling_fp(vid_fp);
007bea09 1389
21855ff5
DB		 1390 if (pstate > cpudata->pstate.max_pstate)
1391 vid = cpudata->vid.turbo;
1392
fdfdb2b1 1393 return val | vid;
007bea09
DB		 1394}
1395
1421df63 1396static int silvermont_get_scaling(void)
b27580b0
DB		 1397{
1398 u64 value;
1399 int i;
1421df63
PL		 1400 /* Defined in Table 35-6 from SDM (Sept 2015) */
1401 static int silvermont_freq_table[] = {
1402 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1403
1404 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1405 i = value & 0x7;
1406 WARN_ON(i > 4);
b27580b0 1407
1421df63
PL		 1408 return silvermont_freq_table[i];
1409}
b27580b0 1410
1421df63
PL		 1411static int airmont_get_scaling(void)
1412{
1413 u64 value;
1414 int i;
1415 /* Defined in Table 35-10 from SDM (Sept 2015) */
1416 static int airmont_freq_table[] = {
1417 83300, 100000, 133300, 116700, 80000,
1418 93300, 90000, 88900, 87500};
1419
1420 rdmsrl(MSR_FSB_FREQ, value);
1421 i = value & 0xF;
1422 WARN_ON(i > 8);
1423
1424 return airmont_freq_table[i];
b27580b0
DB		 1425}
1426
938d21a2 1427static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1428{
1429 u64 value;
1430
92134bdb 1431 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1432 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1433 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1434 cpudata->vid.ratio = div_fp(
1435 cpudata->vid.max - cpudata->vid.min,
1436 int_tofp(cpudata->pstate.max_pstate -
1437 cpudata->pstate.min_pstate));
21855ff5 1438
92134bdb 1439 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1440 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1441}
1442
016c8150 1443static int core_get_min_pstate(void)
93f0822d
DB		 1444{
1445 u64 value;
845c1cbe 1446
05e99c8c 1447 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1448 return (value >> 40) & 0xFF;
1449}
1450
3bcc6fa9 1451static int core_get_max_pstate_physical(void)
93f0822d
DB		 1452{
1453 u64 value;
845c1cbe 1454
05e99c8c 1455 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1456 return (value >> 8) & 0xFF;
1457}
1458
8fc7554a
SP		 1459static int core_get_tdp_ratio(u64 plat_info)
1460{
1461 /* Check how many TDP levels present */
1462 if (plat_info & 0x600000000) {
1463 u64 tdp_ctrl;
1464 u64 tdp_ratio;
1465 int tdp_msr;
1466 int err;
1467
1468 /* Get the TDP level (0, 1, 2) to get ratios */
1469 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1470 if (err)
1471 return err;
1472
1473 /* TDP MSR are continuous starting at 0x648 */
1474 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1475 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1476 if (err)
1477 return err;
1478
1479 /* For level 1 and 2, bits[23:16] contain the ratio */
1480 if (tdp_ctrl & 0x03)
1481 tdp_ratio >>= 16;
1482
1483 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1484 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1485
1486 return (int)tdp_ratio;
1487 }
1488
1489 return -ENXIO;
1490}
1491
016c8150 1492static int core_get_max_pstate(void)
93f0822d 1493{
6a35fc2d
SP		 1494 u64 tar;
1495 u64 plat_info;
1496 int max_pstate;
8fc7554a 1497 int tdp_ratio;
6a35fc2d
SP		 1498 int err;
1499
1500 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1501 max_pstate = (plat_info >> 8) & 0xFF;
1502
8fc7554a
SP		 1503 tdp_ratio = core_get_tdp_ratio(plat_info);
1504 if (tdp_ratio <= 0)
1505 return max_pstate;
1506
1507 if (hwp_active) {
1508 /* Turbo activation ratio is not used on HWP platforms */
1509 return tdp_ratio;
1510 }
1511
6a35fc2d
SP		 1512 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1513 if (!err) {
8fc7554a
SP		 1514 int tar_levels;
1515
6a35fc2d 1516 /* Do some sanity checking for safety */
8fc7554a
SP		 1517 tar_levels = tar & 0xff;
1518 if (tdp_ratio - 1 == tar_levels) {
1519 max_pstate = tar_levels;
1520 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1521 }
1522 }
845c1cbe 1523
6a35fc2d 1524 return max_pstate;
93f0822d
DB		 1525}
1526
016c8150 1527static int core_get_turbo_pstate(void)
93f0822d
DB		 1528{
1529 u64 value;
1530 int nont, ret;
845c1cbe 1531
100cf6f2 1532 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1533 nont = core_get_max_pstate();
285cb990 1534 ret = (value) & 255;
93f0822d
DB		 1535 if (ret <= nont)
1536 ret = nont;
1537 return ret;
1538}
1539
b27580b0
DB		 1540static inline int core_get_scaling(void)
1541{
1542 return 100000;
1543}
1544
fdfdb2b1 1545static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1546{
1547 u64 val;
1548
144c8e17 1549 val = (u64)pstate << 8;
51443fbf 1550 if (limits->no_turbo && !limits->turbo_disabled)
016c8150
DB		 1551 val |= (u64)1 << 32;
1552
fdfdb2b1 1553 return val;
016c8150
DB		 1554}
1555
b34ef932
DC		 1556static int knl_get_turbo_pstate(void)
1557{
1558 u64 value;
1559 int nont, ret;
1560
100cf6f2 1561 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1562 nont = core_get_max_pstate();
1563 ret = (((value) >> 8) & 0xFF);
1564 if (ret <= nont)
1565 ret = nont;
1566 return ret;
1567}
1568
016c8150
DB		 1569static struct cpu_defaults core_params = {
1570 .pid_policy = {
1571 .sample_rate_ms = 10,
1572 .deadband = 0,
1573 .setpoint = 97,
1574 .p_gain_pct = 20,
1575 .d_gain_pct = 0,
1576 .i_gain_pct = 0,
1577 },
1578 .funcs = {
1579 .get_max = core_get_max_pstate,
3bcc6fa9 1580 .get_max_physical = core_get_max_pstate_physical,
016c8150
DB		 1581 .get_min = core_get_min_pstate,
1582 .get_turbo = core_get_turbo_pstate,
b27580b0 1583 .get_scaling = core_get_scaling,
fdfdb2b1 1584 .get_val = core_get_val,
157386b6 1585 .get_target_pstate = get_target_pstate_use_performance,
016c8150
DB		 1586 },
1587};
1588
42ce8921 1589static const struct cpu_defaults silvermont_params = {
1421df63
PL		 1590 .pid_policy = {
1591 .sample_rate_ms = 10,
1592 .deadband = 0,
1593 .setpoint = 60,
1594 .p_gain_pct = 14,
1595 .d_gain_pct = 0,
1596 .i_gain_pct = 4,
1597 },
1598 .funcs = {
1599 .get_max = atom_get_max_pstate,
1600 .get_max_physical = atom_get_max_pstate,
1601 .get_min = atom_get_min_pstate,
1602 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1603 .get_val = atom_get_val,
1421df63
PL		 1604 .get_scaling = silvermont_get_scaling,
1605 .get_vid = atom_get_vid,
e70eed2b 1606 .get_target_pstate = get_target_pstate_use_cpu_load,
1421df63
PL		 1607 },
1608};
1609
42ce8921 1610static const struct cpu_defaults airmont_params = {
19e77c28
DB		 1611 .pid_policy = {
1612 .sample_rate_ms = 10,
1613 .deadband = 0,
6a82ba6d 1614 .setpoint = 60,
19e77c28
DB		 1615 .p_gain_pct = 14,
1616 .d_gain_pct = 0,
1617 .i_gain_pct = 4,
1618 },
1619 .funcs = {
938d21a2
PL		 1620 .get_max = atom_get_max_pstate,
1621 .get_max_physical = atom_get_max_pstate,
1622 .get_min = atom_get_min_pstate,
1623 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1624 .get_val = atom_get_val,
1421df63 1625 .get_scaling = airmont_get_scaling,
938d21a2 1626 .get_vid = atom_get_vid,
e70eed2b 1627 .get_target_pstate = get_target_pstate_use_cpu_load,
19e77c28
DB		 1628 },
1629};
1630
42ce8921 1631static const struct cpu_defaults knl_params = {
b34ef932
DC		 1632 .pid_policy = {
1633 .sample_rate_ms = 10,
1634 .deadband = 0,
1635 .setpoint = 97,
1636 .p_gain_pct = 20,
1637 .d_gain_pct = 0,
1638 .i_gain_pct = 0,
1639 },
1640 .funcs = {
1641 .get_max = core_get_max_pstate,
3bcc6fa9 1642 .get_max_physical = core_get_max_pstate_physical,
b34ef932
DC		 1643 .get_min = core_get_min_pstate,
1644 .get_turbo = knl_get_turbo_pstate,
69cefc27 1645 .get_scaling = core_get_scaling,
fdfdb2b1 1646 .get_val = core_get_val,
157386b6 1647 .get_target_pstate = get_target_pstate_use_performance,
b34ef932
DC		 1648 },
1649};
1650
42ce8921 1651static const struct cpu_defaults bxt_params = {
41bad47f
SP		 1652 .pid_policy = {
1653 .sample_rate_ms = 10,
1654 .deadband = 0,
1655 .setpoint = 60,
1656 .p_gain_pct = 14,
1657 .d_gain_pct = 0,
1658 .i_gain_pct = 4,
1659 },
1660 .funcs = {
1661 .get_max = core_get_max_pstate,
1662 .get_max_physical = core_get_max_pstate_physical,
1663 .get_min = core_get_min_pstate,
1664 .get_turbo = core_get_turbo_pstate,
1665 .get_scaling = core_get_scaling,
1666 .get_val = core_get_val,
1667 .get_target_pstate = get_target_pstate_use_cpu_load,
1668 },
1669};
1670
93f0822d
DB		 1671static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1672{
1673 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 1674 int max_perf_adj;
93f0822d 1675 int min_perf;
eae48f04 1676 struct perf_limits *perf_limits = limits;
845c1cbe 1677
51443fbf 1678 if (limits->no_turbo || limits->turbo_disabled)
93f0822d
DB		 1679 max_perf = cpu->pstate.max_pstate;
1680
eae48f04
SP		 1681 if (per_cpu_limits)
1682 perf_limits = cpu->perf_limits;
1683
e0d4c8f8
KCA		 1684 /*
1685 * performance can be limited by user through sysfs, by cpufreq
1686 * policy, or by cpu specific default values determined through
1687 * experimentation.
1688 */
d5dd33d9 1689 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
799281a3
RW		 1690 *max = clamp_t(int, max_perf_adj,
1691 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
93f0822d 1692
d5dd33d9 1693 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
799281a3 1694 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
93f0822d
DB		 1695}
1696
a6c6ead1 1697static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1698{
bc95a454
RW		 1699 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1700 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1701 /*
1702 * Generally, there is no guarantee that this code will always run on
1703 * the CPU being updated, so force the register update to run on the
1704 * right CPU.
1705 */
1706 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1707 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1708}
1709
a6c6ead1
RW		 1710static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1711{
1712 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1713}
1714
1715static void intel_pstate_max_within_limits(struct cpudata *cpu)
1716{
1717 int min_pstate, max_pstate;
1718
1719 update_turbo_state();
1720 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1721 intel_pstate_set_pstate(cpu, max_pstate);
1722}
1723
93f0822d
DB		 1724static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1725{
016c8150
DB		 1726 cpu->pstate.min_pstate = pstate_funcs.get_min();
1727 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1728 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1729 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1730 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0
RW		 1731 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1732 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d 1733
007bea09
DB		 1734 if (pstate_funcs.get_vid)
1735 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1736
1737 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1738}
1739
a1c9787d 1740static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1741{
6b17ddb2 1742 struct sample *sample = &cpu->sample;
e66c1768 1743
a1c9787d 1744 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1745}
1746
4fec7ad5 1747static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1748{
93f0822d 1749 u64 aperf, mperf;
4ab60c3f 1750 unsigned long flags;
4055fad3 1751 u64 tsc;
93f0822d 1752
4ab60c3f 1753 local_irq_save(flags);
93f0822d
DB		 1754 rdmsrl(MSR_IA32_APERF, aperf);
1755 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1756 tsc = rdtsc();
4fec7ad5 1757 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1758 local_irq_restore(flags);
4fec7ad5 1759 return false;
8e601a9f 1760 }
4ab60c3f 1761 local_irq_restore(flags);
b69880f9 1762
c4ee841f 1763 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1764 cpu->sample.time = time;
d37e2b76
DB		 1765 cpu->sample.aperf = aperf;
1766 cpu->sample.mperf = mperf;
4055fad3 1767 cpu->sample.tsc = tsc;
d37e2b76
DB		 1768 cpu->sample.aperf -= cpu->prev_aperf;
1769 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1770 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1771
93f0822d
DB		 1772 cpu->prev_aperf = aperf;
1773 cpu->prev_mperf = mperf;
4055fad3 1774 cpu->prev_tsc = tsc;
febce40f
RW		 1775 /*
1776 * First time this function is invoked in a given cycle, all of the
1777 * previous sample data fields are equal to zero or stale and they must
1778 * be populated with meaningful numbers for things to work, so assume
1779 * that sample.time will always be reset before setting the utilization
1780 * update hook and make the caller skip the sample then.
1781 */
1782 return !!cpu->last_sample_time;
93f0822d
DB		 1783}
1784
8fa520af
PL		 1785static inline int32_t get_avg_frequency(struct cpudata *cpu)
1786{
a1c9787d
RW		 1787 return mul_ext_fp(cpu->sample.core_avg_perf,
1788 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
8fa520af
PL		 1789}
1790
bdcaa23f
PL		 1791static inline int32_t get_avg_pstate(struct cpudata *cpu)
1792{
8edb0a6e
RW		 1793 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1794 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1795}
1796
e70eed2b
PL		 1797static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1798{
1799 struct sample *sample = &cpu->sample;
09c448d3 1800 int32_t busy_frac, boost;
0843e83c 1801 int target, avg_pstate;
e70eed2b 1802
09c448d3 1803 busy_frac = div_fp(sample->mperf, sample->tsc);
63d1d656 1804
09c448d3
RW		 1805 boost = cpu->iowait_boost;
1806 cpu->iowait_boost >>= 1;
63d1d656 1807
09c448d3
RW		 1808 if (busy_frac < boost)
1809 busy_frac = boost;
63d1d656 1810
09c448d3 1811 sample->busy_scaled = busy_frac * 100;
0843e83c
RW		 1812
1813 target = limits->no_turbo || limits->turbo_disabled ?
1814 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1815 target += target >> 2;
1816 target = mul_fp(target, busy_frac);
1817 if (target < cpu->pstate.min_pstate)
1818 target = cpu->pstate.min_pstate;
1819
1820 /*
1821 * If the average P-state during the previous cycle was higher than the
1822 * current target, add 50% of the difference to the target to reduce
1823 * possible performance oscillations and offset possible performance
1824 * loss related to moving the workload from one CPU to another within
1825 * a package/module.
1826 */
1827 avg_pstate = get_avg_pstate(cpu);
1828 if (avg_pstate > target)
1829 target += (avg_pstate - target) >> 1;
1830
1831 return target;
e70eed2b
PL		 1832}
1833
157386b6 1834static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
93f0822d 1835{
1aa7a6e2 1836 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
a4675fbc 1837 u64 duration_ns;
93f0822d 1838
e0d4c8f8 1839 /*
f00593a4
RW		 1840 * perf_scaled is the ratio of the average P-state during the last
1841 * sampling period to the P-state requested last time (in percent).
1842 *
1843 * That measures the system's response to the previous P-state
1844 * selection.
e0d4c8f8 1845 */
22590efb
RW		 1846 max_pstate = cpu->pstate.max_pstate_physical;
1847 current_pstate = cpu->pstate.current_pstate;
1aa7a6e2 1848 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
a1c9787d 1849 div_fp(100 * max_pstate, current_pstate));
c4ee841f 1850
e0d4c8f8 1851 /*
a4675fbc
RW		 1852 * Since our utilization update callback will not run unless we are
1853 * in C0, check if the actual elapsed time is significantly greater (3x)
1854 * than our sample interval. If it is, then we were idle for a long
1aa7a6e2 1855 * enough period of time to adjust our performance metric.
e0d4c8f8 1856 */
a4675fbc 1857 duration_ns = cpu->sample.time - cpu->last_sample_time;
febce40f 1858 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
22590efb 1859 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1aa7a6e2 1860 perf_scaled = mul_fp(perf_scaled, sample_ratio);
ffb81056
RW		 1861 } else {
1862 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1863 if (sample_ratio < int_tofp(1))
1aa7a6e2 1864 perf_scaled = 0;
c4ee841f
DB		 1865 }
1866
1aa7a6e2
RW		 1867 cpu->sample.busy_scaled = perf_scaled;
1868 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
93f0822d
DB		 1869}
1870
001c76f0 1871static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1
RW		 1872{
1873 int max_perf, min_perf;
1874
fdfdb2b1
RW		 1875 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1876 pstate = clamp_t(int, pstate, min_perf, max_perf);
bc95a454 1877 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
001c76f0
RW		 1878 return pstate;
1879}
1880
1881static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1882{
1883 pstate = intel_pstate_prepare_request(cpu, pstate);
fdfdb2b1
RW		 1884 if (pstate == cpu->pstate.current_pstate)
1885 return;
1886
bc95a454 1887 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1888 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1889}
1890
93f0822d
DB		 1891static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1892{
157386b6 1893 int from, target_pstate;
4055fad3
DS		 1894 struct sample *sample;
1895
1896 from = cpu->pstate.current_pstate;
93f0822d 1897
2f1d407a
RW		 1898 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1899 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
93f0822d 1900
001c76f0
RW		 1901 update_turbo_state();
1902
fdfdb2b1 1903 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1904
1905 sample = &cpu->sample;
a1c9787d 1906 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1907 fp_toint(sample->busy_scaled),
4055fad3
DS		 1908 from,
1909 cpu->pstate.current_pstate,
1910 sample->mperf,
1911 sample->aperf,
1912 sample->tsc,
3ba7bcaa
SP		 1913 get_avg_frequency(cpu),
1914 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1915}
1916
a4675fbc 1917static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1918 unsigned int flags)
93f0822d 1919{
a4675fbc 1920 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1921 u64 delta_ns;
1922
1d29815e 1923 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
09c448d3
RW		 1924 if (flags & SCHED_CPUFREQ_IOWAIT) {
1925 cpu->iowait_boost = int_tofp(1);
1926 } else if (cpu->iowait_boost) {
1927 /* Clear iowait_boost if the CPU may have been idle. */
1928 delta_ns = time - cpu->last_update;
1929 if (delta_ns > TICK_NSEC)
1930 cpu->iowait_boost = 0;
1931 }
1932 cpu->last_update = time;
1933 }
b69880f9 1934
09c448d3 1935 delta_ns = time - cpu->sample.time;
a4675fbc 1936 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
4fec7ad5
RW		 1937 bool sample_taken = intel_pstate_sample(cpu, time);
1938
6d45b719 1939 if (sample_taken) {
a1c9787d 1940 intel_pstate_calc_avg_perf(cpu);
6d45b719
RW		 1941 if (!hwp_active)
1942 intel_pstate_adjust_busy_pstate(cpu);
1943 }
a4675fbc 1944 }
93f0822d
DB		 1945}
1946
1947#define ICPU(model, policy) \
6cbd7ee1
DB		 1948 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1949 (unsigned long)&policy }
93f0822d
DB		 1950
1951static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
5b20c944
DH		 1952 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1953 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1954 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1955 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1956 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1957 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1958 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1959 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1960 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1961 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1962 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1963 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1964 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1965 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1966 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1967 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1968 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
58bf4542 1969 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
41bad47f 1970 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
93f0822d
DB		 1971 {}
1972};
1973MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1974
29327c84 1975static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
5b20c944 1976 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
65c1262f
SP		 1977 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1978 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
2f86dc4c
DB		 1979 {}
1980};
1981
6e978b22
SP		 1982static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1983 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1984 {}
1985};
1986
93f0822d
DB		 1987static int intel_pstate_init_cpu(unsigned int cpunum)
1988{
93f0822d
DB		 1989 struct cpudata *cpu;
1990
eae48f04
SP		 1991 cpu = all_cpu_data[cpunum];
1992
1993 if (!cpu) {
1994 unsigned int size = sizeof(struct cpudata);
1995
1996 if (per_cpu_limits)
1997 size += sizeof(struct perf_limits);
1998
1999 cpu = kzalloc(size, GFP_KERNEL);
2000 if (!cpu)
2001 return -ENOMEM;
2002
2003 all_cpu_data[cpunum] = cpu;
2004 if (per_cpu_limits)
2005 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2006
984edbdc
SP		 2007 cpu->epp_default = -EINVAL;
2008 cpu->epp_powersave = -EINVAL;
2009 cpu->epp_saved = -EINVAL;
eae48f04 2010 }
93f0822d
DB		 2011
2012 cpu = all_cpu_data[cpunum];
2013
93f0822d 2014 cpu->cpu = cpunum;
ba88d433 2015
a4675fbc 2016 if (hwp_active) {
6e978b22
SP		 2017 const struct x86_cpu_id *id;
2018
2019 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2020 if (id)
2021 intel_pstate_disable_ee(cpunum);
2022
ba88d433 2023 intel_pstate_hwp_enable(cpu);
a4675fbc
RW		 2024 pid_params.sample_rate_ms = 50;
2025 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2026 }
ba88d433 2027
179e8471 2028 intel_pstate_get_cpu_pstates(cpu);
016c8150 2029
93f0822d 2030 intel_pstate_busy_pid_reset(cpu);
93f0822d 2031
4836df17 2032 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 2033
2034 return 0;
2035}
2036
2037static unsigned int intel_pstate_get(unsigned int cpu_num)
2038{
f96fd0c8 2039 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 2040
f96fd0c8 2041 return cpu ? get_avg_frequency(cpu) : 0;
93f0822d
DB		 2042}
2043
febce40f 2044static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 2045{
febce40f
RW		 2046 struct cpudata *cpu = all_cpu_data[cpu_num];
2047
5ab666e0
RW		 2048 if (cpu->update_util_set)
2049 return;
2050
febce40f
RW		 2051 /* Prevent intel_pstate_update_util() from using stale data. */
2052 cpu->sample.time = 0;
0bed612b
RW		 2053 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2054 intel_pstate_update_util);
4578ee7e 2055 cpu->update_util_set = true;
bb6ab52f
RW		 2056}
2057
2058static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2059{
4578ee7e
CY		 2060 struct cpudata *cpu_data = all_cpu_data[cpu];
2061
2062 if (!cpu_data->update_util_set)
2063 return;
2064
0bed612b 2065 cpufreq_remove_update_util_hook(cpu);
4578ee7e 2066 cpu_data->update_util_set = false;
bb6ab52f
RW		 2067 synchronize_sched();
2068}
2069
eae48f04
SP		 2070static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2071 struct perf_limits *limits)
2072{
a410c03d 2073
eae48f04
SP		 2074 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2075 policy->cpuinfo.max_freq);
2076 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
5879f877
SP		 2077 if (policy->max == policy->min) {
2078 limits->min_policy_pct = limits->max_policy_pct;
2079 } else {
46992d6b
SP		 2080 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2081 policy->cpuinfo.max_freq);
5879f877
SP		 2082 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2083 0, 100);
2084 }
eae48f04
SP		 2085
2086 /* Normalize user input to [min_policy_pct, max_policy_pct] */
2087 limits->min_perf_pct = max(limits->min_policy_pct,
2088 limits->min_sysfs_pct);
2089 limits->min_perf_pct = min(limits->max_policy_pct,
2090 limits->min_perf_pct);
2091 limits->max_perf_pct = min(limits->max_policy_pct,
2092 limits->max_sysfs_pct);
2093 limits->max_perf_pct = max(limits->min_policy_pct,
2094 limits->max_perf_pct);
2095
2096 /* Make sure min_perf_pct <= max_perf_pct */
2097 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2098
d5dd33d9
SP		 2099 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2100 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2101 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2102 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
eae48f04
SP		 2103
2104 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2105 limits->max_perf_pct, limits->min_perf_pct);
2106}
2107
93f0822d
DB		 2108static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2109{
3be9200d 2110 struct cpudata *cpu;
eae48f04 2111 struct perf_limits *perf_limits = NULL;
3be9200d 2112
d3929b83
DB		 2113 if (!policy->cpuinfo.max_freq)
2114 return -ENODEV;
2115
2c2c1af4
SP		 2116 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2117 policy->cpuinfo.max_freq, policy->max);
2118
a6c6ead1 2119 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 2120 cpu->policy = policy->policy;
2121
c749c64f
RW		 2122 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2123 policy->max < policy->cpuinfo.max_freq &&
2124 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2125 pr_debug("policy->max > max non turbo frequency\n");
2126 policy->max = policy->cpuinfo.max_freq;
3be9200d
SP		 2127 }
2128
eae48f04
SP		 2129 if (per_cpu_limits)
2130 perf_limits = cpu->perf_limits;
2131
b59fe540
SP		 2132 mutex_lock(&intel_pstate_limits_lock);
2133
eae48f04
SP		 2134 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2135 if (!perf_limits) {
2136 limits = &performance_limits;
2137 perf_limits = limits;
2138 }
1443ebba
SP		 2139 if (policy->max >= policy->cpuinfo.max_freq &&
2140 !limits->no_turbo) {
4836df17 2141 pr_debug("set performance\n");
eae48f04 2142 intel_pstate_set_performance_limits(perf_limits);
30a39153
SP		 2143 goto out;
2144 }
2145 } else {
4836df17 2146 pr_debug("set powersave\n");
eae48f04
SP		 2147 if (!perf_limits) {
2148 limits = &powersave_limits;
2149 perf_limits = limits;
2150 }
43717aad 2151
eae48f04 2152 }
93f0822d 2153
eae48f04 2154 intel_pstate_update_perf_limits(policy, perf_limits);
bb6ab52f 2155 out:
2f1d407a 2156 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 2157 /*
2158 * NOHZ_FULL CPUs need this as the governor callback may not
2159 * be invoked on them.
2160 */
2161 intel_pstate_clear_update_util_hook(policy->cpu);
2162 intel_pstate_max_within_limits(cpu);
2163 }
2164
bb6ab52f
RW		 2165 intel_pstate_set_update_util_hook(policy->cpu);
2166
ba41e1bc 2167 intel_pstate_hwp_set_policy(policy);
2f86dc4c 2168
b59fe540
SP		 2169 mutex_unlock(&intel_pstate_limits_lock);
2170
93f0822d
DB		 2171 return 0;
2172}
2173
2174static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2175{
7d9a8a9f
SP		 2176 struct cpudata *cpu = all_cpu_data[policy->cpu];
2177 struct perf_limits *perf_limits;
2178
2179 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2180 perf_limits = &performance_limits;
2181 else
2182 perf_limits = &powersave_limits;
2183
2184 update_turbo_state();
2185 policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2186 perf_limits->no_turbo ?
2187 cpu->pstate.max_freq :
2188 cpu->pstate.turbo_freq;
2189
be49e346 2190 cpufreq_verify_within_cpu_limits(policy);
93f0822d 2191
285cb990 2192 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 2193 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 2194 return -EINVAL;
2195
1443ebba
SP		 2196 /* When per-CPU limits are used, sysfs limits are not used */
2197 if (!per_cpu_limits) {
2198 unsigned int max_freq, min_freq;
2199
2200 max_freq = policy->cpuinfo.max_freq *
2201 limits->max_sysfs_pct / 100;
2202 min_freq = policy->cpuinfo.max_freq *
2203 limits->min_sysfs_pct / 100;
2204 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2205 }
2206
93f0822d
DB		 2207 return 0;
2208}
2209
001c76f0
RW		 2210static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2211{
2212 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2213}
2214
bb18008f 2215static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 2216{
001c76f0 2217 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 2218
001c76f0 2219 intel_pstate_clear_update_util_hook(policy->cpu);
984edbdc
SP		 2220 if (hwp_active)
2221 intel_pstate_hwp_save_state(policy);
2222 else
001c76f0
RW		 2223 intel_cpufreq_stop_cpu(policy);
2224}
bb18008f 2225
001c76f0
RW		 2226static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2227{
2228 intel_pstate_exit_perf_limits(policy);
a4675fbc 2229
001c76f0 2230 policy->fast_switch_possible = false;
2f86dc4c 2231
001c76f0 2232 return 0;
93f0822d
DB		 2233}
2234
001c76f0 2235static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2236{
93f0822d 2237 struct cpudata *cpu;
52e0a509 2238 int rc;
93f0822d
DB		 2239
2240 rc = intel_pstate_init_cpu(policy->cpu);
2241 if (rc)
2242 return rc;
2243
2244 cpu = all_cpu_data[policy->cpu];
2245
eae48f04
SP		 2246 /*
2247 * We need sane value in the cpu->perf_limits, so inherit from global
2248 * perf_limits limits, which are seeded with values based on the
2249 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2250 */
2251 if (per_cpu_limits)
2252 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
93f0822d 2253
b27580b0
DB		 2254 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2255 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 2256
2257 /* cpuinfo and default policy values */
b27580b0 2258 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e
SP		 2259 update_turbo_state();
2260 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2261 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2262 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2263
9522a2ff 2264 intel_pstate_init_acpi_perf_limits(policy);
93f0822d
DB		 2265 cpumask_set_cpu(policy->cpu, policy->cpus);
2266
001c76f0
RW		 2267 policy->fast_switch_possible = true;
2268
93f0822d
DB		 2269 return 0;
2270}
2271
001c76f0 2272static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2273{
001c76f0
RW		 2274 int ret = __intel_pstate_cpu_init(policy);
2275
2276 if (ret)
2277 return ret;
2278
2279 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2280 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2281 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2282 else
2283 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 2284
2285 return 0;
2286}
2287
001c76f0 2288static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2289 .flags = CPUFREQ_CONST_LOOPS,
2290 .verify = intel_pstate_verify_policy,
2291 .setpolicy = intel_pstate_set_policy,
984edbdc 2292 .suspend = intel_pstate_hwp_save_state,
8442885f 2293 .resume = intel_pstate_resume,
93f0822d
DB		 2294 .get = intel_pstate_get,
2295 .init = intel_pstate_cpu_init,
9522a2ff 2296 .exit = intel_pstate_cpu_exit,
bb18008f 2297 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 2298 .name = "intel_pstate",
93f0822d
DB		 2299};
2300
001c76f0
RW		 2301static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2302{
2303 struct cpudata *cpu = all_cpu_data[policy->cpu];
2304 struct perf_limits *perf_limits = limits;
2305
2306 update_turbo_state();
2307 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2308 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2309
2310 cpufreq_verify_within_cpu_limits(policy);
2311
2312 if (per_cpu_limits)
2313 perf_limits = cpu->perf_limits;
2314
cad30467
RW		 2315 mutex_lock(&intel_pstate_limits_lock);
2316
001c76f0
RW		 2317 intel_pstate_update_perf_limits(policy, perf_limits);
2318
cad30467
RW		 2319 mutex_unlock(&intel_pstate_limits_lock);
2320
001c76f0
RW		 2321 return 0;
2322}
2323
2324static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2325 struct cpufreq_policy *policy,
2326 unsigned int target_freq)
2327{
2328 unsigned int max_freq;
2329
2330 update_turbo_state();
2331
2332 max_freq = limits->no_turbo || limits->turbo_disabled ?
2333 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2334 policy->cpuinfo.max_freq = max_freq;
2335 if (policy->max > max_freq)
2336 policy->max = max_freq;
2337
2338 if (target_freq > max_freq)
2339 target_freq = max_freq;
2340
2341 return target_freq;
2342}
2343
2344static int intel_cpufreq_target(struct cpufreq_policy *policy,
2345 unsigned int target_freq,
2346 unsigned int relation)
2347{
2348 struct cpudata *cpu = all_cpu_data[policy->cpu];
2349 struct cpufreq_freqs freqs;
2350 int target_pstate;
2351
2352 freqs.old = policy->cur;
2353 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2354
2355 cpufreq_freq_transition_begin(policy, &freqs);
2356 switch (relation) {
2357 case CPUFREQ_RELATION_L:
2358 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2359 break;
2360 case CPUFREQ_RELATION_H:
2361 target_pstate = freqs.new / cpu->pstate.scaling;
2362 break;
2363 default:
2364 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2365 break;
2366 }
2367 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2368 if (target_pstate != cpu->pstate.current_pstate) {
2369 cpu->pstate.current_pstate = target_pstate;
2370 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2371 pstate_funcs.get_val(cpu, target_pstate));
2372 }
2373 cpufreq_freq_transition_end(policy, &freqs, false);
2374
2375 return 0;
2376}
2377
2378static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2379 unsigned int target_freq)
2380{
2381 struct cpudata *cpu = all_cpu_data[policy->cpu];
2382 int target_pstate;
2383
2384 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2385 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2386 intel_pstate_update_pstate(cpu, target_pstate);
2387 return target_freq;
2388}
2389
2390static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2391{
2392 int ret = __intel_pstate_cpu_init(policy);
2393
2394 if (ret)
2395 return ret;
2396
2397 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2398 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2399 policy->cur = policy->cpuinfo.min_freq;
2400
2401 return 0;
2402}
2403
2404static struct cpufreq_driver intel_cpufreq = {
2405 .flags = CPUFREQ_CONST_LOOPS,
2406 .verify = intel_cpufreq_verify_policy,
2407 .target = intel_cpufreq_target,
2408 .fast_switch = intel_cpufreq_fast_switch,
2409 .init = intel_cpufreq_cpu_init,
2410 .exit = intel_pstate_cpu_exit,
2411 .stop_cpu = intel_cpufreq_stop_cpu,
2412 .name = "intel_cpufreq",
2413};
2414
2415static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2416
fb1fe104
RW		 2417static void intel_pstate_driver_cleanup(void)
2418{
2419 unsigned int cpu;
2420
2421 get_online_cpus();
2422 for_each_online_cpu(cpu) {
2423 if (all_cpu_data[cpu]) {
2424 if (intel_pstate_driver == &intel_pstate)
2425 intel_pstate_clear_update_util_hook(cpu);
2426
2427 kfree(all_cpu_data[cpu]);
2428 all_cpu_data[cpu] = NULL;
2429 }
2430 }
2431 put_online_cpus();
2432}
2433
2434static int intel_pstate_register_driver(void)
2435{
2436 int ret;
2437
c3a49c89
RW		 2438 intel_pstate_init_limits(&powersave_limits);
2439 intel_pstate_set_performance_limits(&performance_limits);
2440 limits = IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) ?
2441 &performance_limits : &powersave_limits;
2442
fb1fe104
RW		 2443 ret = cpufreq_register_driver(intel_pstate_driver);
2444 if (ret) {
2445 intel_pstate_driver_cleanup();
2446 return ret;
2447 }
2448
2449 mutex_lock(&intel_pstate_limits_lock);
2450 driver_registered = true;
2451 mutex_unlock(&intel_pstate_limits_lock);
2452
2453 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2454 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2455 intel_pstate_debug_expose_params();
2456
2457 return 0;
2458}
2459
2460static int intel_pstate_unregister_driver(void)
2461{
2462 if (hwp_active)
2463 return -EBUSY;
2464
2465 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2466 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2467 intel_pstate_debug_hide_params();
2468
2469 mutex_lock(&intel_pstate_limits_lock);
2470 driver_registered = false;
2471 mutex_unlock(&intel_pstate_limits_lock);
2472
2473 cpufreq_unregister_driver(intel_pstate_driver);
2474 intel_pstate_driver_cleanup();
2475
2476 return 0;
2477}
2478
2479static ssize_t intel_pstate_show_status(char *buf)
2480{
2481 if (!driver_registered)
2482 return sprintf(buf, "off\n");
2483
2484 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2485 "active" : "passive");
2486}
2487
2488static int intel_pstate_update_status(const char *buf, size_t size)
2489{
2490 int ret;
2491
2492 if (size == 3 && !strncmp(buf, "off", size))
2493 return driver_registered ?
2494 intel_pstate_unregister_driver() : -EINVAL;
2495
2496 if (size == 6 && !strncmp(buf, "active", size)) {
2497 if (driver_registered) {
2498 if (intel_pstate_driver == &intel_pstate)
2499 return 0;
2500
2501 ret = intel_pstate_unregister_driver();
2502 if (ret)
2503 return ret;
2504 }
2505
2506 intel_pstate_driver = &intel_pstate;
2507 return intel_pstate_register_driver();
2508 }
2509
2510 if (size == 7 && !strncmp(buf, "passive", size)) {
2511 if (driver_registered) {
2512 if (intel_pstate_driver != &intel_pstate)
2513 return 0;
2514
2515 ret = intel_pstate_unregister_driver();
2516 if (ret)
2517 return ret;
2518 }
2519
2520 intel_pstate_driver = &intel_cpufreq;
2521 return intel_pstate_register_driver();
2522 }
2523
2524 return -EINVAL;
2525}
2526
eed43609
JZ		 2527static int no_load __initdata;
2528static int no_hwp __initdata;
2529static int hwp_only __initdata;
29327c84 2530static unsigned int force_load __initdata;
6be26498 2531
29327c84 2532static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2533{
016c8150 2534 if (!pstate_funcs.get_max() ||
c410833a
SK		 2535 !pstate_funcs.get_min() ||
2536 !pstate_funcs.get_turbo())
b563b4e3
DB		 2537 return -ENODEV;
2538
b563b4e3
DB		 2539 return 0;
2540}
016c8150 2541
29327c84 2542static void __init copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB		 2543{
2544 pid_params.sample_rate_ms = policy->sample_rate_ms;
a4675fbc 2545 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
016c8150
DB		 2546 pid_params.p_gain_pct = policy->p_gain_pct;
2547 pid_params.i_gain_pct = policy->i_gain_pct;
2548 pid_params.d_gain_pct = policy->d_gain_pct;
2549 pid_params.deadband = policy->deadband;
2550 pid_params.setpoint = policy->setpoint;
2551}
2552
7f7a516e
SP		 2553#ifdef CONFIG_ACPI
2554static void intel_pstate_use_acpi_profile(void)
2555{
2556 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2557 pstate_funcs.get_target_pstate =
2558 get_target_pstate_use_cpu_load;
2559}
2560#else
2561static void intel_pstate_use_acpi_profile(void)
2562{
2563}
2564#endif
2565
29327c84 2566static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2567{
2568 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2569 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2570 pstate_funcs.get_min = funcs->get_min;
2571 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2572 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2573 pstate_funcs.get_val = funcs->get_val;
007bea09 2574 pstate_funcs.get_vid = funcs->get_vid;
157386b6
PL		 2575 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2576
7f7a516e 2577 intel_pstate_use_acpi_profile();
016c8150
DB		 2578}
2579
9522a2ff 2580#ifdef CONFIG_ACPI
fbbcdc07 2581
29327c84 2582static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2583{
2584 int i;
2585
2586 for_each_possible_cpu(i) {
2587 acpi_status status;
2588 union acpi_object *pss;
2589 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2590 struct acpi_processor *pr = per_cpu(processors, i);
2591
2592 if (!pr)
2593 continue;
2594
2595 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2596 if (ACPI_FAILURE(status))
2597 continue;
2598
2599 pss = buffer.pointer;
2600 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2601 kfree(pss);
2602 return false;
2603 }
2604
2605 kfree(pss);
2606 }
2607
2608 return true;
2609}
2610
29327c84 2611static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2612{
2613 int i;
2614
2615 for_each_possible_cpu(i) {
2616 struct acpi_processor *pr = per_cpu(processors, i);
2617
2618 if (!pr)
2619 continue;
2620 if (acpi_has_method(pr->handle, "_PPC"))
2621 return true;
2622 }
2623 return false;
2624}
2625
2626enum {
2627 PSS,
2628 PPC,
2629};
2630
fbbcdc07
AH		 2631struct hw_vendor_info {
2632 u16 valid;
2633 char oem_id[ACPI_OEM_ID_SIZE];
2634 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
966916ea 2635 int oem_pwr_table;
fbbcdc07
AH		 2636};
2637
2638/* Hardware vendor-specific info that has its own power management modes */
29327c84 2639static struct hw_vendor_info vendor_info[] __initdata = {
966916ea 2640 {1, "HP ", "ProLiant", PSS},
2641 {1, "ORACLE", "X4-2 ", PPC},
2642 {1, "ORACLE", "X4-2L ", PPC},
2643 {1, "ORACLE", "X4-2B ", PPC},
2644 {1, "ORACLE", "X3-2 ", PPC},
2645 {1, "ORACLE", "X3-2L ", PPC},
2646 {1, "ORACLE", "X3-2B ", PPC},
2647 {1, "ORACLE", "X4470M2 ", PPC},
2648 {1, "ORACLE", "X4270M3 ", PPC},
2649 {1, "ORACLE", "X4270M2 ", PPC},
2650 {1, "ORACLE", "X4170M2 ", PPC},
5aecc3c8
EZ		 2651 {1, "ORACLE", "X4170 M3", PPC},
2652 {1, "ORACLE", "X4275 M3", PPC},
2653 {1, "ORACLE", "X6-2 ", PPC},
2654 {1, "ORACLE", "Sudbury ", PPC},
fbbcdc07
AH		 2655 {0, "", ""},
2656};
2657
29327c84 2658static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07
AH		 2659{
2660 struct acpi_table_header hdr;
2661 struct hw_vendor_info *v_info;
2f86dc4c
DB		 2662 const struct x86_cpu_id *id;
2663 u64 misc_pwr;
2664
2665 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2666 if (id) {
2667 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2668 if ( misc_pwr & (1 << 8))
2669 return true;
2670 }
fbbcdc07 2671
c410833a
SK		 2672 if (acpi_disabled ||
2673 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
fbbcdc07
AH		 2674 return false;
2675
2676 for (v_info = vendor_info; v_info->valid; v_info++) {
c410833a 2677 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
966916ea 2678 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2679 ACPI_OEM_TABLE_ID_SIZE))
2680 switch (v_info->oem_pwr_table) {
2681 case PSS:
2682 return intel_pstate_no_acpi_pss();
2683 case PPC:
aa4ea34d
EZ		 2684 return intel_pstate_has_acpi_ppc() &&
2685 (!force_load);
966916ea 2686 }
fbbcdc07
AH		 2687 }
2688
2689 return false;
2690}
d0ea59e1
RW		 2691
2692static void intel_pstate_request_control_from_smm(void)
2693{
2694 /*
2695 * It may be unsafe to request P-states control from SMM if _PPC support
2696 * has not been enabled.
2697 */
2698 if (acpi_ppc)
2699 acpi_processor_pstate_control();
2700}
fbbcdc07
AH		 2701#else /* CONFIG_ACPI not enabled */
2702static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2703static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2704static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2705#endif /* CONFIG_ACPI */
2706
7791e4aa
SP		 2707static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2708 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2709 {}
2710};
2711
93f0822d
DB		 2712static int __init intel_pstate_init(void)
2713{
93f0822d 2714 const struct x86_cpu_id *id;
64df1fdf 2715 struct cpu_defaults *cpu_def;
fb1fe104 2716 int rc = 0;
93f0822d 2717
6be26498
DB		 2718 if (no_load)
2719 return -ENODEV;
2720
7791e4aa
SP		 2721 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2722 copy_cpu_funcs(&core_params.funcs);
2723 hwp_active++;
984edbdc 2724 intel_pstate.attr = hwp_cpufreq_attrs;
7791e4aa
SP		 2725 goto hwp_cpu_matched;
2726 }
2727
93f0822d
DB		 2728 id = x86_match_cpu(intel_pstate_cpu_ids);
2729 if (!id)
2730 return -ENODEV;
2731
64df1fdf 2732 cpu_def = (struct cpu_defaults *)id->driver_data;
016c8150 2733
64df1fdf
BP		 2734 copy_pid_params(&cpu_def->pid_policy);
2735 copy_cpu_funcs(&cpu_def->funcs);
016c8150 2736
b563b4e3
DB		 2737 if (intel_pstate_msrs_not_valid())
2738 return -ENODEV;
2739
7791e4aa
SP		 2740hwp_cpu_matched:
2741 /*
2742 * The Intel pstate driver will be ignored if the platform
2743 * firmware has its own power management modes.
2744 */
2745 if (intel_pstate_platform_pwr_mgmt_exists())
2746 return -ENODEV;
2747
fb1fe104
RW		 2748 if (!hwp_active && hwp_only)
2749 return -ENOTSUPP;
2750
4836df17 2751 pr_info("Intel P-state driver initializing\n");
93f0822d 2752
b57ffac5 2753 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB		 2754 if (!all_cpu_data)
2755 return -ENOMEM;
93f0822d 2756
d0ea59e1
RW		 2757 intel_pstate_request_control_from_smm();
2758
93f0822d 2759 intel_pstate_sysfs_expose_params();
b69880f9 2760
0c30b65b 2761 mutex_lock(&intel_pstate_driver_lock);
fb1fe104 2762 rc = intel_pstate_register_driver();
0c30b65b 2763 mutex_unlock(&intel_pstate_driver_lock);
fb1fe104
RW		 2764 if (rc)
2765 return rc;
366430b5 2766
7791e4aa 2767 if (hwp_active)
4836df17 2768 pr_info("HWP enabled\n");
7791e4aa 2769
fb1fe104 2770 return 0;
93f0822d
DB		 2771}
2772device_initcall(intel_pstate_init);
2773
6be26498
DB		 2774static int __init intel_pstate_setup(char *str)
2775{
2776 if (!str)
2777 return -EINVAL;
2778
001c76f0 2779 if (!strcmp(str, "disable")) {
6be26498 2780 no_load = 1;
001c76f0
RW		 2781 } else if (!strcmp(str, "passive")) {
2782 pr_info("Passive mode enabled\n");
2783 intel_pstate_driver = &intel_cpufreq;
2784 no_hwp = 1;
2785 }
539342f6 2786 if (!strcmp(str, "no_hwp")) {
4836df17 2787 pr_info("HWP disabled\n");
2f86dc4c 2788 no_hwp = 1;
539342f6 2789 }
aa4ea34d
EZ		 2790 if (!strcmp(str, "force"))
2791 force_load = 1;
d64c3b0b
KCA		 2792 if (!strcmp(str, "hwp_only"))
2793 hwp_only = 1;
eae48f04
SP		 2794 if (!strcmp(str, "per_cpu_perf_limits"))
2795 per_cpu_limits = true;
9522a2ff
SP		 2796
2797#ifdef CONFIG_ACPI
2798 if (!strcmp(str, "support_acpi_ppc"))
2799 acpi_ppc = true;
2800#endif
2801
6be26498
DB		 2802 return 0;
2803}
2804early_param("intel_pstate", intel_pstate_setup);
2805
93f0822d
DB		 2806MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2807MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2808MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)