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Merge tag 'sound-fix-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[linux-2.6-block.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
55687da1 22#include <linux/sched/cpufreq.h>
93f0822d
DB		 23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
fbbcdc07 29#include <linux/acpi.h>
d6472302 30#include <linux/vmalloc.h>
93f0822d
DB		 31#include <trace/events/power.h>
32
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
64df1fdf 36#include <asm/cpufeature.h>
5b20c944 37#include <asm/intel-family.h>
93f0822d 38
d77d4888 39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
eabd22c6 40
001c76f0 41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
1b72e7fd 42#define INTEL_CPUFREQ_TRANSITION_DELAY 500
001c76f0 43
9522a2ff
SP		 44#ifdef CONFIG_ACPI
45#include <acpi/processor.h>
17669006 46#include <acpi/cppc_acpi.h>
9522a2ff
SP		 47#endif
48
f0fe3cd7 49#define FRAC_BITS 8
93f0822d
DB		 50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 52
a1c9787d
RW		 53#define EXT_BITS 6
54#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 55#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 57
93f0822d
DB		 58static inline int32_t mul_fp(int32_t x, int32_t y)
59{
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61}
62
7180dddf 63static inline int32_t div_fp(s64 x, s64 y)
93f0822d 64{
7180dddf 65 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 66}
67
d022a65e
DB		 68static inline int ceiling_fp(int32_t x)
69{
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77}
78
ff35f02e
RW		 79static inline int32_t percent_fp(int percent)
80{
81 return div_fp(percent, 100);
82}
83
a1c9787d
RW		 84static inline u64 mul_ext_fp(u64 x, u64 y)
85{
86 return (x * y) >> EXT_FRAC_BITS;
87}
88
89static inline u64 div_ext_fp(u64 x, u64 y)
90{
91 return div64_u64(x << EXT_FRAC_BITS, y);
92}
93
e4c204ce
RW		 94static inline int32_t percent_ext_fp(int percent)
95{
96 return div_ext_fp(percent, 100);
97}
98
13ad7701
SP		 99/**
100 * struct sample - Store performance sample
a1c9787d 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 104 * P state. This can be different than core_avg_perf
13ad7701
SP		 105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
13ad7701
SP		 112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
93f0822d 117struct sample {
a1c9787d 118 int32_t core_avg_perf;
157386b6 119 int32_t busy_scaled;
93f0822d
DB		 120 u64 aperf;
121 u64 mperf;
4055fad3 122 u64 tsc;
a4675fbc 123 u64 time;
93f0822d
DB		 124};
125
13ad7701
SP		 126/**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
93f0822d
DB		 142struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
3bcc6fa9 146 int max_pstate_physical;
b27580b0 147 int scaling;
93f0822d 148 int turbo_pstate;
001c76f0
RW		 149 unsigned int max_freq;
150 unsigned int turbo_freq;
93f0822d
DB		 151};
152
13ad7701
SP		 153/**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
007bea09 166struct vid_data {
21855ff5
DB		 167 int min;
168 int max;
169 int turbo;
007bea09
DB		 170 int32_t ratio;
171};
172
c5a2ee7d
RW		 173/**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
183 * P-state capacity.
184 */
185struct global_params {
186 bool no_turbo;
187 bool turbo_disabled;
188 int max_perf_pct;
189 int min_perf_pct;
eae48f04
SP		 190};
191
13ad7701
SP		 192/**
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
2f1d407a 195 * @policy: CPUFreq policy value
13ad7701 196 * @update_util: CPUFreq utility callback information
4578ee7e 197 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
13ad7701
SP		 200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
13ad7701 202 * @last_sample_time: Last Sample time
6e34e1f2
SP		 203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
13ad7701
SP		 206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
1a4fe38a
SP		 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
9522a2ff
SP		 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
8442885f 219 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
e0efd5be
SP		 224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
52ccc431
SP		 226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
e0efd5be 228 * @hwp_boost_min: Last HWP boosted min performance
13ad7701
SP		 229 *
230 * This structure stores per CPU instance data for all CPUs.
231 */
93f0822d
DB		 232struct cpudata {
233 int cpu;
234
2f1d407a 235 unsigned int policy;
a4675fbc 236 struct update_util_data update_util;
4578ee7e 237 bool update_util_set;
93f0822d 238
93f0822d 239 struct pstate_data pstate;
007bea09 240 struct vid_data vid;
93f0822d 241
09c448d3 242 u64 last_update;
a4675fbc 243 u64 last_sample_time;
6e34e1f2 244 u64 aperf_mperf_shift;
93f0822d
DB		 245 u64 prev_aperf;
246 u64 prev_mperf;
4055fad3 247 u64 prev_tsc;
63d1d656 248 u64 prev_cummulative_iowait;
d37e2b76 249 struct sample sample;
1a4fe38a
SP		 250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
9522a2ff
SP		 252#ifdef CONFIG_ACPI
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
255#endif
09c448d3 256 unsigned int iowait_boost;
984edbdc 257 s16 epp_powersave;
8442885f 258 s16 epp_policy;
984edbdc
SP		 259 s16 epp_default;
260 s16 epp_saved;
e0efd5be
SP		 261 u64 hwp_req_cached;
262 u64 hwp_cap_cached;
52ccc431
SP		 263 u64 last_io_update;
264 unsigned int sched_flags;
e0efd5be 265 u32 hwp_boost_min;
93f0822d
DB		 266};
267
268static struct cpudata **all_cpu_data;
13ad7701 269
13ad7701
SP		 270/**
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
13ad7701
SP		 279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
016c8150
DB		 283struct pstate_funcs {
284 int (*get_max)(void);
3bcc6fa9 285 int (*get_max_physical)(void);
016c8150
DB		 286 int (*get_min)(void);
287 int (*get_turbo)(void);
b27580b0 288 int (*get_scaling)(void);
6e34e1f2 289 int (*get_aperf_mperf_shift)(void);
fdfdb2b1 290 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 291 void (*get_vid)(struct cpudata *);
93f0822d
DB		 292};
293
4a7cb7a9 294static struct pstate_funcs pstate_funcs __read_mostly;
5c439053 295
4a7cb7a9 296static int hwp_active __read_mostly;
eae48f04 297static bool per_cpu_limits __read_mostly;
e0efd5be 298static bool hwp_boost __read_mostly;
016c8150 299
ee8df89a 300static struct cpufreq_driver *intel_pstate_driver __read_mostly;
0c30b65b 301
9522a2ff
SP		 302#ifdef CONFIG_ACPI
303static bool acpi_ppc;
304#endif
13ad7701 305
c5a2ee7d 306static struct global_params global;
93f0822d 307
0c30b65b 308static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 309static DEFINE_MUTEX(intel_pstate_limits_lock);
310
9522a2ff 311#ifdef CONFIG_ACPI
2b3ec765
SP		 312
313static bool intel_pstate_get_ppc_enable_status(void)
314{
315 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
316 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
317 return true;
318
319 return acpi_ppc;
320}
321
17669006
RW		 322#ifdef CONFIG_ACPI_CPPC_LIB
323
324/* The work item is needed to avoid CPU hotplug locking issues */
325static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
326{
327 sched_set_itmt_support();
328}
329
330static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
331
332static void intel_pstate_set_itmt_prio(int cpu)
333{
334 struct cppc_perf_caps cppc_perf;
335 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
336 int ret;
337
338 ret = cppc_get_perf_caps(cpu, &cppc_perf);
339 if (ret)
340 return;
341
342 /*
343 * The priorities can be set regardless of whether or not
344 * sched_set_itmt_support(true) has been called and it is valid to
345 * update them at any time after it has been called.
346 */
347 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
348
349 if (max_highest_perf <= min_highest_perf) {
350 if (cppc_perf.highest_perf > max_highest_perf)
351 max_highest_perf = cppc_perf.highest_perf;
352
353 if (cppc_perf.highest_perf < min_highest_perf)
354 min_highest_perf = cppc_perf.highest_perf;
355
356 if (max_highest_perf > min_highest_perf) {
357 /*
358 * This code can be run during CPU online under the
359 * CPU hotplug locks, so sched_set_itmt_support()
360 * cannot be called from here. Queue up a work item
361 * to invoke it.
362 */
363 schedule_work(&sched_itmt_work);
364 }
365 }
366}
367#else
368static void intel_pstate_set_itmt_prio(int cpu)
369{
370}
371#endif
372
9522a2ff
SP		 373static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
374{
375 struct cpudata *cpu;
9522a2ff
SP		 376 int ret;
377 int i;
378
17669006
RW		 379 if (hwp_active) {
380 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 381 return;
17669006 382 }
e59a8f7f 383
2b3ec765 384 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 385 return;
386
387 cpu = all_cpu_data[policy->cpu];
388
389 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
390 policy->cpu);
391 if (ret)
392 return;
393
394 /*
395 * Check if the control value in _PSS is for PERF_CTL MSR, which should
396 * guarantee that the states returned by it map to the states in our
397 * list directly.
398 */
399 if (cpu->acpi_perf_data.control_register.space_id !=
400 ACPI_ADR_SPACE_FIXED_HARDWARE)
401 goto err;
402
403 /*
404 * If there is only one entry _PSS, simply ignore _PSS and continue as
405 * usual without taking _PSS into account
406 */
407 if (cpu->acpi_perf_data.state_count < 2)
408 goto err;
409
410 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
411 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
412 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
413 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
414 (u32) cpu->acpi_perf_data.states[i].core_frequency,
415 (u32) cpu->acpi_perf_data.states[i].power,
416 (u32) cpu->acpi_perf_data.states[i].control);
417 }
418
419 /*
420 * The _PSS table doesn't contain whole turbo frequency range.
421 * This just contains +1 MHZ above the max non turbo frequency,
422 * with control value corresponding to max turbo ratio. But
423 * when cpufreq set policy is called, it will call with this
424 * max frequency, which will cause a reduced performance as
425 * this driver uses real max turbo frequency as the max
426 * frequency. So correct this frequency in _PSS table to
b00345d1 427 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 428 * Also need to convert to MHz as _PSS freq is in MHz.
429 */
7de32556 430 if (!global.turbo_disabled)
9522a2ff
SP		 431 cpu->acpi_perf_data.states[0].core_frequency =
432 policy->cpuinfo.max_freq / 1000;
433 cpu->valid_pss_table = true;
6cacd115 434 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 435
436 return;
437
438 err:
439 cpu->valid_pss_table = false;
440 acpi_processor_unregister_performance(policy->cpu);
441}
442
443static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
444{
445 struct cpudata *cpu;
446
447 cpu = all_cpu_data[policy->cpu];
448 if (!cpu->valid_pss_table)
449 return;
450
451 acpi_processor_unregister_performance(policy->cpu);
452}
9522a2ff 453#else
7a3ba767 454static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 455{
456}
457
7a3ba767 458static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 459{
460}
461#endif
462
4521e1a0
GM		 463static inline void update_turbo_state(void)
464{
465 u64 misc_en;
466 struct cpudata *cpu;
467
468 cpu = all_cpu_data[0];
469 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
7de32556 470 global.turbo_disabled =
4521e1a0
GM		 471 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
472 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
473}
474
c5a2ee7d
RW		 475static int min_perf_pct_min(void)
476{
477 struct cpudata *cpu = all_cpu_data[0];
57caf4ec 478 int turbo_pstate = cpu->pstate.turbo_pstate;
c5a2ee7d 479
57caf4ec 480 return turbo_pstate ?
d4436c0d 481 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
c5a2ee7d
RW		 482}
483
8442885f
SP		 484static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
485{
486 u64 epb;
487 int ret;
488
489 if (!static_cpu_has(X86_FEATURE_EPB))
490 return -ENXIO;
491
492 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
493 if (ret)
494 return (s16)ret;
495
496 return (s16)(epb & 0x0f);
497}
498
499static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
500{
501 s16 epp;
502
984edbdc
SP		 503 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
504 /*
505 * When hwp_req_data is 0, means that caller didn't read
506 * MSR_HWP_REQUEST, so need to read and get EPP.
507 */
508 if (!hwp_req_data) {
509 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
510 &hwp_req_data);
511 if (epp)
512 return epp;
513 }
8442885f 514 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 515 } else {
8442885f
SP		 516 /* When there is no EPP present, HWP uses EPB settings */
517 epp = intel_pstate_get_epb(cpu_data);
984edbdc 518 }
8442885f
SP		 519
520 return epp;
521}
522
984edbdc 523static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 524{
525 u64 epb;
984edbdc 526 int ret;
8442885f
SP		 527
528 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 529 return -ENXIO;
8442885f 530
984edbdc
SP		 531 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
532 if (ret)
533 return ret;
8442885f
SP		 534
535 epb = (epb & ~0x0f) | pref;
536 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 537
538 return 0;
8442885f
SP		 539}
540
984edbdc
SP		 541/*
542 * EPP/EPB display strings corresponding to EPP index in the
543 * energy_perf_strings[]
544 * index String
545 *-------------------------------------
546 * 0 default
547 * 1 performance
548 * 2 balance_performance
549 * 3 balance_power
550 * 4 power
551 */
552static const char * const energy_perf_strings[] = {
553 "default",
554 "performance",
555 "balance_performance",
556 "balance_power",
557 "power",
558 NULL
559};
3cedbc5a
LB		 560static const unsigned int epp_values[] = {
561 HWP_EPP_PERFORMANCE,
562 HWP_EPP_BALANCE_PERFORMANCE,
563 HWP_EPP_BALANCE_POWERSAVE,
564 HWP_EPP_POWERSAVE
565};
984edbdc
SP		 566
567static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
568{
569 s16 epp;
570 int index = -EINVAL;
571
572 epp = intel_pstate_get_epp(cpu_data, 0);
573 if (epp < 0)
574 return epp;
575
576 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
3cedbc5a
LB		 577 if (epp == HWP_EPP_PERFORMANCE)
578 return 1;
579 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
580 return 2;
581 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
582 return 3;
583 else
584 return 4;
984edbdc
SP		 585 } else if (static_cpu_has(X86_FEATURE_EPB)) {
586 /*
587 * Range:
588 * 0x00-0x03 : Performance
589 * 0x04-0x07 : Balance performance
590 * 0x08-0x0B : Balance power
591 * 0x0C-0x0F : Power
592 * The EPB is a 4 bit value, but our ranges restrict the
593 * value which can be set. Here only using top two bits
594 * effectively.
595 */
596 index = (epp >> 2) + 1;
597 }
598
599 return index;
600}
601
602static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
603 int pref_index)
604{
605 int epp = -EINVAL;
606 int ret;
607
608 if (!pref_index)
609 epp = cpu_data->epp_default;
610
611 mutex_lock(&intel_pstate_limits_lock);
612
613 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
614 u64 value;
615
616 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
617 if (ret)
618 goto return_pref;
619
620 value &= ~GENMASK_ULL(31, 24);
621
984edbdc 622 if (epp == -EINVAL)
3cedbc5a 623 epp = epp_values[pref_index - 1];
984edbdc
SP		 624
625 value |= (u64)epp << 24;
626 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
627 } else {
628 if (epp == -EINVAL)
629 epp = (pref_index - 1) << 2;
630 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
631 }
632return_pref:
633 mutex_unlock(&intel_pstate_limits_lock);
634
635 return ret;
636}
637
638static ssize_t show_energy_performance_available_preferences(
639 struct cpufreq_policy *policy, char *buf)
640{
641 int i = 0;
642 int ret = 0;
643
644 while (energy_perf_strings[i] != NULL)
645 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
646
647 ret += sprintf(&buf[ret], "\n");
648
649 return ret;
650}
651
652cpufreq_freq_attr_ro(energy_performance_available_preferences);
653
654static ssize_t store_energy_performance_preference(
655 struct cpufreq_policy *policy, const char *buf, size_t count)
656{
657 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
658 char str_preference[21];
659 int ret, i = 0;
660
661 ret = sscanf(buf, "%20s", str_preference);
662 if (ret != 1)
663 return -EINVAL;
664
665 while (energy_perf_strings[i] != NULL) {
666 if (!strcmp(str_preference, energy_perf_strings[i])) {
667 intel_pstate_set_energy_pref_index(cpu_data, i);
668 return count;
669 }
670 ++i;
671 }
672
673 return -EINVAL;
674}
675
676static ssize_t show_energy_performance_preference(
677 struct cpufreq_policy *policy, char *buf)
678{
679 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
680 int preference;
681
682 preference = intel_pstate_get_energy_pref_index(cpu_data);
683 if (preference < 0)
684 return preference;
685
686 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
687}
688
689cpufreq_freq_attr_rw(energy_performance_preference);
690
691static struct freq_attr *hwp_cpufreq_attrs[] = {
692 &energy_performance_preference,
693 &energy_performance_available_preferences,
694 NULL,
695};
696
1a4fe38a
SP		 697static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
698 int *current_max)
2f86dc4c 699{
1a4fe38a 700 u64 cap;
74da56ce 701
2bfc4cbb 702 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
e0efd5be 703 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
2bfc4cbb 704 if (global.no_turbo)
1a4fe38a 705 *current_max = HWP_GUARANTEED_PERF(cap);
2bfc4cbb 706 else
1a4fe38a
SP		 707 *current_max = HWP_HIGHEST_PERF(cap);
708
709 *phy_max = HWP_HIGHEST_PERF(cap);
710}
711
712static void intel_pstate_hwp_set(unsigned int cpu)
713{
714 struct cpudata *cpu_data = all_cpu_data[cpu];
715 int max, min;
716 u64 value;
717 s16 epp;
718
719 max = cpu_data->max_perf_ratio;
720 min = cpu_data->min_perf_ratio;
eae48f04 721
2bfc4cbb
RW		 722 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
723 min = max;
3f8ed54a 724
2bfc4cbb 725 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
2f86dc4c 726
2bfc4cbb
RW		 727 value &= ~HWP_MIN_PERF(~0L);
728 value |= HWP_MIN_PERF(min);
8442885f 729
2bfc4cbb
RW		 730 value &= ~HWP_MAX_PERF(~0L);
731 value |= HWP_MAX_PERF(max);
8442885f 732
2bfc4cbb
RW		 733 if (cpu_data->epp_policy == cpu_data->policy)
734 goto skip_epp;
8442885f 735
2bfc4cbb 736 cpu_data->epp_policy = cpu_data->policy;
984edbdc 737
2bfc4cbb
RW		 738 if (cpu_data->epp_saved >= 0) {
739 epp = cpu_data->epp_saved;
740 cpu_data->epp_saved = -EINVAL;
741 goto update_epp;
742 }
8442885f 743
2bfc4cbb
RW		 744 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
745 epp = intel_pstate_get_epp(cpu_data, value);
746 cpu_data->epp_powersave = epp;
747 /* If EPP read was failed, then don't try to write */
748 if (epp < 0)
749 goto skip_epp;
8442885f 750
2bfc4cbb
RW		 751 epp = 0;
752 } else {
753 /* skip setting EPP, when saved value is invalid */
754 if (cpu_data->epp_powersave < 0)
755 goto skip_epp;
8442885f 756
2bfc4cbb
RW		 757 /*
758 * No need to restore EPP when it is not zero. This
759 * means:
760 * - Policy is not changed
761 * - user has manually changed
762 * - Error reading EPB
763 */
764 epp = intel_pstate_get_epp(cpu_data, value);
765 if (epp)
766 goto skip_epp;
8442885f 767
2bfc4cbb
RW		 768 epp = cpu_data->epp_powersave;
769 }
984edbdc 770update_epp:
2bfc4cbb
RW		 771 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
772 value &= ~GENMASK_ULL(31, 24);
773 value |= (u64)epp << 24;
774 } else {
775 intel_pstate_set_epb(cpu, epp);
2f86dc4c 776 }
2bfc4cbb 777skip_epp:
e0efd5be 778 WRITE_ONCE(cpu_data->hwp_req_cached, value);
2bfc4cbb 779 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
41cfd64c 780}
2f86dc4c 781
984edbdc
SP		 782static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
783{
784 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
785
786 if (!hwp_active)
787 return 0;
788
789 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
790
791 return 0;
792}
793
70f6bf2a
CY		 794static void intel_pstate_hwp_enable(struct cpudata *cpudata);
795
8442885f
SP		 796static int intel_pstate_resume(struct cpufreq_policy *policy)
797{
798 if (!hwp_active)
799 return 0;
800
aa439248
RW		 801 mutex_lock(&intel_pstate_limits_lock);
802
70f6bf2a
CY		 803 if (policy->cpu == 0)
804 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
805
8442885f 806 all_cpu_data[policy->cpu]->epp_policy = 0;
2bfc4cbb 807 intel_pstate_hwp_set(policy->cpu);
aa439248
RW		 808
809 mutex_unlock(&intel_pstate_limits_lock);
810
5f98ced1 811 return 0;
8442885f
SP		 812}
813
111b8b3f 814static void intel_pstate_update_policies(void)
41cfd64c 815{
111b8b3f
RW		 816 int cpu;
817
818 for_each_possible_cpu(cpu)
819 cpufreq_update_policy(cpu);
2f86dc4c
DB		 820}
821
93f0822d
DB		 822/************************** sysfs begin ************************/
823#define show_one(file_name, object) \
824 static ssize_t show_##file_name \
825 (struct kobject *kobj, struct attribute *attr, char *buf) \
826 { \
7de32556 827 return sprintf(buf, "%u\n", global.object); \
93f0822d
DB		 828 }
829
fb1fe104
RW		 830static ssize_t intel_pstate_show_status(char *buf);
831static int intel_pstate_update_status(const char *buf, size_t size);
832
833static ssize_t show_status(struct kobject *kobj,
834 struct attribute *attr, char *buf)
835{
836 ssize_t ret;
837
838 mutex_lock(&intel_pstate_driver_lock);
839 ret = intel_pstate_show_status(buf);
840 mutex_unlock(&intel_pstate_driver_lock);
841
842 return ret;
843}
844
845static ssize_t store_status(struct kobject *a, struct attribute *b,
846 const char *buf, size_t count)
847{
848 char *p = memchr(buf, '\n', count);
849 int ret;
850
851 mutex_lock(&intel_pstate_driver_lock);
852 ret = intel_pstate_update_status(buf, p ? p - buf : count);
853 mutex_unlock(&intel_pstate_driver_lock);
854
855 return ret < 0 ? ret : count;
856}
857
d01b1f48
KCA		 858static ssize_t show_turbo_pct(struct kobject *kobj,
859 struct attribute *attr, char *buf)
860{
861 struct cpudata *cpu;
862 int total, no_turbo, turbo_pct;
863 uint32_t turbo_fp;
864
0c30b65b
RW		 865 mutex_lock(&intel_pstate_driver_lock);
866
ee8df89a 867 if (!intel_pstate_driver) {
0c30b65b
RW		 868 mutex_unlock(&intel_pstate_driver_lock);
869 return -EAGAIN;
870 }
871
d01b1f48
KCA		 872 cpu = all_cpu_data[0];
873
874 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
875 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 876 turbo_fp = div_fp(no_turbo, total);
d01b1f48 877 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 878
879 mutex_unlock(&intel_pstate_driver_lock);
880
d01b1f48
KCA		 881 return sprintf(buf, "%u\n", turbo_pct);
882}
883
0522424e
KCA		 884static ssize_t show_num_pstates(struct kobject *kobj,
885 struct attribute *attr, char *buf)
886{
887 struct cpudata *cpu;
888 int total;
889
0c30b65b
RW		 890 mutex_lock(&intel_pstate_driver_lock);
891
ee8df89a 892 if (!intel_pstate_driver) {
0c30b65b
RW		 893 mutex_unlock(&intel_pstate_driver_lock);
894 return -EAGAIN;
895 }
896
0522424e
KCA		 897 cpu = all_cpu_data[0];
898 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 899
900 mutex_unlock(&intel_pstate_driver_lock);
901
0522424e
KCA		 902 return sprintf(buf, "%u\n", total);
903}
904
4521e1a0
GM		 905static ssize_t show_no_turbo(struct kobject *kobj,
906 struct attribute *attr, char *buf)
907{
908 ssize_t ret;
909
0c30b65b
RW		 910 mutex_lock(&intel_pstate_driver_lock);
911
ee8df89a 912 if (!intel_pstate_driver) {
0c30b65b
RW		 913 mutex_unlock(&intel_pstate_driver_lock);
914 return -EAGAIN;
915 }
916
4521e1a0 917 update_turbo_state();
7de32556
RW		 918 if (global.turbo_disabled)
919 ret = sprintf(buf, "%u\n", global.turbo_disabled);
4521e1a0 920 else
7de32556 921 ret = sprintf(buf, "%u\n", global.no_turbo);
4521e1a0 922
0c30b65b
RW		 923 mutex_unlock(&intel_pstate_driver_lock);
924
4521e1a0
GM		 925 return ret;
926}
927
93f0822d 928static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 929 const char *buf, size_t count)
93f0822d
DB		 930{
931 unsigned int input;
932 int ret;
845c1cbe 933
93f0822d
DB		 934 ret = sscanf(buf, "%u", &input);
935 if (ret != 1)
936 return -EINVAL;
4521e1a0 937
0c30b65b
RW		 938 mutex_lock(&intel_pstate_driver_lock);
939
ee8df89a 940 if (!intel_pstate_driver) {
0c30b65b
RW		 941 mutex_unlock(&intel_pstate_driver_lock);
942 return -EAGAIN;
943 }
944
a410c03d
SP		 945 mutex_lock(&intel_pstate_limits_lock);
946
4521e1a0 947 update_turbo_state();
7de32556 948 if (global.turbo_disabled) {
4836df17 949 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 950 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 951 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 952 return -EPERM;
dd5fbf70 953 }
2f86dc4c 954
7de32556 955 global.no_turbo = clamp_t(int, input, 0, 1);
111b8b3f 956
c5a2ee7d
RW		 957 if (global.no_turbo) {
958 struct cpudata *cpu = all_cpu_data[0];
959 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
960
961 /* Squash the global minimum into the permitted range. */
962 if (global.min_perf_pct > pct)
963 global.min_perf_pct = pct;
964 }
965
cd59b4be
RW		 966 mutex_unlock(&intel_pstate_limits_lock);
967
7de32556
RW		 968 intel_pstate_update_policies();
969
0c30b65b
RW		 970 mutex_unlock(&intel_pstate_driver_lock);
971
93f0822d
DB		 972 return count;
973}
974
975static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 976 const char *buf, size_t count)
93f0822d
DB		 977{
978 unsigned int input;
979 int ret;
845c1cbe 980
93f0822d
DB		 981 ret = sscanf(buf, "%u", &input);
982 if (ret != 1)
983 return -EINVAL;
984
0c30b65b
RW		 985 mutex_lock(&intel_pstate_driver_lock);
986
ee8df89a 987 if (!intel_pstate_driver) {
0c30b65b
RW		 988 mutex_unlock(&intel_pstate_driver_lock);
989 return -EAGAIN;
990 }
991
a410c03d
SP		 992 mutex_lock(&intel_pstate_limits_lock);
993
c5a2ee7d 994 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
111b8b3f 995
cd59b4be
RW		 996 mutex_unlock(&intel_pstate_limits_lock);
997
7de32556
RW		 998 intel_pstate_update_policies();
999
0c30b65b
RW		 1000 mutex_unlock(&intel_pstate_driver_lock);
1001
93f0822d
DB		 1002 return count;
1003}
1004
1005static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1006 const char *buf, size_t count)
93f0822d
DB		 1007{
1008 unsigned int input;
1009 int ret;
845c1cbe 1010
93f0822d
DB		 1011 ret = sscanf(buf, "%u", &input);
1012 if (ret != 1)
1013 return -EINVAL;
a0475992 1014
0c30b65b
RW		 1015 mutex_lock(&intel_pstate_driver_lock);
1016
ee8df89a 1017 if (!intel_pstate_driver) {
0c30b65b
RW		 1018 mutex_unlock(&intel_pstate_driver_lock);
1019 return -EAGAIN;
1020 }
1021
a410c03d
SP		 1022 mutex_lock(&intel_pstate_limits_lock);
1023
c5a2ee7d
RW		 1024 global.min_perf_pct = clamp_t(int, input,
1025 min_perf_pct_min(), global.max_perf_pct);
111b8b3f 1026
cd59b4be
RW		 1027 mutex_unlock(&intel_pstate_limits_lock);
1028
7de32556
RW		 1029 intel_pstate_update_policies();
1030
0c30b65b
RW		 1031 mutex_unlock(&intel_pstate_driver_lock);
1032
93f0822d
DB		 1033 return count;
1034}
1035
aaaece3d
SP		 1036static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1037 struct attribute *attr, char *buf)
1038{
1039 return sprintf(buf, "%u\n", hwp_boost);
1040}
1041
1042static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b,
1043 const char *buf, size_t count)
1044{
1045 unsigned int input;
1046 int ret;
1047
1048 ret = kstrtouint(buf, 10, &input);
1049 if (ret)
1050 return ret;
1051
1052 mutex_lock(&intel_pstate_driver_lock);
1053 hwp_boost = !!input;
1054 intel_pstate_update_policies();
1055 mutex_unlock(&intel_pstate_driver_lock);
1056
1057 return count;
1058}
1059
93f0822d
DB		 1060show_one(max_perf_pct, max_perf_pct);
1061show_one(min_perf_pct, min_perf_pct);
1062
fb1fe104 1063define_one_global_rw(status);
93f0822d
DB		 1064define_one_global_rw(no_turbo);
1065define_one_global_rw(max_perf_pct);
1066define_one_global_rw(min_perf_pct);
d01b1f48 1067define_one_global_ro(turbo_pct);
0522424e 1068define_one_global_ro(num_pstates);
aaaece3d 1069define_one_global_rw(hwp_dynamic_boost);
93f0822d
DB		 1070
1071static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1072 &status.attr,
93f0822d 1073 &no_turbo.attr,
d01b1f48 1074 &turbo_pct.attr,
0522424e 1075 &num_pstates.attr,
93f0822d
DB		 1076 NULL
1077};
1078
106c9c77 1079static const struct attribute_group intel_pstate_attr_group = {
93f0822d
DB		 1080 .attrs = intel_pstate_attributes,
1081};
93f0822d 1082
317dd50e 1083static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1084{
317dd50e 1085 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1086 int rc;
1087
1088 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1089 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1090 if (WARN_ON(!intel_pstate_kobject))
1091 return;
1092
2d8d1f18 1093 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1094 if (WARN_ON(rc))
1095 return;
1096
1097 /*
1098 * If per cpu limits are enforced there are no global limits, so
1099 * return without creating max/min_perf_pct attributes
1100 */
1101 if (per_cpu_limits)
1102 return;
1103
1104 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1105 WARN_ON(rc);
1106
1107 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1108 WARN_ON(rc);
1109
aaaece3d
SP		 1110 if (hwp_active) {
1111 rc = sysfs_create_file(intel_pstate_kobject,
1112 &hwp_dynamic_boost.attr);
1113 WARN_ON(rc);
1114 }
93f0822d 1115}
93f0822d 1116/************************** sysfs end ************************/
2f86dc4c 1117
ba88d433 1118static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1119{
f05c9665 1120 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1121 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1122 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1123
ba88d433 1124 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1125 cpudata->epp_policy = 0;
984edbdc
SP		 1126 if (cpudata->epp_default == -EINVAL)
1127 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1128}
1129
6e978b22
SP		 1130#define MSR_IA32_POWER_CTL_BIT_EE 19
1131
1132/* Disable energy efficiency optimization */
1133static void intel_pstate_disable_ee(int cpu)
1134{
1135 u64 power_ctl;
1136 int ret;
1137
1138 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1139 if (ret)
1140 return;
1141
1142 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1143 pr_info("Disabling energy efficiency optimization\n");
1144 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1145 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1146 }
1147}
1148
938d21a2 1149static int atom_get_min_pstate(void)
19e77c28
DB		 1150{
1151 u64 value;
845c1cbe 1152
92134bdb 1153 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1154 return (value >> 8) & 0x7F;
19e77c28
DB		 1155}
1156
938d21a2 1157static int atom_get_max_pstate(void)
19e77c28
DB		 1158{
1159 u64 value;
845c1cbe 1160
92134bdb 1161 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1162 return (value >> 16) & 0x7F;
19e77c28 1163}
93f0822d 1164
938d21a2 1165static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1166{
1167 u64 value;
845c1cbe 1168
92134bdb 1169 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1170 return value & 0x7F;
61d8d2ab
DB		 1171}
1172
fdfdb2b1 1173static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1174{
1175 u64 val;
1176 int32_t vid_fp;
1177 u32 vid;
1178
144c8e17 1179 val = (u64)pstate << 8;
7de32556 1180 if (global.no_turbo && !global.turbo_disabled)
007bea09
DB		 1181 val |= (u64)1 << 32;
1182
1183 vid_fp = cpudata->vid.min + mul_fp(
1184 int_tofp(pstate - cpudata->pstate.min_pstate),
1185 cpudata->vid.ratio);
1186
1187 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1188 vid = ceiling_fp(vid_fp);
007bea09 1189
21855ff5
DB		 1190 if (pstate > cpudata->pstate.max_pstate)
1191 vid = cpudata->vid.turbo;
1192
fdfdb2b1 1193 return val | vid;
007bea09
DB		 1194}
1195
1421df63 1196static int silvermont_get_scaling(void)
b27580b0
DB		 1197{
1198 u64 value;
1199 int i;
1421df63
PL		 1200 /* Defined in Table 35-6 from SDM (Sept 2015) */
1201 static int silvermont_freq_table[] = {
1202 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1203
1204 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1205 i = value & 0x7;
1206 WARN_ON(i > 4);
b27580b0 1207
1421df63
PL		 1208 return silvermont_freq_table[i];
1209}
b27580b0 1210
1421df63
PL		 1211static int airmont_get_scaling(void)
1212{
1213 u64 value;
1214 int i;
1215 /* Defined in Table 35-10 from SDM (Sept 2015) */
1216 static int airmont_freq_table[] = {
1217 83300, 100000, 133300, 116700, 80000,
1218 93300, 90000, 88900, 87500};
1219
1220 rdmsrl(MSR_FSB_FREQ, value);
1221 i = value & 0xF;
1222 WARN_ON(i > 8);
1223
1224 return airmont_freq_table[i];
b27580b0
DB		 1225}
1226
938d21a2 1227static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1228{
1229 u64 value;
1230
92134bdb 1231 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1232 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1233 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1234 cpudata->vid.ratio = div_fp(
1235 cpudata->vid.max - cpudata->vid.min,
1236 int_tofp(cpudata->pstate.max_pstate -
1237 cpudata->pstate.min_pstate));
21855ff5 1238
92134bdb 1239 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1240 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1241}
1242
016c8150 1243static int core_get_min_pstate(void)
93f0822d
DB		 1244{
1245 u64 value;
845c1cbe 1246
05e99c8c 1247 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1248 return (value >> 40) & 0xFF;
1249}
1250
3bcc6fa9 1251static int core_get_max_pstate_physical(void)
93f0822d
DB		 1252{
1253 u64 value;
845c1cbe 1254
05e99c8c 1255 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1256 return (value >> 8) & 0xFF;
1257}
1258
8fc7554a
SP		 1259static int core_get_tdp_ratio(u64 plat_info)
1260{
1261 /* Check how many TDP levels present */
1262 if (plat_info & 0x600000000) {
1263 u64 tdp_ctrl;
1264 u64 tdp_ratio;
1265 int tdp_msr;
1266 int err;
1267
1268 /* Get the TDP level (0, 1, 2) to get ratios */
1269 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1270 if (err)
1271 return err;
1272
1273 /* TDP MSR are continuous starting at 0x648 */
1274 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1275 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1276 if (err)
1277 return err;
1278
1279 /* For level 1 and 2, bits[23:16] contain the ratio */
1280 if (tdp_ctrl & 0x03)
1281 tdp_ratio >>= 16;
1282
1283 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1284 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1285
1286 return (int)tdp_ratio;
1287 }
1288
1289 return -ENXIO;
1290}
1291
016c8150 1292static int core_get_max_pstate(void)
93f0822d 1293{
6a35fc2d
SP		 1294 u64 tar;
1295 u64 plat_info;
1296 int max_pstate;
8fc7554a 1297 int tdp_ratio;
6a35fc2d
SP		 1298 int err;
1299
1300 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1301 max_pstate = (plat_info >> 8) & 0xFF;
1302
8fc7554a
SP		 1303 tdp_ratio = core_get_tdp_ratio(plat_info);
1304 if (tdp_ratio <= 0)
1305 return max_pstate;
1306
1307 if (hwp_active) {
1308 /* Turbo activation ratio is not used on HWP platforms */
1309 return tdp_ratio;
1310 }
1311
6a35fc2d
SP		 1312 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1313 if (!err) {
8fc7554a
SP		 1314 int tar_levels;
1315
6a35fc2d 1316 /* Do some sanity checking for safety */
8fc7554a
SP		 1317 tar_levels = tar & 0xff;
1318 if (tdp_ratio - 1 == tar_levels) {
1319 max_pstate = tar_levels;
1320 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1321 }
1322 }
845c1cbe 1323
6a35fc2d 1324 return max_pstate;
93f0822d
DB		 1325}
1326
016c8150 1327static int core_get_turbo_pstate(void)
93f0822d
DB		 1328{
1329 u64 value;
1330 int nont, ret;
845c1cbe 1331
100cf6f2 1332 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1333 nont = core_get_max_pstate();
285cb990 1334 ret = (value) & 255;
93f0822d
DB		 1335 if (ret <= nont)
1336 ret = nont;
1337 return ret;
1338}
1339
b27580b0
DB		 1340static inline int core_get_scaling(void)
1341{
1342 return 100000;
1343}
1344
fdfdb2b1 1345static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1346{
1347 u64 val;
1348
144c8e17 1349 val = (u64)pstate << 8;
7de32556 1350 if (global.no_turbo && !global.turbo_disabled)
016c8150
DB		 1351 val |= (u64)1 << 32;
1352
fdfdb2b1 1353 return val;
016c8150
DB		 1354}
1355
6e34e1f2
SP		 1356static int knl_get_aperf_mperf_shift(void)
1357{
1358 return 10;
1359}
1360
b34ef932
DC		 1361static int knl_get_turbo_pstate(void)
1362{
1363 u64 value;
1364 int nont, ret;
1365
100cf6f2 1366 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1367 nont = core_get_max_pstate();
1368 ret = (((value) >> 8) & 0xFF);
1369 if (ret <= nont)
1370 ret = nont;
1371 return ret;
1372}
1373
b02aabe8 1374static int intel_pstate_get_base_pstate(struct cpudata *cpu)
93f0822d 1375{
b02aabe8
RW		 1376 return global.no_turbo || global.turbo_disabled ?
1377 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
93f0822d
DB		 1378}
1379
a6c6ead1 1380static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1381{
bc95a454
RW		 1382 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1383 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1384 /*
1385 * Generally, there is no guarantee that this code will always run on
1386 * the CPU being updated, so force the register update to run on the
1387 * right CPU.
1388 */
1389 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1390 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1391}
1392
a6c6ead1
RW		 1393static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1394{
1395 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1396}
1397
1398static void intel_pstate_max_within_limits(struct cpudata *cpu)
1399{
b02aabe8 1400 int pstate;
a6c6ead1
RW		 1401
1402 update_turbo_state();
b02aabe8 1403 pstate = intel_pstate_get_base_pstate(cpu);
1a4fe38a 1404 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
b02aabe8 1405 intel_pstate_set_pstate(cpu, pstate);
a6c6ead1
RW		 1406}
1407
93f0822d
DB		 1408static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1409{
016c8150
DB		 1410 cpu->pstate.min_pstate = pstate_funcs.get_min();
1411 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1412 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1413 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1414 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0
RW		 1415 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1416 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d 1417
6e34e1f2
SP		 1418 if (pstate_funcs.get_aperf_mperf_shift)
1419 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1420
007bea09
DB		 1421 if (pstate_funcs.get_vid)
1422 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1423
1424 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1425}
1426
e0efd5be
SP		 1427/*
1428 * Long hold time will keep high perf limits for long time,
1429 * which negatively impacts perf/watt for some workloads,
1430 * like specpower. 3ms is based on experiements on some
1431 * workoads.
1432 */
1433static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1434
1435static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1436{
1437 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1438 u32 max_limit = (hwp_req & 0xff00) >> 8;
1439 u32 min_limit = (hwp_req & 0xff);
1440 u32 boost_level1;
1441
1442 /*
1443 * Cases to consider (User changes via sysfs or boot time):
1444 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1445 * No boost, return.
1446 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1447 * Should result in one level boost only for P0.
1448 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1449 * Should result in two level boost:
1450 * (min + p1)/2 and P1.
1451 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1452 * Should result in three level boost:
1453 * (min + p1)/2, P1 and P0.
1454 */
1455
1456 /* If max and min are equal or already at max, nothing to boost */
1457 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1458 return;
1459
1460 if (!cpu->hwp_boost_min)
1461 cpu->hwp_boost_min = min_limit;
1462
1463 /* level at half way mark between min and guranteed */
1464 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1465
1466 if (cpu->hwp_boost_min < boost_level1)
1467 cpu->hwp_boost_min = boost_level1;
1468 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1469 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1470 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1471 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1472 cpu->hwp_boost_min = max_limit;
1473 else
1474 return;
1475
1476 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1477 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1478 cpu->last_update = cpu->sample.time;
1479}
1480
1481static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1482{
1483 if (cpu->hwp_boost_min) {
1484 bool expired;
1485
1486 /* Check if we are idle for hold time to boost down */
1487 expired = time_after64(cpu->sample.time, cpu->last_update +
1488 hwp_boost_hold_time_ns);
1489 if (expired) {
1490 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1491 cpu->hwp_boost_min = 0;
1492 }
1493 }
1494 cpu->last_update = cpu->sample.time;
1495}
1496
52ccc431
SP		 1497static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1498 u64 time)
1499{
1500 cpu->sample.time = time;
1501
1502 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1503 bool do_io = false;
1504
1505 cpu->sched_flags = 0;
1506 /*
1507 * Set iowait_boost flag and update time. Since IO WAIT flag
1508 * is set all the time, we can't just conclude that there is
1509 * some IO bound activity is scheduled on this CPU with just
1510 * one occurrence. If we receive at least two in two
1511 * consecutive ticks, then we treat as boost candidate.
1512 */
1513 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1514 do_io = true;
1515
1516 cpu->last_io_update = time;
1517
1518 if (do_io)
1519 intel_pstate_hwp_boost_up(cpu);
1520
1521 } else {
1522 intel_pstate_hwp_boost_down(cpu);
1523 }
1524}
1525
e0efd5be
SP		 1526static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1527 u64 time, unsigned int flags)
1528{
52ccc431
SP		 1529 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1530
1531 cpu->sched_flags |= flags;
1532
1533 if (smp_processor_id() == cpu->cpu)
1534 intel_pstate_update_util_hwp_local(cpu, time);
e0efd5be
SP		 1535}
1536
a1c9787d 1537static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1538{
6b17ddb2 1539 struct sample *sample = &cpu->sample;
e66c1768 1540
a1c9787d 1541 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1542}
1543
4fec7ad5 1544static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1545{
93f0822d 1546 u64 aperf, mperf;
4ab60c3f 1547 unsigned long flags;
4055fad3 1548 u64 tsc;
93f0822d 1549
4ab60c3f 1550 local_irq_save(flags);
93f0822d
DB		 1551 rdmsrl(MSR_IA32_APERF, aperf);
1552 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1553 tsc = rdtsc();
4fec7ad5 1554 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1555 local_irq_restore(flags);
4fec7ad5 1556 return false;
8e601a9f 1557 }
4ab60c3f 1558 local_irq_restore(flags);
b69880f9 1559
c4ee841f 1560 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1561 cpu->sample.time = time;
d37e2b76
DB		 1562 cpu->sample.aperf = aperf;
1563 cpu->sample.mperf = mperf;
4055fad3 1564 cpu->sample.tsc = tsc;
d37e2b76
DB		 1565 cpu->sample.aperf -= cpu->prev_aperf;
1566 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1567 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1568
93f0822d
DB		 1569 cpu->prev_aperf = aperf;
1570 cpu->prev_mperf = mperf;
4055fad3 1571 cpu->prev_tsc = tsc;
febce40f
RW		 1572 /*
1573 * First time this function is invoked in a given cycle, all of the
1574 * previous sample data fields are equal to zero or stale and they must
1575 * be populated with meaningful numbers for things to work, so assume
1576 * that sample.time will always be reset before setting the utilization
1577 * update hook and make the caller skip the sample then.
1578 */
eabd22c6
RW		 1579 if (cpu->last_sample_time) {
1580 intel_pstate_calc_avg_perf(cpu);
1581 return true;
1582 }
1583 return false;
93f0822d
DB		 1584}
1585
8fa520af
PL		 1586static inline int32_t get_avg_frequency(struct cpudata *cpu)
1587{
c587c79f 1588 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
8fa520af
PL		 1589}
1590
bdcaa23f
PL		 1591static inline int32_t get_avg_pstate(struct cpudata *cpu)
1592{
8edb0a6e
RW		 1593 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1594 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1595}
1596
d77d4888 1597static inline int32_t get_target_pstate(struct cpudata *cpu)
e70eed2b
PL		 1598{
1599 struct sample *sample = &cpu->sample;
09c448d3 1600 int32_t busy_frac, boost;
0843e83c 1601 int target, avg_pstate;
e70eed2b 1602
6e34e1f2
SP		 1603 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1604 sample->tsc);
63d1d656 1605
09c448d3
RW		 1606 boost = cpu->iowait_boost;
1607 cpu->iowait_boost >>= 1;
63d1d656 1608
09c448d3
RW		 1609 if (busy_frac < boost)
1610 busy_frac = boost;
63d1d656 1611
09c448d3 1612 sample->busy_scaled = busy_frac * 100;
0843e83c 1613
7de32556 1614 target = global.no_turbo || global.turbo_disabled ?
0843e83c
RW		 1615 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1616 target += target >> 2;
1617 target = mul_fp(target, busy_frac);
1618 if (target < cpu->pstate.min_pstate)
1619 target = cpu->pstate.min_pstate;
1620
1621 /*
1622 * If the average P-state during the previous cycle was higher than the
1623 * current target, add 50% of the difference to the target to reduce
1624 * possible performance oscillations and offset possible performance
1625 * loss related to moving the workload from one CPU to another within
1626 * a package/module.
1627 */
1628 avg_pstate = get_avg_pstate(cpu);
1629 if (avg_pstate > target)
1630 target += (avg_pstate - target) >> 1;
1631
1632 return target;
e70eed2b
PL		 1633}
1634
001c76f0 1635static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1 1636{
b02aabe8
RW		 1637 int max_pstate = intel_pstate_get_base_pstate(cpu);
1638 int min_pstate;
fdfdb2b1 1639
1a4fe38a
SP		 1640 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1641 max_pstate = max(min_pstate, cpu->max_perf_ratio);
b02aabe8 1642 return clamp_t(int, pstate, min_pstate, max_pstate);
001c76f0
RW		 1643}
1644
1645static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1646{
fdfdb2b1
RW		 1647 if (pstate == cpu->pstate.current_pstate)
1648 return;
1649
bc95a454 1650 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1651 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1652}
1653
a891283e 1654static void intel_pstate_adjust_pstate(struct cpudata *cpu)
93f0822d 1655{
67dd9bf4 1656 int from = cpu->pstate.current_pstate;
4055fad3 1657 struct sample *sample;
a891283e 1658 int target_pstate;
4055fad3 1659
001c76f0
RW		 1660 update_turbo_state();
1661
d77d4888 1662 target_pstate = get_target_pstate(cpu);
64078299
RW		 1663 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1664 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1 1665 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1666
1667 sample = &cpu->sample;
a1c9787d 1668 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1669 fp_toint(sample->busy_scaled),
4055fad3
DS		 1670 from,
1671 cpu->pstate.current_pstate,
1672 sample->mperf,
1673 sample->aperf,
1674 sample->tsc,
3ba7bcaa
SP		 1675 get_avg_frequency(cpu),
1676 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1677}
1678
a4675fbc 1679static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1680 unsigned int flags)
93f0822d 1681{
a4675fbc 1682 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1683 u64 delta_ns;
1684
674e7541
VK		 1685 /* Don't allow remote callbacks */
1686 if (smp_processor_id() != cpu->cpu)
1687 return;
1688
eabd22c6
RW		 1689 if (flags & SCHED_CPUFREQ_IOWAIT) {
1690 cpu->iowait_boost = int_tofp(1);
7bde2d50
SP		 1691 cpu->last_update = time;
1692 /*
1693 * The last time the busy was 100% so P-state was max anyway
1694 * so avoid overhead of computation.
1695 */
1696 if (fp_toint(cpu->sample.busy_scaled) == 100)
1697 return;
1698
1699 goto set_pstate;
eabd22c6
RW		 1700 } else if (cpu->iowait_boost) {
1701 /* Clear iowait_boost if the CPU may have been idle. */
1702 delta_ns = time - cpu->last_update;
1703 if (delta_ns > TICK_NSEC)
1704 cpu->iowait_boost = 0;
09c448d3 1705 }
eabd22c6 1706 cpu->last_update = time;
09c448d3 1707 delta_ns = time - cpu->sample.time;
d77d4888 1708 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
eabd22c6 1709 return;
4fec7ad5 1710
7bde2d50 1711set_pstate:
a891283e
RW		 1712 if (intel_pstate_sample(cpu, time))
1713 intel_pstate_adjust_pstate(cpu);
67dd9bf4 1714}
eabd22c6 1715
2f49afc2
RW		 1716static struct pstate_funcs core_funcs = {
1717 .get_max = core_get_max_pstate,
1718 .get_max_physical = core_get_max_pstate_physical,
1719 .get_min = core_get_min_pstate,
1720 .get_turbo = core_get_turbo_pstate,
1721 .get_scaling = core_get_scaling,
1722 .get_val = core_get_val,
de4a76cb
RW		 1723};
1724
2f49afc2
RW		 1725static const struct pstate_funcs silvermont_funcs = {
1726 .get_max = atom_get_max_pstate,
1727 .get_max_physical = atom_get_max_pstate,
1728 .get_min = atom_get_min_pstate,
1729 .get_turbo = atom_get_turbo_pstate,
1730 .get_val = atom_get_val,
1731 .get_scaling = silvermont_get_scaling,
1732 .get_vid = atom_get_vid,
de4a76cb
RW		 1733};
1734
2f49afc2
RW		 1735static const struct pstate_funcs airmont_funcs = {
1736 .get_max = atom_get_max_pstate,
1737 .get_max_physical = atom_get_max_pstate,
1738 .get_min = atom_get_min_pstate,
1739 .get_turbo = atom_get_turbo_pstate,
1740 .get_val = atom_get_val,
1741 .get_scaling = airmont_get_scaling,
1742 .get_vid = atom_get_vid,
de4a76cb
RW		 1743};
1744
2f49afc2
RW		 1745static const struct pstate_funcs knl_funcs = {
1746 .get_max = core_get_max_pstate,
1747 .get_max_physical = core_get_max_pstate_physical,
1748 .get_min = core_get_min_pstate,
1749 .get_turbo = knl_get_turbo_pstate,
6e34e1f2 1750 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2f49afc2
RW		 1751 .get_scaling = core_get_scaling,
1752 .get_val = core_get_val,
de4a76cb
RW		 1753};
1754
93f0822d 1755#define ICPU(model, policy) \
6cbd7ee1
DB		 1756 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1757 (unsigned long)&policy }
93f0822d
DB		 1758
1759static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2f49afc2
RW		 1760 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1761 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1762 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1763 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1764 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1765 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1766 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1767 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1768 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1769 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1770 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1771 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1772 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1773 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1774 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1775 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1776 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1777 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
dbd49b85
SP		 1778 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1779 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
d8de7a44 1780 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
93f0822d
DB		 1781 {}
1782};
1783MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1784
29327c84 1785static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2f49afc2
RW		 1786 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1787 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1788 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
2f86dc4c
DB		 1789 {}
1790};
1791
6e978b22 1792static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2f49afc2 1793 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
6e978b22
SP		 1794 {}
1795};
1796
41ab43c9
SP		 1797static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1798 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1799 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1800 {}
1801};
1802
93f0822d
DB		 1803static int intel_pstate_init_cpu(unsigned int cpunum)
1804{
93f0822d
DB		 1805 struct cpudata *cpu;
1806
eae48f04
SP		 1807 cpu = all_cpu_data[cpunum];
1808
1809 if (!cpu) {
c5a2ee7d 1810 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
eae48f04
SP		 1811 if (!cpu)
1812 return -ENOMEM;
1813
1814 all_cpu_data[cpunum] = cpu;
eae48f04 1815
984edbdc
SP		 1816 cpu->epp_default = -EINVAL;
1817 cpu->epp_powersave = -EINVAL;
1818 cpu->epp_saved = -EINVAL;
eae48f04 1819 }
93f0822d
DB		 1820
1821 cpu = all_cpu_data[cpunum];
1822
93f0822d 1823 cpu->cpu = cpunum;
ba88d433 1824
a4675fbc 1825 if (hwp_active) {
6e978b22
SP		 1826 const struct x86_cpu_id *id;
1827
1828 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1829 if (id)
1830 intel_pstate_disable_ee(cpunum);
1831
ba88d433 1832 intel_pstate_hwp_enable(cpu);
41ab43c9
SP		 1833
1834 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1835 if (id)
1836 hwp_boost = true;
a4675fbc 1837 }
ba88d433 1838
179e8471 1839 intel_pstate_get_cpu_pstates(cpu);
016c8150 1840
4836df17 1841 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1842
1843 return 0;
1844}
1845
febce40f 1846static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1847{
febce40f
RW		 1848 struct cpudata *cpu = all_cpu_data[cpu_num];
1849
e0efd5be 1850 if (hwp_active && !hwp_boost)
62611cb9
LB		 1851 return;
1852
5ab666e0
RW		 1853 if (cpu->update_util_set)
1854 return;
1855
febce40f
RW		 1856 /* Prevent intel_pstate_update_util() from using stale data. */
1857 cpu->sample.time = 0;
67dd9bf4 1858 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
e0efd5be
SP		 1859 (hwp_active ?
1860 intel_pstate_update_util_hwp :
1861 intel_pstate_update_util));
4578ee7e 1862 cpu->update_util_set = true;
bb6ab52f
RW		 1863}
1864
1865static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1866{
4578ee7e
CY		 1867 struct cpudata *cpu_data = all_cpu_data[cpu];
1868
1869 if (!cpu_data->update_util_set)
1870 return;
1871
0bed612b 1872 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1873 cpu_data->update_util_set = false;
bb6ab52f
RW		 1874 synchronize_sched();
1875}
1876
80b120ca
RW		 1877static int intel_pstate_get_max_freq(struct cpudata *cpu)
1878{
1879 return global.turbo_disabled || global.no_turbo ?
1880 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1881}
1882
eae48f04 1883static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
c5a2ee7d 1884 struct cpudata *cpu)
eae48f04 1885{
80b120ca 1886 int max_freq = intel_pstate_get_max_freq(cpu);
e4c204ce 1887 int32_t max_policy_perf, min_policy_perf;
1a4fe38a 1888 int max_state, turbo_max;
a410c03d 1889
1a4fe38a
SP		 1890 /*
1891 * HWP needs some special consideration, because on BDX the
1892 * HWP_REQUEST uses abstract value to represent performance
1893 * rather than pure ratios.
1894 */
1895 if (hwp_active) {
1896 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1897 } else {
1898 max_state = intel_pstate_get_base_pstate(cpu);
1899 turbo_max = cpu->pstate.turbo_pstate;
1900 }
1901
1902 max_policy_perf = max_state * policy->max / max_freq;
5879f877 1903 if (policy->max == policy->min) {
e4c204ce 1904 min_policy_perf = max_policy_perf;
5879f877 1905 } else {
1a4fe38a 1906 min_policy_perf = max_state * policy->min / max_freq;
e4c204ce
RW		 1907 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1908 0, max_policy_perf);
5879f877 1909 }
eae48f04 1910
1a4fe38a
SP		 1911 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1912 policy->cpu, max_state,
1913 min_policy_perf, max_policy_perf);
1914
e4c204ce 1915 /* Normalize user input to [min_perf, max_perf] */
c5a2ee7d 1916 if (per_cpu_limits) {
1a4fe38a
SP		 1917 cpu->min_perf_ratio = min_policy_perf;
1918 cpu->max_perf_ratio = max_policy_perf;
c5a2ee7d
RW		 1919 } else {
1920 int32_t global_min, global_max;
1921
1922 /* Global limits are in percent of the maximum turbo P-state. */
1a4fe38a
SP		 1923 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1924 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
c5a2ee7d 1925 global_min = clamp_t(int32_t, global_min, 0, global_max);
eae48f04 1926
1a4fe38a
SP		 1927 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1928 global_min, global_max);
c5a2ee7d 1929
1a4fe38a
SP		 1930 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1931 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1932 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1933 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
eae48f04 1934
1a4fe38a
SP		 1935 /* Make sure min_perf <= max_perf */
1936 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1937 cpu->max_perf_ratio);
eae48f04 1938
1a4fe38a
SP		 1939 }
1940 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1941 cpu->max_perf_ratio,
1942 cpu->min_perf_ratio);
eae48f04
SP		 1943}
1944
93f0822d
DB		 1945static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1946{
3be9200d
SP		 1947 struct cpudata *cpu;
1948
d3929b83
DB		 1949 if (!policy->cpuinfo.max_freq)
1950 return -ENODEV;
1951
2c2c1af4
SP		 1952 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1953 policy->cpuinfo.max_freq, policy->max);
1954
a6c6ead1 1955 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 1956 cpu->policy = policy->policy;
1957
b59fe540
SP		 1958 mutex_lock(&intel_pstate_limits_lock);
1959
c5a2ee7d 1960 intel_pstate_update_perf_limits(policy, cpu);
a240c4aa 1961
2f1d407a 1962 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 1963 /*
1964 * NOHZ_FULL CPUs need this as the governor callback may not
1965 * be invoked on them.
1966 */
1967 intel_pstate_clear_update_util_hook(policy->cpu);
1968 intel_pstate_max_within_limits(cpu);
82b4e03e
LB		 1969 } else {
1970 intel_pstate_set_update_util_hook(policy->cpu);
a6c6ead1
RW		 1971 }
1972
e0efd5be
SP		 1973 if (hwp_active) {
1974 /*
1975 * When hwp_boost was active before and dynamically it
1976 * was turned off, in that case we need to clear the
1977 * update util hook.
1978 */
1979 if (!hwp_boost)
1980 intel_pstate_clear_update_util_hook(policy->cpu);
2bfc4cbb 1981 intel_pstate_hwp_set(policy->cpu);
e0efd5be 1982 }
2f86dc4c 1983
b59fe540
SP		 1984 mutex_unlock(&intel_pstate_limits_lock);
1985
93f0822d
DB		 1986 return 0;
1987}
1988
80b120ca
RW		 1989static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1990 struct cpudata *cpu)
1991{
1992 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1993 policy->max < policy->cpuinfo.max_freq &&
1994 policy->max > cpu->pstate.max_freq) {
1995 pr_debug("policy->max > max non turbo frequency\n");
1996 policy->max = policy->cpuinfo.max_freq;
1997 }
1998}
1999
93f0822d
DB		 2000static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2001{
7d9a8a9f 2002 struct cpudata *cpu = all_cpu_data[policy->cpu];
7d9a8a9f
SP		 2003
2004 update_turbo_state();
80b120ca
RW		 2005 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2006 intel_pstate_get_max_freq(cpu));
93f0822d 2007
285cb990 2008 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 2009 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 2010 return -EINVAL;
2011
80b120ca
RW		 2012 intel_pstate_adjust_policy_max(policy, cpu);
2013
93f0822d
DB		 2014 return 0;
2015}
2016
001c76f0
RW		 2017static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2018{
2019 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2020}
2021
bb18008f 2022static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 2023{
001c76f0 2024 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 2025
001c76f0 2026 intel_pstate_clear_update_util_hook(policy->cpu);
984edbdc
SP		 2027 if (hwp_active)
2028 intel_pstate_hwp_save_state(policy);
2029 else
001c76f0
RW		 2030 intel_cpufreq_stop_cpu(policy);
2031}
bb18008f 2032
001c76f0
RW		 2033static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2034{
2035 intel_pstate_exit_perf_limits(policy);
a4675fbc 2036
001c76f0 2037 policy->fast_switch_possible = false;
2f86dc4c 2038
001c76f0 2039 return 0;
93f0822d
DB		 2040}
2041
001c76f0 2042static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2043{
93f0822d 2044 struct cpudata *cpu;
52e0a509 2045 int rc;
93f0822d
DB		 2046
2047 rc = intel_pstate_init_cpu(policy->cpu);
2048 if (rc)
2049 return rc;
2050
2051 cpu = all_cpu_data[policy->cpu];
2052
1a4fe38a
SP		 2053 cpu->max_perf_ratio = 0xFF;
2054 cpu->min_perf_ratio = 0;
93f0822d 2055
b27580b0
DB		 2056 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2057 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 2058
2059 /* cpuinfo and default policy values */
b27580b0 2060 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e 2061 update_turbo_state();
7de32556 2062 policy->cpuinfo.max_freq = global.turbo_disabled ?
983e600e
SP		 2063 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2064 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2065
9522a2ff 2066 intel_pstate_init_acpi_perf_limits(policy);
93f0822d 2067
001c76f0
RW		 2068 policy->fast_switch_possible = true;
2069
93f0822d
DB		 2070 return 0;
2071}
2072
001c76f0 2073static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2074{
001c76f0
RW		 2075 int ret = __intel_pstate_cpu_init(policy);
2076
2077 if (ret)
2078 return ret;
2079
7de32556 2080 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
001c76f0
RW		 2081 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2082 else
2083 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 2084
2085 return 0;
2086}
2087
001c76f0 2088static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2089 .flags = CPUFREQ_CONST_LOOPS,
2090 .verify = intel_pstate_verify_policy,
2091 .setpolicy = intel_pstate_set_policy,
984edbdc 2092 .suspend = intel_pstate_hwp_save_state,
8442885f 2093 .resume = intel_pstate_resume,
93f0822d 2094 .init = intel_pstate_cpu_init,
9522a2ff 2095 .exit = intel_pstate_cpu_exit,
bb18008f 2096 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 2097 .name = "intel_pstate",
93f0822d
DB		 2098};
2099
001c76f0
RW		 2100static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2101{
2102 struct cpudata *cpu = all_cpu_data[policy->cpu];
001c76f0
RW		 2103
2104 update_turbo_state();
80b120ca
RW		 2105 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2106 intel_pstate_get_max_freq(cpu));
001c76f0 2107
80b120ca 2108 intel_pstate_adjust_policy_max(policy, cpu);
001c76f0 2109
c5a2ee7d
RW		 2110 intel_pstate_update_perf_limits(policy, cpu);
2111
001c76f0
RW		 2112 return 0;
2113}
2114
50e9ffab
DS		 2115/* Use of trace in passive mode:
2116 *
2117 * In passive mode the trace core_busy field (also known as the
2118 * performance field, and lablelled as such on the graphs; also known as
2119 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2120 * driver call was via the normal or fast switch path. Various graphs
2121 * output from the intel_pstate_tracer.py utility that include core_busy
2122 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2123 * so we use 10 to indicate the the normal path through the driver, and
2124 * 90 to indicate the fast switch path through the driver.
2125 * The scaled_busy field is not used, and is set to 0.
2126 */
2127
2128#define INTEL_PSTATE_TRACE_TARGET 10
2129#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2130
2131static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2132{
2133 struct sample *sample;
2134
2135 if (!trace_pstate_sample_enabled())
2136 return;
2137
2138 if (!intel_pstate_sample(cpu, ktime_get()))
2139 return;
2140
2141 sample = &cpu->sample;
2142 trace_pstate_sample(trace_type,
2143 0,
2144 old_pstate,
2145 cpu->pstate.current_pstate,
2146 sample->mperf,
2147 sample->aperf,
2148 sample->tsc,
2149 get_avg_frequency(cpu),
2150 fp_toint(cpu->iowait_boost * 100));
2151}
2152
001c76f0
RW		 2153static int intel_cpufreq_target(struct cpufreq_policy *policy,
2154 unsigned int target_freq,
2155 unsigned int relation)
2156{
2157 struct cpudata *cpu = all_cpu_data[policy->cpu];
2158 struct cpufreq_freqs freqs;
50e9ffab 2159 int target_pstate, old_pstate;
001c76f0 2160
64897b20
RW		 2161 update_turbo_state();
2162
001c76f0 2163 freqs.old = policy->cur;
64897b20 2164 freqs.new = target_freq;
001c76f0
RW		 2165
2166 cpufreq_freq_transition_begin(policy, &freqs);
2167 switch (relation) {
2168 case CPUFREQ_RELATION_L:
2169 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2170 break;
2171 case CPUFREQ_RELATION_H:
2172 target_pstate = freqs.new / cpu->pstate.scaling;
2173 break;
2174 default:
2175 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2176 break;
2177 }
2178 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2179 old_pstate = cpu->pstate.current_pstate;
001c76f0
RW		 2180 if (target_pstate != cpu->pstate.current_pstate) {
2181 cpu->pstate.current_pstate = target_pstate;
2182 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2183 pstate_funcs.get_val(cpu, target_pstate));
2184 }
64078299 2185 freqs.new = target_pstate * cpu->pstate.scaling;
50e9ffab 2186 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
001c76f0
RW		 2187 cpufreq_freq_transition_end(policy, &freqs, false);
2188
2189 return 0;
2190}
2191
2192static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2193 unsigned int target_freq)
2194{
2195 struct cpudata *cpu = all_cpu_data[policy->cpu];
50e9ffab 2196 int target_pstate, old_pstate;
001c76f0 2197
64897b20
RW		 2198 update_turbo_state();
2199
001c76f0 2200 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
64078299 2201 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
50e9ffab 2202 old_pstate = cpu->pstate.current_pstate;
001c76f0 2203 intel_pstate_update_pstate(cpu, target_pstate);
50e9ffab 2204 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
64078299 2205 return target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2206}
2207
2208static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2209{
2210 int ret = __intel_pstate_cpu_init(policy);
2211
2212 if (ret)
2213 return ret;
2214
2215 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
1b72e7fd 2216 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
001c76f0
RW		 2217 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2218 policy->cur = policy->cpuinfo.min_freq;
2219
2220 return 0;
2221}
2222
2223static struct cpufreq_driver intel_cpufreq = {
2224 .flags = CPUFREQ_CONST_LOOPS,
2225 .verify = intel_cpufreq_verify_policy,
2226 .target = intel_cpufreq_target,
2227 .fast_switch = intel_cpufreq_fast_switch,
2228 .init = intel_cpufreq_cpu_init,
2229 .exit = intel_pstate_cpu_exit,
2230 .stop_cpu = intel_cpufreq_stop_cpu,
2231 .name = "intel_cpufreq",
2232};
2233
ee8df89a 2234static struct cpufreq_driver *default_driver = &intel_pstate;
001c76f0 2235
fb1fe104
RW		 2236static void intel_pstate_driver_cleanup(void)
2237{
2238 unsigned int cpu;
2239
2240 get_online_cpus();
2241 for_each_online_cpu(cpu) {
2242 if (all_cpu_data[cpu]) {
2243 if (intel_pstate_driver == &intel_pstate)
2244 intel_pstate_clear_update_util_hook(cpu);
2245
2246 kfree(all_cpu_data[cpu]);
2247 all_cpu_data[cpu] = NULL;
2248 }
2249 }
2250 put_online_cpus();
ee8df89a 2251 intel_pstate_driver = NULL;
fb1fe104
RW		 2252}
2253
ee8df89a 2254static int intel_pstate_register_driver(struct cpufreq_driver *driver)
fb1fe104
RW		 2255{
2256 int ret;
2257
c5a2ee7d
RW		 2258 memset(&global, 0, sizeof(global));
2259 global.max_perf_pct = 100;
c3a49c89 2260
ee8df89a 2261 intel_pstate_driver = driver;
fb1fe104
RW		 2262 ret = cpufreq_register_driver(intel_pstate_driver);
2263 if (ret) {
2264 intel_pstate_driver_cleanup();
2265 return ret;
2266 }
2267
c5a2ee7d
RW		 2268 global.min_perf_pct = min_perf_pct_min();
2269
fb1fe104
RW		 2270 return 0;
2271}
2272
2273static int intel_pstate_unregister_driver(void)
2274{
2275 if (hwp_active)
2276 return -EBUSY;
2277
fb1fe104
RW		 2278 cpufreq_unregister_driver(intel_pstate_driver);
2279 intel_pstate_driver_cleanup();
2280
2281 return 0;
2282}
2283
2284static ssize_t intel_pstate_show_status(char *buf)
2285{
ee8df89a 2286 if (!intel_pstate_driver)
fb1fe104
RW		 2287 return sprintf(buf, "off\n");
2288
2289 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2290 "active" : "passive");
2291}
2292
2293static int intel_pstate_update_status(const char *buf, size_t size)
2294{
2295 int ret;
2296
2297 if (size == 3 && !strncmp(buf, "off", size))
ee8df89a 2298 return intel_pstate_driver ?
fb1fe104
RW		 2299 intel_pstate_unregister_driver() : -EINVAL;
2300
2301 if (size == 6 && !strncmp(buf, "active", size)) {
ee8df89a 2302 if (intel_pstate_driver) {
fb1fe104
RW		 2303 if (intel_pstate_driver == &intel_pstate)
2304 return 0;
2305
2306 ret = intel_pstate_unregister_driver();
2307 if (ret)
2308 return ret;
2309 }
2310
ee8df89a 2311 return intel_pstate_register_driver(&intel_pstate);
fb1fe104
RW		 2312 }
2313
2314 if (size == 7 && !strncmp(buf, "passive", size)) {
ee8df89a 2315 if (intel_pstate_driver) {
0042b2c0 2316 if (intel_pstate_driver == &intel_cpufreq)
fb1fe104
RW		 2317 return 0;
2318
2319 ret = intel_pstate_unregister_driver();
2320 if (ret)
2321 return ret;
2322 }
2323
ee8df89a 2324 return intel_pstate_register_driver(&intel_cpufreq);
fb1fe104
RW		 2325 }
2326
2327 return -EINVAL;
2328}
2329
eed43609
JZ		 2330static int no_load __initdata;
2331static int no_hwp __initdata;
2332static int hwp_only __initdata;
29327c84 2333static unsigned int force_load __initdata;
6be26498 2334
29327c84 2335static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2336{
016c8150 2337 if (!pstate_funcs.get_max() ||
c410833a
SK		 2338 !pstate_funcs.get_min() ||
2339 !pstate_funcs.get_turbo())
b563b4e3
DB		 2340 return -ENODEV;
2341
b563b4e3
DB		 2342 return 0;
2343}
016c8150 2344
29327c84 2345static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2346{
2347 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2348 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2349 pstate_funcs.get_min = funcs->get_min;
2350 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2351 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2352 pstate_funcs.get_val = funcs->get_val;
007bea09 2353 pstate_funcs.get_vid = funcs->get_vid;
6e34e1f2 2354 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
016c8150
DB		 2355}
2356
9522a2ff 2357#ifdef CONFIG_ACPI
fbbcdc07 2358
29327c84 2359static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2360{
2361 int i;
2362
2363 for_each_possible_cpu(i) {
2364 acpi_status status;
2365 union acpi_object *pss;
2366 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2367 struct acpi_processor *pr = per_cpu(processors, i);
2368
2369 if (!pr)
2370 continue;
2371
2372 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2373 if (ACPI_FAILURE(status))
2374 continue;
2375
2376 pss = buffer.pointer;
2377 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2378 kfree(pss);
2379 return false;
2380 }
2381
2382 kfree(pss);
2383 }
2384
2385 return true;
2386}
2387
29327c84 2388static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2389{
2390 int i;
2391
2392 for_each_possible_cpu(i) {
2393 struct acpi_processor *pr = per_cpu(processors, i);
2394
2395 if (!pr)
2396 continue;
2397 if (acpi_has_method(pr->handle, "_PPC"))
2398 return true;
2399 }
2400 return false;
2401}
2402
2403enum {
2404 PSS,
2405 PPC,
2406};
2407
fbbcdc07 2408/* Hardware vendor-specific info that has its own power management modes */
5e932321
TK		 2409static struct acpi_platform_list plat_info[] __initdata = {
2410 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2411 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2412 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2413 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2414 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2415 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2416 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2417 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2418 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2419 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2420 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2421 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2422 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2423 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2424 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2425 { } /* End */
fbbcdc07
AH		 2426};
2427
29327c84 2428static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07 2429{
2f86dc4c
DB		 2430 const struct x86_cpu_id *id;
2431 u64 misc_pwr;
5e932321 2432 int idx;
2f86dc4c
DB		 2433
2434 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2435 if (id) {
2436 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2437 if ( misc_pwr & (1 << 8))
2438 return true;
2439 }
fbbcdc07 2440
5e932321
TK		 2441 idx = acpi_match_platform_list(plat_info);
2442 if (idx < 0)
fbbcdc07
AH		 2443 return false;
2444
5e932321
TK		 2445 switch (plat_info[idx].data) {
2446 case PSS:
2447 return intel_pstate_no_acpi_pss();
2448 case PPC:
2449 return intel_pstate_has_acpi_ppc() && !force_load;
fbbcdc07
AH		 2450 }
2451
2452 return false;
2453}
d0ea59e1
RW		 2454
2455static void intel_pstate_request_control_from_smm(void)
2456{
2457 /*
2458 * It may be unsafe to request P-states control from SMM if _PPC support
2459 * has not been enabled.
2460 */
2461 if (acpi_ppc)
2462 acpi_processor_pstate_control();
2463}
fbbcdc07
AH		 2464#else /* CONFIG_ACPI not enabled */
2465static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2466static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2467static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2468#endif /* CONFIG_ACPI */
2469
7791e4aa
SP		 2470static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2471 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2472 {}
2473};
2474
93f0822d
DB		 2475static int __init intel_pstate_init(void)
2476{
eb5139d1 2477 int rc;
93f0822d 2478
6be26498
DB		 2479 if (no_load)
2480 return -ENODEV;
2481
eb5139d1 2482 if (x86_match_cpu(hwp_support_ids)) {
2f49afc2 2483 copy_cpu_funcs(&core_funcs);
c4f3f70c 2484 if (!no_hwp) {
eb5139d1
RW		 2485 hwp_active++;
2486 intel_pstate.attr = hwp_cpufreq_attrs;
2487 goto hwp_cpu_matched;
2488 }
2489 } else {
2490 const struct x86_cpu_id *id;
7791e4aa 2491
eb5139d1
RW		 2492 id = x86_match_cpu(intel_pstate_cpu_ids);
2493 if (!id)
2494 return -ENODEV;
93f0822d 2495
2f49afc2 2496 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
eb5139d1 2497 }
016c8150 2498
b563b4e3
DB		 2499 if (intel_pstate_msrs_not_valid())
2500 return -ENODEV;
2501
7791e4aa
SP		 2502hwp_cpu_matched:
2503 /*
2504 * The Intel pstate driver will be ignored if the platform
2505 * firmware has its own power management modes.
2506 */
2507 if (intel_pstate_platform_pwr_mgmt_exists())
2508 return -ENODEV;
2509
fb1fe104
RW		 2510 if (!hwp_active && hwp_only)
2511 return -ENOTSUPP;
2512
4836df17 2513 pr_info("Intel P-state driver initializing\n");
93f0822d 2514
fad953ce 2515 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
93f0822d
DB		 2516 if (!all_cpu_data)
2517 return -ENOMEM;
93f0822d 2518
d0ea59e1
RW		 2519 intel_pstate_request_control_from_smm();
2520
93f0822d 2521 intel_pstate_sysfs_expose_params();
b69880f9 2522
0c30b65b 2523 mutex_lock(&intel_pstate_driver_lock);
ee8df89a 2524 rc = intel_pstate_register_driver(default_driver);
0c30b65b 2525 mutex_unlock(&intel_pstate_driver_lock);
fb1fe104
RW		 2526 if (rc)
2527 return rc;
366430b5 2528
7791e4aa 2529 if (hwp_active)
4836df17 2530 pr_info("HWP enabled\n");
7791e4aa 2531
fb1fe104 2532 return 0;
93f0822d
DB		 2533}
2534device_initcall(intel_pstate_init);
2535
6be26498
DB		 2536static int __init intel_pstate_setup(char *str)
2537{
2538 if (!str)
2539 return -EINVAL;
2540
001c76f0 2541 if (!strcmp(str, "disable")) {
6be26498 2542 no_load = 1;
001c76f0
RW		 2543 } else if (!strcmp(str, "passive")) {
2544 pr_info("Passive mode enabled\n");
ee8df89a 2545 default_driver = &intel_cpufreq;
001c76f0
RW		 2546 no_hwp = 1;
2547 }
539342f6 2548 if (!strcmp(str, "no_hwp")) {
4836df17 2549 pr_info("HWP disabled\n");
2f86dc4c 2550 no_hwp = 1;
539342f6 2551 }
aa4ea34d
EZ		 2552 if (!strcmp(str, "force"))
2553 force_load = 1;
d64c3b0b
KCA		 2554 if (!strcmp(str, "hwp_only"))
2555 hwp_only = 1;
eae48f04
SP		 2556 if (!strcmp(str, "per_cpu_perf_limits"))
2557 per_cpu_limits = true;
9522a2ff
SP		 2558
2559#ifdef CONFIG_ACPI
2560 if (!strcmp(str, "support_acpi_ppc"))
2561 acpi_ppc = true;
2562#endif
2563
6be26498
DB		 2564 return 0;
2565}
2566early_param("intel_pstate", intel_pstate_setup);
2567
93f0822d
DB		 2568MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2569MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2570MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)