[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

static struct clk *arm_clk;
static struct clk *pll1_sys_clk;
static struct clk *pll1_sw_clk;
static struct clk *step_clk;
static struct clk *pll2_pfd2_396m_clk;

/* clk used by i.MX6UL */
static struct clk *pll2_bus_clk;
static struct clk *secondary_sel_clk;

static struct device *cpu_dev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	bool pll1_sys_temp_enabled = false;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(arm_clk) / 1000;

	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	 * flow is slightly different from other i.MX6 OSC.
	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
		else
			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
		clk_set_parent(step_clk, secondary_sel_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
	} else {
		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
			clk_set_rate(pll1_sys_clk, new_freq * 1000);
			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(pll1_sys_clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, new_freq * 1000);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		regulator_set_voltage_tol(arm_reg, volt_old, 0);
		return ret;
	}

	/* PLL1 is only needed until after ARM-PODF is set. */
	if (pll1_sys_temp_enabled)
		clk_disable_unprepare(pll1_sys_clk);

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
			ret = 0;
		}
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
				ret = 0;
			}
		}
	}

	return 0;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->clk = arm_clk;
	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	policy->suspend_freq = policy->max;

	return ret;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
	.suspend = cpufreq_generic_suspend,
};

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3
#define OCOTP_CFG3_SPEED_996MHZ		0x2
#define OCOTP_CFG3_SPEED_852MHZ		0x1

static void imx6q_opp_check_speed_grading(struct device *dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np)
		return;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(dev, "failed to map ocotp\n");
		goto put_node;
	}

	/*
	 * SPEED_GRADING[1:0] defines the max speed of ARM:
	 * 2b'11: 1200000000Hz;
	 * 2b'10: 996000000Hz;
	 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	 * 2b'00: 792000000Hz;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if ((val != OCOTP_CFG3_SPEED_1P2GHZ) &&
	     of_machine_is_compatible("fsl,imx6q"))
		if (dev_pm_opp_disable(dev, 1200000000))
			dev_warn(dev, "failed to disable 1.2GHz OPP\n");
	if (val < OCOTP_CFG3_SPEED_996MHZ)
		if (dev_pm_opp_disable(dev, 996000000))
			dev_warn(dev, "failed to disable 996MHz OPP\n");
	if (of_machine_is_compatible("fsl,imx6q")) {
		if (val != OCOTP_CFG3_SPEED_852MHZ)
			if (dev_pm_opp_disable(dev, 852000000))
				dev_warn(dev, "failed to disable 852MHz OPP\n");
	}
	iounmap(base);
put_node:
	of_node_put(np);
}

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	arm_clk = clk_get(cpu_dev, "arm");
	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	step_clk = clk_get(cpu_dev, "step");
	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
		dev_err(cpu_dev, "failed to get clocks\n");
		ret = -ENOENT;
		goto put_clk;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
		secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
		if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
			dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
			ret = -ENOENT;
			goto put_clk;
		}
	}

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		dev_dbg(cpu_dev, "regulators not ready, defer\n");
		goto put_reg;
	}
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	ret = dev_pm_opp_of_add_table(cpu_dev);
	if (ret < 0) {
		dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
		goto put_reg;
	}

	imx6q_opp_check_speed_grading(cpu_dev);

	/* Because we have added the OPPs here, we must free them */
	free_opp = true;
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = num;
		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
		goto out_free_opp;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_free_opp;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[--num].frequency * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_opp:
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);
put_clk:
	if (!IS_ERR(arm_clk))
		clk_put(arm_clk);
	if (!IS_ERR(pll1_sys_clk))
		clk_put(pll1_sys_clk);
	if (!IS_ERR(pll1_sw_clk))
		clk_put(pll1_sw_clk);
	if (!IS_ERR(step_clk))
		clk_put(step_clk);
	if (!IS_ERR(pll2_pfd2_396m_clk))
		clk_put(pll2_pfd2_396m_clk);
	if (!IS_ERR(pll2_bus_clk))
		clk_put(pll2_bus_clk);
	if (!IS_ERR(secondary_sel_clk))
		clk_put(secondary_sel_clk);
	of_node_put(np);
	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);
	clk_put(arm_clk);
	clk_put(pll1_sys_clk);
	clk_put(pll1_sw_clk);
	clk_put(step_clk);
	clk_put(pll2_pfd2_396m_clk);
	clk_put(pll2_bus_clk);
	clk_put(secondary_sel_clk);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0	11	#include <linux/cpufreq.h>
1dd538f0 SG	12	#include <linux/err.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
2b3d58a3	15	#include <linux/of_address.h>
e4db1c74	16	#include <linux/pm_opp.h>
1dd538f0 SG	17	#include <linux/platform_device.h>
	18	#include <linux/regulator/consumer.h>
	19
	20	#define PU_SOC_VOLTAGE_NORMAL 1250000
	21	#define PU_SOC_VOLTAGE_HIGH 1275000
	22	#define FREQ_1P2_GHZ 1200000000
	23
	24	static struct regulator *arm_reg;
	25	static struct regulator *pu_reg;
	26	static struct regulator *soc_reg;
	27
	28	static struct clk *arm_clk;
	29	static struct clk *pll1_sys_clk;
	30	static struct clk *pll1_sw_clk;
	31	static struct clk *step_clk;
	32	static struct clk *pll2_pfd2_396m_clk;
	33
a35fc5a3 BP	34	/* clk used by i.MX6UL */
	35	static struct clk *pll2_bus_clk;
	36	static struct clk *secondary_sel_clk;
	37
1dd538f0	38	static struct device *cpu_dev;
cc87b8a8	39	static bool free_opp;
1dd538f0 SG	40	static struct cpufreq_frequency_table *freq_table;
	41	static unsigned int transition_latency;
	42
b4573d1d AH	43	static u32 *imx6_soc_volt;
	44	static u32 soc_opp_count;
	45
9c0ebcf7	46	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	47	{
47d43ba7	48	struct dev_pm_opp *opp;
1dd538f0	49	unsigned long freq_hz, volt, volt_old;
d4019f0a	50	unsigned int old_freq, new_freq;
fded5fc8	51	bool pll1_sys_temp_enabled = false;
1dd538f0 SG	52	int ret;
1dd538f0 SG	53
d4019f0a VK	54	new_freq = freq_table[index].frequency;
	55	freq_hz = new_freq * 1000;
	56	old_freq = clk_get_rate(arm_clk) / 1000;
1dd538f0	57
5d4879cd	58	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0	59	if (IS_ERR(opp)) {
1dd538f0 SG	60	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	61	return PTR_ERR(opp);
	62	}
	63
5d4879cd	64	volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	65	dev_pm_opp_put(opp);
8a31d9d9 VK	66
1dd538f0 SG	67	volt_old = regulator_get_voltage(arm_reg);
	68
	69	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	70	old_freq / 1000, volt_old / 1000,
d4019f0a VK	71	new_freq / 1000, volt / 1000);
5a571c35	72
1dd538f0	73	/* scaling up? scale voltage before frequency */
d4019f0a	74	if (new_freq > old_freq) {
22d0628a AH	75	if (!IS_ERR(pu_reg)) {
	76	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	77	if (ret) {
	78	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	79	return ret;
	80	}
b4573d1d AH	81	}
	82	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	83	if (ret) {
	84	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	85	return ret;
	86	}
1dd538f0 SG	87	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	88	if (ret) {
	89	dev_err(cpu_dev,
	90	"failed to scale vddarm up: %d\n", ret);
d4019f0a	91	return ret;
1dd538f0	92	}
1dd538f0 SG	93	}
	94
	95	/*
	96	* The setpoints are selected per PLL/PDF frequencies, so we need to
	97	* reprogram PLL for frequency scaling. The procedure of reprogramming
	98	* PLL1 is as below.
a35fc5a3 BP	99	* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	100	* flow is slightly different from other i.MX6 OSC.
	101	* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
1dd538f0 SG	102	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	103	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	104	* - Disable pll2_pfd2_396m_clk
	105	*/
3fafb4e7 OP	106	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	107	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	108	/*
	109	* When changing pll1_sw_clk's parent to pll1_sys_clk,
	110	* CPU may run at higher than 528MHz, this will lead to
	111	* the system unstable if the voltage is lower than the
	112	* voltage of 528MHz, so lower the CPU frequency to one
	113	* half before changing CPU frequency.
	114	*/
	115	clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
1dd538f0	116	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
a35fc5a3 BP	117	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
	118	clk_set_parent(secondary_sel_clk, pll2_bus_clk);
	119	else
	120	clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
	121	clk_set_parent(step_clk, secondary_sel_clk);
	122	clk_set_parent(pll1_sw_clk, step_clk);
	123	} else {
	124	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	125	clk_set_parent(pll1_sw_clk, step_clk);
	126	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
	127	clk_set_rate(pll1_sys_clk, new_freq * 1000);
	128	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
fded5fc8 LC	129	} else {
	130	/* pll1_sys needs to be enabled for divider rate change to work. */
	131	pll1_sys_temp_enabled = true;
	132	clk_prepare_enable(pll1_sys_clk);
a35fc5a3	133	}
1dd538f0 SG	134	}
	135
	136	/* Ensure the arm clock divider is what we expect */
d4019f0a	137	ret = clk_set_rate(arm_clk, new_freq * 1000);
1dd538f0 SG	138	if (ret) {
	139	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
	140	regulator_set_voltage_tol(arm_reg, volt_old, 0);
d4019f0a	141	return ret;
1dd538f0 SG	142	}
1dd538f0 SG	143
fded5fc8 LC	144	/* PLL1 is only needed until after ARM-PODF is set. */
	145	if (pll1_sys_temp_enabled)
	146	clk_disable_unprepare(pll1_sys_clk);
	147
1dd538f0	148	/* scaling down? scale voltage after frequency */
d4019f0a	149	if (new_freq < old_freq) {
1dd538f0	150	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	151	if (ret) {
1dd538f0 SG	152	dev_warn(cpu_dev,
1dd538f0 SG	153	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	154	ret = 0;
5a571c35 VK	155	}
b4573d1d AH	156	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	157	if (ret) {
	158	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
	159	ret = 0;
	160	}
22d0628a AH	161	if (!IS_ERR(pu_reg)) {
	162	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	163	if (ret) {
	164	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
	165	ret = 0;
	166	}
1dd538f0 SG	167	}
	168	}
	169
d4019f0a	170	return 0;
1dd538f0 SG	171	}
	172
	173	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	174	{
5aa1599f LC	175	int ret;
5aa1599f LC	176
652ed95d	177	policy->clk = arm_clk;
5aa1599f LC	178	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	179	policy->suspend_freq = policy->max;
	180
	181	return ret;
1dd538f0 SG	182	}
1dd538f0 SG	183
1dd538f0	184	static struct cpufreq_driver imx6q_cpufreq_driver = {
ae6b4271	185	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
4f6ba385	186	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	187	.target_index = imx6q_set_target,
652ed95d	188	.get = cpufreq_generic_get,
1dd538f0	189	.init = imx6q_cpufreq_init,
1dd538f0	190	.name = "imx6q-cpufreq",
4f6ba385	191	.attr = cpufreq_generic_attr,
5aa1599f	192	.suspend = cpufreq_generic_suspend,
1dd538f0 SG	193	};
1dd538f0 SG	194
2b3d58a3 FE	195	#define OCOTP_CFG3 0x440
	196	#define OCOTP_CFG3_SPEED_SHIFT 16
	197	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	198	#define OCOTP_CFG3_SPEED_996MHZ 0x2
	199	#define OCOTP_CFG3_SPEED_852MHZ 0x1
	200
	201	static void imx6q_opp_check_speed_grading(struct device *dev)
	202	{
	203	struct device_node *np;
	204	void __iomem *base;
	205	u32 val;
	206
	207	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	208	if (!np)
	209	return;
	210
	211	base = of_iomap(np, 0);
	212	if (!base) {
	213	dev_err(dev, "failed to map ocotp\n");
	214	goto put_node;
	215	}
	216
	217	/*
	218	* SPEED_GRADING[1:0] defines the max speed of ARM:
	219	* 2b'11: 1200000000Hz;
	220	* 2b'10: 996000000Hz;
	221	* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	222	* 2b'00: 792000000Hz;
	223	* We need to set the max speed of ARM according to fuse map.
	224	*/
	225	val = readl_relaxed(base + OCOTP_CFG3);
	226	val >>= OCOTP_CFG3_SPEED_SHIFT;
	227	val &= 0x3;
	228
	229	if ((val != OCOTP_CFG3_SPEED_1P2GHZ) &&
	230	of_machine_is_compatible("fsl,imx6q"))
	231	if (dev_pm_opp_disable(dev, 1200000000))
	232	dev_warn(dev, "failed to disable 1.2GHz OPP\n");
	233	if (val < OCOTP_CFG3_SPEED_996MHZ)
	234	if (dev_pm_opp_disable(dev, 996000000))
	235	dev_warn(dev, "failed to disable 996MHz OPP\n");
	236	if (of_machine_is_compatible("fsl,imx6q")) {
	237	if (val != OCOTP_CFG3_SPEED_852MHZ)
	238	if (dev_pm_opp_disable(dev, 852000000))
	239	dev_warn(dev, "failed to disable 852MHz OPP\n");
	240	}
	241	iounmap(base);
	242	put_node:
	243	of_node_put(np);
	244	}
	245
1dd538f0 SG	246	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	247	{
	248	struct device_node *np;
47d43ba7	249	struct dev_pm_opp *opp;
1dd538f0 SG	250	unsigned long min_volt, max_volt;
1dd538f0 SG	251	int num, ret;
b4573d1d AH	252	const struct property *prop;
	253	const __be32 *val;
	254	u32 nr, i, j;
1dd538f0	255
b494b48d SK	256	cpu_dev = get_cpu_device(0);
	257	if (!cpu_dev) {
	258	pr_err("failed to get cpu0 device\n");
	259	return -ENODEV;
	260	}
1dd538f0	261
cdc58d60	262	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	263	if (!np) {
	264	dev_err(cpu_dev, "failed to find cpu0 node\n");
	265	return -ENOENT;
	266	}
	267
f8269c19 PZ	268	arm_clk = clk_get(cpu_dev, "arm");
	269	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	270	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	271	step_clk = clk_get(cpu_dev, "step");
	272	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
1dd538f0 SG	273	if (IS_ERR(arm_clk) \|\| IS_ERR(pll1_sys_clk) \|\| IS_ERR(pll1_sw_clk) \|\|
	274	IS_ERR(step_clk) \|\| IS_ERR(pll2_pfd2_396m_clk)) {
	275	dev_err(cpu_dev, "failed to get clocks\n");
	276	ret = -ENOENT;
f8269c19	277	goto put_clk;
1dd538f0 SG	278	}
1dd538f0 SG	279
3fafb4e7 OP	280	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	281	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	282	pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
	283	secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
	284	if (IS_ERR(pll2_bus_clk) \|\| IS_ERR(secondary_sel_clk)) {
	285	dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
	286	ret = -ENOENT;
	287	goto put_clk;
	288	}
	289	}
	290
f8269c19	291	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	292	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	293	soc_reg = regulator_get(cpu_dev, "soc");
54cad2fc IT	294	if (PTR_ERR(arm_reg) == -EPROBE_DEFER \|\|
	295	PTR_ERR(soc_reg) == -EPROBE_DEFER \|\|
	296	PTR_ERR(pu_reg) == -EPROBE_DEFER) {
	297	ret = -EPROBE_DEFER;
	298	dev_dbg(cpu_dev, "regulators not ready, defer\n");
	299	goto put_reg;
	300	}
22d0628a	301	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	302	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	303	ret = -ENOENT;
f8269c19	304	goto put_reg;
1dd538f0 SG	305	}
1dd538f0 SG	306
2b3d58a3 FE	307	ret = dev_pm_opp_of_add_table(cpu_dev);
	308	if (ret < 0) {
	309	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
	310	goto put_reg;
	311	}
20b7cbe2	312
2b3d58a3	313	imx6q_opp_check_speed_grading(cpu_dev);
cc87b8a8	314
2b3d58a3 FE	315	/* Because we have added the OPPs here, we must free them */
	316	free_opp = true;
	317	num = dev_pm_opp_get_opp_count(cpu_dev);
	318	if (num < 0) {
	319	ret = num;
	320	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
	321	goto out_free_opp;
1dd538f0 SG	322	}
1dd538f0 SG	323
5d4879cd	324	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	325	if (ret) {
1dd538f0 SG	326	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
eafca851	327	goto out_free_opp;
1dd538f0 SG	328	}
1dd538f0 SG	329
b4573d1d AH	330	/* Make imx6_soc_volt array's size same as arm opp number */
	331	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(imx6_soc_volt) num, GFP_KERNEL);
	332	if (imx6_soc_volt == NULL) {
	333	ret = -ENOMEM;
	334	goto free_freq_table;
	335	}
	336
	337	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	338	if (!prop \|\| !prop->value)
	339	goto soc_opp_out;
	340
	341	/*
	342	* Each OPP is a set of tuples consisting of frequency and
	343	* voltage like <freq-kHz vol-uV>.
	344	*/
	345	nr = prop->length / sizeof(u32);
	346	if (nr % 2 \|\| (nr / 2) < num)
	347	goto soc_opp_out;
	348
	349	for (j = 0; j < num; j++) {
	350	val = prop->value;
	351	for (i = 0; i < nr / 2; i++) {
	352	unsigned long freq = be32_to_cpup(val++);
	353	unsigned long volt = be32_to_cpup(val++);
	354	if (freq_table[j].frequency == freq) {
	355	imx6_soc_volt[soc_opp_count++] = volt;
	356	break;
	357	}
	358	}
	359	}
	360
	361	soc_opp_out:
	362	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	363	if (soc_opp_count != num) {
	364	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	365	for (j = 0; j < num; j++)
	366	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	367	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	368	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	369	}
	370
1dd538f0 SG	371	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	372	transition_latency = CPUFREQ_ETERNAL;
	373
b4573d1d AH	374	/*
	375	* Calculate the ramp time for max voltage change in the
	376	* VDDSOC and VDDPU regulators.
	377	*/
	378	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	379	if (ret > 0)
	380	transition_latency += ret * 1000;
22d0628a AH	381	if (!IS_ERR(pu_reg)) {
	382	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	383	if (ret > 0)
	384	transition_latency += ret * 1000;
	385	}
b4573d1d	386
1dd538f0 SG	387	/*
	388	* OPP is maintained in order of increasing frequency, and
	389	* freq_table initialised from OPP is therefore sorted in the
	390	* same order.
	391	*/
5d4879cd	392	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	393	freq_table[0].frequency * 1000, true);
5d4879cd	394	min_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	395	dev_pm_opp_put(opp);
5d4879cd	396	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	397	freq_table[--num].frequency * 1000, true);
5d4879cd	398	max_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	399	dev_pm_opp_put(opp);
8a31d9d9 VK	400
1dd538f0 SG	401	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	402	if (ret > 0)
	403	transition_latency += ret * 1000;
	404
1dd538f0 SG	405	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	406	if (ret) {
	407	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	408	goto free_freq_table;
	409	}
	410
	411	of_node_put(np);
	412	return 0;
	413
	414	free_freq_table:
5d4879cd	415	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8 VK	416	out_free_opp:
cc87b8a8 VK	417	if (free_opp)
8f8d37b2	418	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19 PZ	419	put_reg:
	420	if (!IS_ERR(arm_reg))
	421	regulator_put(arm_reg);
	422	if (!IS_ERR(pu_reg))
	423	regulator_put(pu_reg);
	424	if (!IS_ERR(soc_reg))
	425	regulator_put(soc_reg);
	426	put_clk:
	427	if (!IS_ERR(arm_clk))
	428	clk_put(arm_clk);
	429	if (!IS_ERR(pll1_sys_clk))
	430	clk_put(pll1_sys_clk);
	431	if (!IS_ERR(pll1_sw_clk))
	432	clk_put(pll1_sw_clk);
	433	if (!IS_ERR(step_clk))
	434	clk_put(step_clk);
	435	if (!IS_ERR(pll2_pfd2_396m_clk))
	436	clk_put(pll2_pfd2_396m_clk);
a35fc5a3 BP	437	if (!IS_ERR(pll2_bus_clk))
	438	clk_put(pll2_bus_clk);
	439	if (!IS_ERR(secondary_sel_clk))
	440	clk_put(secondary_sel_clk);
1dd538f0 SG	441	of_node_put(np);
	442	return ret;
	443	}
	444
	445	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	446	{
	447	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	448	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8	449	if (free_opp)
8f8d37b2	450	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19	451	regulator_put(arm_reg);
22d0628a AH	452	if (!IS_ERR(pu_reg))
22d0628a AH	453	regulator_put(pu_reg);
f8269c19 PZ	454	regulator_put(soc_reg);
	455	clk_put(arm_clk);
	456	clk_put(pll1_sys_clk);
	457	clk_put(pll1_sw_clk);
	458	clk_put(step_clk);
	459	clk_put(pll2_pfd2_396m_clk);
a35fc5a3 BP	460	clk_put(pll2_bus_clk);
a35fc5a3 BP	461	clk_put(secondary_sel_clk);
1dd538f0 SG	462
	463	return 0;
	464	}
	465
	466	static struct platform_driver imx6q_cpufreq_platdrv = {
	467	.driver = {
	468	.name = "imx6q-cpufreq",
1dd538f0 SG	469	},
	470	.probe = imx6q_cpufreq_probe,
	471	.remove = imx6q_cpufreq_remove,
	472	};
	473	module_platform_driver(imx6q_cpufreq_platdrv);
	474
	475	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	476	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	477	MODULE_LICENSE("GPL");