[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpu_cooling.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

enum IMX6_CPUFREQ_CLKS {
	ARM,
	PLL1_SYS,
	STEP,
	PLL1_SW,
	PLL2_PFD2_396M,
	/* MX6UL requires two more clks */
	PLL2_BUS,
	SECONDARY_SEL,
};
#define IMX6Q_CPUFREQ_CLK_NUM		5
#define IMX6UL_CPUFREQ_CLK_NUM		7

static int num_clks;
static struct clk_bulk_data clks[] = {
	{ .id = "arm" },
	{ .id = "pll1_sys" },
	{ .id = "step" },
	{ .id = "pll1_sw" },
	{ .id = "pll2_pfd2_396m" },
	{ .id = "pll2_bus" },
	{ .id = "secondary_sel" },
};

static struct device *cpu_dev;
static struct thermal_cooling_device *cdev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int max_freq;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	bool pll1_sys_temp_enabled = false;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(clks[ARM].clk) / 1000;

	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	 * flow is slightly different from other i.MX6 OSC.
	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
		clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_BUS].clk);
		else
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		}
	} else {
		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(clks[PLL1_SYS].clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
	if (ret) {
		int ret1;

		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
		if (ret1)
			dev_warn(cpu_dev,
				 "failed to restore vddarm voltage: %d\n", ret1);
		return ret;
	}

	/* PLL1 is only needed until after ARM-PODF is set. */
	if (pll1_sys_temp_enabled)
		clk_disable_unprepare(clks[PLL1_SYS].clk);

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
			ret = 0;
		}
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
				ret = 0;
			}
		}
	}

	return 0;
}

static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
{
	cdev = of_cpufreq_cooling_register(policy);

	if (!cdev)
		dev_err(cpu_dev,
			"running cpufreq without cooling device: %ld\n",
			PTR_ERR(cdev));
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->clk = clks[ARM].clk;
	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	policy->suspend_freq = max_freq;

	return ret;
}

static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
{
	cpufreq_cooling_unregister(cdev);

	return 0;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.exit = imx6q_cpufreq_exit,
	.name = "imx6q-cpufreq",
	.ready = imx6q_cpufreq_ready,
	.attr = cpufreq_generic_attr,
	.suspend = cpufreq_generic_suspend,
};

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3
#define OCOTP_CFG3_SPEED_996MHZ		0x2
#define OCOTP_CFG3_SPEED_852MHZ		0x1

static void imx6q_opp_check_speed_grading(struct device *dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np)
		return;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(dev, "failed to map ocotp\n");
		goto put_node;
	}

	/*
	 * SPEED_GRADING[1:0] defines the max speed of ARM:
	 * 2b'11: 1200000000Hz;
	 * 2b'10: 996000000Hz;
	 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	 * 2b'00: 792000000Hz;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (val < OCOTP_CFG3_SPEED_996MHZ)
		if (dev_pm_opp_disable(dev, 996000000))
			dev_warn(dev, "failed to disable 996MHz OPP\n");

	if (of_machine_is_compatible("fsl,imx6q") ||
	    of_machine_is_compatible("fsl,imx6qp")) {
		if (val != OCOTP_CFG3_SPEED_852MHZ)
			if (dev_pm_opp_disable(dev, 852000000))
				dev_warn(dev, "failed to disable 852MHz OPP\n");
		if (val != OCOTP_CFG3_SPEED_1P2GHZ)
			if (dev_pm_opp_disable(dev, 1200000000))
				dev_warn(dev, "failed to disable 1.2GHz OPP\n");
	}
	iounmap(base);
put_node:
	of_node_put(np);
}

#define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2
#define OCOTP_CFG3_6ULL_SPEED_792MHZ	0x2
#define OCOTP_CFG3_6ULL_SPEED_900MHZ	0x3

static int imx6ul_opp_check_speed_grading(struct device *dev)
{
	u32 val;
	int ret = 0;

	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
		if (ret)
			return ret;
	} else {
		struct device_node *np;
		void __iomem *base;

		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
		if (!np)
			return -ENOENT;

		base = of_iomap(np, 0);
		of_node_put(np);
		if (!base) {
			dev_err(dev, "failed to map ocotp\n");
			return -EFAULT;
		}

		val = readl_relaxed(base + OCOTP_CFG3);
		iounmap(base);
	}

	/*
	 * Speed GRADING[1:0] defines the max speed of ARM:
	 * 2b'00: Reserved;
	 * 2b'01: 528000000Hz;
	 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
	 * 2b'11: 900000000Hz on i.MX6ULL only;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (of_machine_is_compatible("fsl,imx6ul")) {
		if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
			if (dev_pm_opp_disable(dev, 696000000))
				dev_warn(dev, "failed to disable 696MHz OPP\n");
	}

	if (of_machine_is_compatible("fsl,imx6ull")) {
		if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
			if (dev_pm_opp_disable(dev, 792000000))
				dev_warn(dev, "failed to disable 792MHz OPP\n");

		if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
			if (dev_pm_opp_disable(dev, 900000000))
				dev_warn(dev, "failed to disable 900MHz OPP\n");
	}

	return ret;
}

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull"))
		num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	else
		num_clks = IMX6Q_CPUFREQ_CLK_NUM;

	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	if (ret)
		goto put_node;

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		dev_dbg(cpu_dev, "regulators not ready, defer\n");
		goto put_reg;
	}
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	ret = dev_pm_opp_of_add_table(cpu_dev);
	if (ret < 0) {
		dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
		goto put_reg;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		ret = imx6ul_opp_check_speed_grading(cpu_dev);
		if (ret == -EPROBE_DEFER)
			return ret;
		if (ret) {
			dev_err(cpu_dev, "failed to read ocotp: %d\n",
				ret);
			return ret;
		}
	} else {
		imx6q_opp_check_speed_grading(cpu_dev);
	}

	/* Because we have added the OPPs here, we must free them */
	free_opp = true;
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = num;
		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
		goto out_free_opp;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_free_opp;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
				     GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	max_freq = freq_table[--num].frequency;
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_opp:
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);
put_node:
	of_node_put(np);

	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_ALIAS("platform:imx6q-cpufreq");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0	11	#include <linux/cpufreq.h>
a1d00154	12	#include <linux/cpu_cooling.h>
1dd538f0 SG	13	#include <linux/err.h>
1dd538f0 SG	14	#include <linux/module.h>
2733fb0d	15	#include <linux/nvmem-consumer.h>
1dd538f0	16	#include <linux/of.h>
2b3d58a3	17	#include <linux/of_address.h>
e4db1c74	18	#include <linux/pm_opp.h>
1dd538f0 SG	19	#include <linux/platform_device.h>
	20	#include <linux/regulator/consumer.h>
	21
	22	#define PU_SOC_VOLTAGE_NORMAL 1250000
	23	#define PU_SOC_VOLTAGE_HIGH 1275000
	24	#define FREQ_1P2_GHZ 1200000000
	25
	26	static struct regulator *arm_reg;
	27	static struct regulator *pu_reg;
	28	static struct regulator *soc_reg;
	29
2332bd04 DA	30	enum IMX6_CPUFREQ_CLKS {
	31	ARM,
	32	PLL1_SYS,
	33	STEP,
	34	PLL1_SW,
	35	PLL2_PFD2_396M,
	36	/* MX6UL requires two more clks */
	37	PLL2_BUS,
	38	SECONDARY_SEL,
	39	};
	40	#define IMX6Q_CPUFREQ_CLK_NUM 5
	41	#define IMX6UL_CPUFREQ_CLK_NUM 7
	42
	43	static int num_clks;
	44	static struct clk_bulk_data clks[] = {
	45	{ .id = "arm" },
	46	{ .id = "pll1_sys" },
	47	{ .id = "step" },
	48	{ .id = "pll1_sw" },
	49	{ .id = "pll2_pfd2_396m" },
	50	{ .id = "pll2_bus" },
	51	{ .id = "secondary_sel" },
	52	};
a35fc5a3	53
1dd538f0	54	static struct device *cpu_dev;
a1d00154	55	static struct thermal_cooling_device *cdev;
cc87b8a8	56	static bool free_opp;
1dd538f0	57	static struct cpufreq_frequency_table *freq_table;
8d768cdc	58	static unsigned int max_freq;
1dd538f0 SG	59	static unsigned int transition_latency;
1dd538f0 SG	60
b4573d1d AH	61	static u32 *imx6_soc_volt;
	62	static u32 soc_opp_count;
	63
9c0ebcf7	64	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	65	{
47d43ba7	66	struct dev_pm_opp *opp;
1dd538f0	67	unsigned long freq_hz, volt, volt_old;
d4019f0a	68	unsigned int old_freq, new_freq;
fded5fc8	69	bool pll1_sys_temp_enabled = false;
1dd538f0 SG	70	int ret;
1dd538f0 SG	71
d4019f0a VK	72	new_freq = freq_table[index].frequency;
d4019f0a VK	73	freq_hz = new_freq * 1000;
2332bd04	74	old_freq = clk_get_rate(clks[ARM].clk) / 1000;
1dd538f0	75
5d4879cd	76	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0	77	if (IS_ERR(opp)) {
1dd538f0 SG	78	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	79	return PTR_ERR(opp);
	80	}
	81
5d4879cd	82	volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	83	dev_pm_opp_put(opp);
8a31d9d9 VK	84
1dd538f0 SG	85	volt_old = regulator_get_voltage(arm_reg);
	86
	87	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	88	old_freq / 1000, volt_old / 1000,
d4019f0a VK	89	new_freq / 1000, volt / 1000);
5a571c35	90
1dd538f0	91	/* scaling up? scale voltage before frequency */
d4019f0a	92	if (new_freq > old_freq) {
22d0628a AH	93	if (!IS_ERR(pu_reg)) {
	94	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	95	if (ret) {
	96	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	97	return ret;
	98	}
b4573d1d AH	99	}
	100	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	101	if (ret) {
	102	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	103	return ret;
	104	}
1dd538f0 SG	105	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	106	if (ret) {
	107	dev_err(cpu_dev,
	108	"failed to scale vddarm up: %d\n", ret);
d4019f0a	109	return ret;
1dd538f0	110	}
1dd538f0 SG	111	}
	112
	113	/*
	114	* The setpoints are selected per PLL/PDF frequencies, so we need to
	115	* reprogram PLL for frequency scaling. The procedure of reprogramming
	116	* PLL1 is as below.
a35fc5a3 BP	117	* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	118	* flow is slightly different from other i.MX6 OSC.
	119	* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
1dd538f0 SG	120	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	121	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	122	* - Disable pll2_pfd2_396m_clk
	123	*/
3fafb4e7 OP	124	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	125	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	126	/*
	127	* When changing pll1_sw_clk's parent to pll1_sys_clk,
	128	* CPU may run at higher than 528MHz, this will lead to
	129	* the system unstable if the voltage is lower than the
	130	* voltage of 528MHz, so lower the CPU frequency to one
	131	* half before changing CPU frequency.
	132	*/
2332bd04 DA	133	clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
	134	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	135	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
	136	clk_set_parent(clks[SECONDARY_SEL].clk,
	137	clks[PLL2_BUS].clk);
a35fc5a3	138	else
2332bd04 DA	139	clk_set_parent(clks[SECONDARY_SEL].clk,
	140	clks[PLL2_PFD2_396M].clk);
	141	clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
	142	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
5028f5d2 AH	143	if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
	144	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	145	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	146	}
a35fc5a3	147	} else {
2332bd04 DA	148	clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
	149	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
	150	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
	151	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	152	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
fded5fc8 LC	153	} else {
	154	/* pll1_sys needs to be enabled for divider rate change to work. */
	155	pll1_sys_temp_enabled = true;
2332bd04	156	clk_prepare_enable(clks[PLL1_SYS].clk);
a35fc5a3	157	}
1dd538f0 SG	158	}
	159
	160	/* Ensure the arm clock divider is what we expect */
2332bd04	161	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
1dd538f0	162	if (ret) {
6ef28a04 AH	163	int ret1;
6ef28a04 AH	164
1dd538f0	165	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
6ef28a04 AH	166	ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
	167	if (ret1)
	168	dev_warn(cpu_dev,
	169	"failed to restore vddarm voltage: %d\n", ret1);
d4019f0a	170	return ret;
1dd538f0 SG	171	}
1dd538f0 SG	172
fded5fc8 LC	173	/* PLL1 is only needed until after ARM-PODF is set. */
fded5fc8 LC	174	if (pll1_sys_temp_enabled)
2332bd04	175	clk_disable_unprepare(clks[PLL1_SYS].clk);
fded5fc8	176
1dd538f0	177	/* scaling down? scale voltage after frequency */
d4019f0a	178	if (new_freq < old_freq) {
1dd538f0	179	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	180	if (ret) {
1dd538f0 SG	181	dev_warn(cpu_dev,
1dd538f0 SG	182	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	183	ret = 0;
5a571c35 VK	184	}
b4573d1d AH	185	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	186	if (ret) {
	187	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
	188	ret = 0;
	189	}
22d0628a AH	190	if (!IS_ERR(pu_reg)) {
	191	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	192	if (ret) {
	193	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
	194	ret = 0;
	195	}
1dd538f0 SG	196	}
	197	}
	198
d4019f0a	199	return 0;
1dd538f0 SG	200	}
1dd538f0 SG	201
a1d00154 BS	202	static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
	203	{
	204	cdev = of_cpufreq_cooling_register(policy);
	205
	206	if (!cdev)
	207	dev_err(cpu_dev,
	208	"running cpufreq without cooling device: %ld\n",
	209	PTR_ERR(cdev));
	210	}
	211
1dd538f0 SG	212	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
1dd538f0 SG	213	{
5aa1599f LC	214	int ret;
5aa1599f LC	215
2332bd04	216	policy->clk = clks[ARM].clk;
5aa1599f	217	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
8d768cdc	218	policy->suspend_freq = max_freq;
5aa1599f LC	219
5aa1599f LC	220	return ret;
1dd538f0 SG	221	}
1dd538f0 SG	222
a1d00154 BS	223	static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
	224	{
	225	cpufreq_cooling_unregister(cdev);
	226
	227	return 0;
	228	}
	229
1dd538f0	230	static struct cpufreq_driver imx6q_cpufreq_driver = {
ae6b4271	231	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
4f6ba385	232	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	233	.target_index = imx6q_set_target,
652ed95d	234	.get = cpufreq_generic_get,
1dd538f0	235	.init = imx6q_cpufreq_init,
a1d00154	236	.exit = imx6q_cpufreq_exit,
1dd538f0	237	.name = "imx6q-cpufreq",
a1d00154	238	.ready = imx6q_cpufreq_ready,
4f6ba385	239	.attr = cpufreq_generic_attr,
5aa1599f	240	.suspend = cpufreq_generic_suspend,
1dd538f0 SG	241	};
1dd538f0 SG	242
2b3d58a3 FE	243	#define OCOTP_CFG3 0x440
	244	#define OCOTP_CFG3_SPEED_SHIFT 16
	245	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	246	#define OCOTP_CFG3_SPEED_996MHZ 0x2
	247	#define OCOTP_CFG3_SPEED_852MHZ 0x1
	248
	249	static void imx6q_opp_check_speed_grading(struct device *dev)
	250	{
	251	struct device_node *np;
	252	void __iomem *base;
	253	u32 val;
	254
	255	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	256	if (!np)
	257	return;
	258
	259	base = of_iomap(np, 0);
	260	if (!base) {
	261	dev_err(dev, "failed to map ocotp\n");
	262	goto put_node;
	263	}
	264
	265	/*
	266	* SPEED_GRADING[1:0] defines the max speed of ARM:
	267	* 2b'11: 1200000000Hz;
	268	* 2b'10: 996000000Hz;
	269	* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	270	* 2b'00: 792000000Hz;
	271	* We need to set the max speed of ARM according to fuse map.
	272	*/
	273	val = readl_relaxed(base + OCOTP_CFG3);
	274	val >>= OCOTP_CFG3_SPEED_SHIFT;
	275	val &= 0x3;
	276
2b3d58a3 FE	277	if (val < OCOTP_CFG3_SPEED_996MHZ)
	278	if (dev_pm_opp_disable(dev, 996000000))
	279	dev_warn(dev, "failed to disable 996MHz OPP\n");
ccc153a6 LS	280
	281	if (of_machine_is_compatible("fsl,imx6q") \|\|
	282	of_machine_is_compatible("fsl,imx6qp")) {
2b3d58a3 FE	283	if (val != OCOTP_CFG3_SPEED_852MHZ)
	284	if (dev_pm_opp_disable(dev, 852000000))
	285	dev_warn(dev, "failed to disable 852MHz OPP\n");
ccc153a6 LS	286	if (val != OCOTP_CFG3_SPEED_1P2GHZ)
	287	if (dev_pm_opp_disable(dev, 1200000000))
	288	dev_warn(dev, "failed to disable 1.2GHz OPP\n");
2b3d58a3 FE	289	}
	290	iounmap(base);
	291	put_node:
	292	of_node_put(np);
	293	}
	294
5028f5d2	295	#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
0aa9abd4 SS	296	#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
0aa9abd4 SS	297	#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
5028f5d2	298
2733fb0d	299	static int imx6ul_opp_check_speed_grading(struct device *dev)
5028f5d2	300	{
5028f5d2	301	u32 val;
2733fb0d	302	int ret = 0;
5028f5d2	303
2733fb0d AH	304	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
	305	ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
	306	if (ret)
	307	return ret;
	308	} else {
	309	struct device_node *np;
	310	void __iomem *base;
	311
	312	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
	313	if (!np)
	314	return -ENOENT;
	315
	316	base = of_iomap(np, 0);
	317	of_node_put(np);
	318	if (!base) {
	319	dev_err(dev, "failed to map ocotp\n");
	320	return -EFAULT;
	321	}
5028f5d2	322
2733fb0d AH	323	val = readl_relaxed(base + OCOTP_CFG3);
2733fb0d AH	324	iounmap(base);
5028f5d2 AH	325	}
	326
	327	/*
	328	* Speed GRADING[1:0] defines the max speed of ARM:
	329	* 2b'00: Reserved;
	330	* 2b'01: 528000000Hz;
0aa9abd4 SS	331	* 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
0aa9abd4 SS	332	* 2b'11: 900000000Hz on i.MX6ULL only;
5028f5d2 AH	333	* We need to set the max speed of ARM according to fuse map.
5028f5d2 AH	334	*/
5028f5d2 AH	335	val >>= OCOTP_CFG3_SPEED_SHIFT;
5028f5d2 AH	336	val &= 0x3;
0aa9abd4 SS	337
	338	if (of_machine_is_compatible("fsl,imx6ul")) {
	339	if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
	340	if (dev_pm_opp_disable(dev, 696000000))
	341	dev_warn(dev, "failed to disable 696MHz OPP\n");
	342	}
	343
	344	if (of_machine_is_compatible("fsl,imx6ull")) {
	345	if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
	346	if (dev_pm_opp_disable(dev, 792000000))
	347	dev_warn(dev, "failed to disable 792MHz OPP\n");
	348
	349	if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
	350	if (dev_pm_opp_disable(dev, 900000000))
	351	dev_warn(dev, "failed to disable 900MHz OPP\n");
	352	}
	353
2733fb0d	354	return ret;
5028f5d2 AH	355	}
5028f5d2 AH	356
1dd538f0 SG	357	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	358	{
	359	struct device_node *np;
47d43ba7	360	struct dev_pm_opp *opp;
1dd538f0 SG	361	unsigned long min_volt, max_volt;
1dd538f0 SG	362	int num, ret;
b4573d1d AH	363	const struct property *prop;
	364	const __be32 *val;
	365	u32 nr, i, j;
1dd538f0	366
b494b48d SK	367	cpu_dev = get_cpu_device(0);
	368	if (!cpu_dev) {
	369	pr_err("failed to get cpu0 device\n");
	370	return -ENODEV;
	371	}
1dd538f0	372
cdc58d60	373	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	374	if (!np) {
	375	dev_err(cpu_dev, "failed to find cpu0 node\n");
	376	return -ENOENT;
	377	}
	378
3fafb4e7	379	if (of_machine_is_compatible("fsl,imx6ul") \|\|
2332bd04 DA	380	of_machine_is_compatible("fsl,imx6ull"))
	381	num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	382	else
	383	num_clks = IMX6Q_CPUFREQ_CLK_NUM;
	384
	385	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	386	if (ret)
	387	goto put_node;
a35fc5a3	388
f8269c19	389	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	390	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	391	soc_reg = regulator_get(cpu_dev, "soc");
54cad2fc IT	392	if (PTR_ERR(arm_reg) == -EPROBE_DEFER \|\|
	393	PTR_ERR(soc_reg) == -EPROBE_DEFER \|\|
	394	PTR_ERR(pu_reg) == -EPROBE_DEFER) {
	395	ret = -EPROBE_DEFER;
	396	dev_dbg(cpu_dev, "regulators not ready, defer\n");
	397	goto put_reg;
	398	}
22d0628a	399	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	400	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	401	ret = -ENOENT;
f8269c19	402	goto put_reg;
1dd538f0 SG	403	}
1dd538f0 SG	404
2b3d58a3 FE	405	ret = dev_pm_opp_of_add_table(cpu_dev);
	406	if (ret < 0) {
	407	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
	408	goto put_reg;
	409	}
20b7cbe2	410
0aa9abd4	411	if (of_machine_is_compatible("fsl,imx6ul") \|\|
2733fb0d AH	412	of_machine_is_compatible("fsl,imx6ull")) {
	413	ret = imx6ul_opp_check_speed_grading(cpu_dev);
	414	if (ret == -EPROBE_DEFER)
	415	return ret;
	416	if (ret) {
	417	dev_err(cpu_dev, "failed to read ocotp: %d\n",
	418	ret);
	419	return ret;
	420	}
	421	} else {
5028f5d2	422	imx6q_opp_check_speed_grading(cpu_dev);
2733fb0d	423	}
cc87b8a8	424
2b3d58a3 FE	425	/* Because we have added the OPPs here, we must free them */
	426	free_opp = true;
	427	num = dev_pm_opp_get_opp_count(cpu_dev);
	428	if (num < 0) {
	429	ret = num;
	430	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
	431	goto out_free_opp;
1dd538f0 SG	432	}
1dd538f0 SG	433
5d4879cd	434	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	435	if (ret) {
1dd538f0 SG	436	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
eafca851	437	goto out_free_opp;
1dd538f0 SG	438	}
1dd538f0 SG	439
b4573d1d	440	/* Make imx6_soc_volt array's size same as arm opp number */
a86854d0 KC	441	imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
a86854d0 KC	442	GFP_KERNEL);
b4573d1d AH	443	if (imx6_soc_volt == NULL) {
	444	ret = -ENOMEM;
	445	goto free_freq_table;
	446	}
	447
	448	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	449	if (!prop \|\| !prop->value)
	450	goto soc_opp_out;
	451
	452	/*
	453	* Each OPP is a set of tuples consisting of frequency and
	454	* voltage like <freq-kHz vol-uV>.
	455	*/
	456	nr = prop->length / sizeof(u32);
	457	if (nr % 2 \|\| (nr / 2) < num)
	458	goto soc_opp_out;
	459
	460	for (j = 0; j < num; j++) {
	461	val = prop->value;
	462	for (i = 0; i < nr / 2; i++) {
	463	unsigned long freq = be32_to_cpup(val++);
	464	unsigned long volt = be32_to_cpup(val++);
	465	if (freq_table[j].frequency == freq) {
	466	imx6_soc_volt[soc_opp_count++] = volt;
	467	break;
	468	}
	469	}
	470	}
	471
	472	soc_opp_out:
	473	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	474	if (soc_opp_count != num) {
	475	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	476	for (j = 0; j < num; j++)
	477	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	478	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	479	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	480	}
	481
1dd538f0 SG	482	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	483	transition_latency = CPUFREQ_ETERNAL;
	484
b4573d1d AH	485	/*
	486	* Calculate the ramp time for max voltage change in the
	487	* VDDSOC and VDDPU regulators.
	488	*/
	489	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	490	if (ret > 0)
	491	transition_latency += ret * 1000;
22d0628a AH	492	if (!IS_ERR(pu_reg)) {
	493	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	494	if (ret > 0)
	495	transition_latency += ret * 1000;
	496	}
b4573d1d	497
1dd538f0 SG	498	/*
	499	* OPP is maintained in order of increasing frequency, and
	500	* freq_table initialised from OPP is therefore sorted in the
	501	* same order.
	502	*/
8d768cdc	503	max_freq = freq_table[--num].frequency;
5d4879cd	504	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	505	freq_table[0].frequency * 1000, true);
5d4879cd	506	min_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	507	dev_pm_opp_put(opp);
8d768cdc	508	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
5d4879cd	509	max_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	510	dev_pm_opp_put(opp);
8a31d9d9 VK	511
1dd538f0 SG	512	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	513	if (ret > 0)
	514	transition_latency += ret * 1000;
	515
1dd538f0 SG	516	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	517	if (ret) {
	518	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	519	goto free_freq_table;
	520	}
	521
	522	of_node_put(np);
	523	return 0;
	524
	525	free_freq_table:
5d4879cd	526	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8 VK	527	out_free_opp:
cc87b8a8 VK	528	if (free_opp)
8f8d37b2	529	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19 PZ	530	put_reg:
	531	if (!IS_ERR(arm_reg))
	532	regulator_put(arm_reg);
	533	if (!IS_ERR(pu_reg))
	534	regulator_put(pu_reg);
	535	if (!IS_ERR(soc_reg))
	536	regulator_put(soc_reg);
2332bd04 DA	537
	538	clk_bulk_put(num_clks, clks);
	539	put_node:
1dd538f0	540	of_node_put(np);
2332bd04	541
1dd538f0 SG	542	return ret;
	543	}
	544
	545	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	546	{
	547	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	548	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8	549	if (free_opp)
8f8d37b2	550	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19	551	regulator_put(arm_reg);
22d0628a AH	552	if (!IS_ERR(pu_reg))
22d0628a AH	553	regulator_put(pu_reg);
f8269c19	554	regulator_put(soc_reg);
2332bd04 DA	555
2332bd04 DA	556	clk_bulk_put(num_clks, clks);
1dd538f0 SG	557
	558	return 0;
	559	}
	560
	561	static struct platform_driver imx6q_cpufreq_platdrv = {
	562	.driver = {
	563	.name = "imx6q-cpufreq",
1dd538f0 SG	564	},
	565	.probe = imx6q_cpufreq_probe,
	566	.remove = imx6q_cpufreq_remove,
	567	};
	568	module_platform_driver(imx6q_cpufreq_platdrv);
	569
d0404738	570	MODULE_ALIAS("platform:imx6q-cpufreq");
1dd538f0 SG	571	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	572	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	573	MODULE_LICENSE("GPL");