[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

enum IMX6_CPUFREQ_CLKS {
	ARM,
	PLL1_SYS,
	STEP,
	PLL1_SW,
	PLL2_PFD2_396M,
	/* MX6UL requires two more clks */
	PLL2_BUS,
	SECONDARY_SEL,
};
#define IMX6Q_CPUFREQ_CLK_NUM		5
#define IMX6UL_CPUFREQ_CLK_NUM		7

static int num_clks;
static struct clk_bulk_data clks[] = {
	{ .id = "arm" },
	{ .id = "pll1_sys" },
	{ .id = "step" },
	{ .id = "pll1_sw" },
	{ .id = "pll2_pfd2_396m" },
	{ .id = "pll2_bus" },
	{ .id = "secondary_sel" },
};

static struct device *cpu_dev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int max_freq;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	bool pll1_sys_temp_enabled = false;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(clks[ARM].clk) / 1000;

	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	 * flow is slightly different from other i.MX6 OSC.
	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
		clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_BUS].clk);
		else
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		}
	} else {
		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(clks[PLL1_SYS].clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		regulator_set_voltage_tol(arm_reg, volt_old, 0);
		return ret;
	}

	/* PLL1 is only needed until after ARM-PODF is set. */
	if (pll1_sys_temp_enabled)
		clk_disable_unprepare(clks[PLL1_SYS].clk);

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
			ret = 0;
		}
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
				ret = 0;
			}
		}
	}

	return 0;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->clk = clks[ARM].clk;
	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	policy->suspend_freq = max_freq;

	return ret;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
	.suspend = cpufreq_generic_suspend,
};

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3
#define OCOTP_CFG3_SPEED_996MHZ		0x2
#define OCOTP_CFG3_SPEED_852MHZ		0x1

static void imx6q_opp_check_speed_grading(struct device *dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np)
		return;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(dev, "failed to map ocotp\n");
		goto put_node;
	}

	/*
	 * SPEED_GRADING[1:0] defines the max speed of ARM:
	 * 2b'11: 1200000000Hz;
	 * 2b'10: 996000000Hz;
	 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	 * 2b'00: 792000000Hz;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (val < OCOTP_CFG3_SPEED_996MHZ)
		if (dev_pm_opp_disable(dev, 996000000))
			dev_warn(dev, "failed to disable 996MHz OPP\n");

	if (of_machine_is_compatible("fsl,imx6q") ||
	    of_machine_is_compatible("fsl,imx6qp")) {
		if (val != OCOTP_CFG3_SPEED_852MHZ)
			if (dev_pm_opp_disable(dev, 852000000))
				dev_warn(dev, "failed to disable 852MHz OPP\n");
		if (val != OCOTP_CFG3_SPEED_1P2GHZ)
			if (dev_pm_opp_disable(dev, 1200000000))
				dev_warn(dev, "failed to disable 1.2GHz OPP\n");
	}
	iounmap(base);
put_node:
	of_node_put(np);
}

#define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2

static void imx6ul_opp_check_speed_grading(struct device *dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
	if (!np)
		return;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(dev, "failed to map ocotp\n");
		goto put_node;
	}

	/*
	 * Speed GRADING[1:0] defines the max speed of ARM:
	 * 2b'00: Reserved;
	 * 2b'01: 528000000Hz;
	 * 2b'10: 696000000Hz;
	 * 2b'11: Reserved;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;
	if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
		if (dev_pm_opp_disable(dev, 696000000))
			dev_warn(dev, "failed to disable 696MHz OPP\n");
	iounmap(base);
put_node:
	of_node_put(np);
}

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull"))
		num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	else
		num_clks = IMX6Q_CPUFREQ_CLK_NUM;

	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	if (ret)
		goto put_node;

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		dev_dbg(cpu_dev, "regulators not ready, defer\n");
		goto put_reg;
	}
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	ret = dev_pm_opp_of_add_table(cpu_dev);
	if (ret < 0) {
		dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
		goto put_reg;
	}

	if (of_machine_is_compatible("fsl,imx6ul"))
		imx6ul_opp_check_speed_grading(cpu_dev);
	else
		imx6q_opp_check_speed_grading(cpu_dev);

	/* Because we have added the OPPs here, we must free them */
	free_opp = true;
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = num;
		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
		goto out_free_opp;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_free_opp;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	max_freq = freq_table[--num].frequency;
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_opp:
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);
put_node:
	of_node_put(np);

	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_ALIAS("platform:imx6q-cpufreq");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0	11	#include <linux/cpufreq.h>
1dd538f0 SG	12	#include <linux/err.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
2b3d58a3	15	#include <linux/of_address.h>
e4db1c74	16	#include <linux/pm_opp.h>
1dd538f0 SG	17	#include <linux/platform_device.h>
	18	#include <linux/regulator/consumer.h>
	19
	20	#define PU_SOC_VOLTAGE_NORMAL 1250000
	21	#define PU_SOC_VOLTAGE_HIGH 1275000
	22	#define FREQ_1P2_GHZ 1200000000
	23
	24	static struct regulator *arm_reg;
	25	static struct regulator *pu_reg;
	26	static struct regulator *soc_reg;
	27
2332bd04 DA	28	enum IMX6_CPUFREQ_CLKS {
	29	ARM,
	30	PLL1_SYS,
	31	STEP,
	32	PLL1_SW,
	33	PLL2_PFD2_396M,
	34	/* MX6UL requires two more clks */
	35	PLL2_BUS,
	36	SECONDARY_SEL,
	37	};
	38	#define IMX6Q_CPUFREQ_CLK_NUM 5
	39	#define IMX6UL_CPUFREQ_CLK_NUM 7
	40
	41	static int num_clks;
	42	static struct clk_bulk_data clks[] = {
	43	{ .id = "arm" },
	44	{ .id = "pll1_sys" },
	45	{ .id = "step" },
	46	{ .id = "pll1_sw" },
	47	{ .id = "pll2_pfd2_396m" },
	48	{ .id = "pll2_bus" },
	49	{ .id = "secondary_sel" },
	50	};
a35fc5a3	51
1dd538f0	52	static struct device *cpu_dev;
cc87b8a8	53	static bool free_opp;
1dd538f0	54	static struct cpufreq_frequency_table *freq_table;
8d768cdc	55	static unsigned int max_freq;
1dd538f0 SG	56	static unsigned int transition_latency;
1dd538f0 SG	57
b4573d1d AH	58	static u32 *imx6_soc_volt;
	59	static u32 soc_opp_count;
	60
9c0ebcf7	61	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	62	{
47d43ba7	63	struct dev_pm_opp *opp;
1dd538f0	64	unsigned long freq_hz, volt, volt_old;
d4019f0a	65	unsigned int old_freq, new_freq;
fded5fc8	66	bool pll1_sys_temp_enabled = false;
1dd538f0 SG	67	int ret;
1dd538f0 SG	68
d4019f0a VK	69	new_freq = freq_table[index].frequency;
d4019f0a VK	70	freq_hz = new_freq * 1000;
2332bd04	71	old_freq = clk_get_rate(clks[ARM].clk) / 1000;
1dd538f0	72
5d4879cd	73	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0	74	if (IS_ERR(opp)) {
1dd538f0 SG	75	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	76	return PTR_ERR(opp);
	77	}
	78
5d4879cd	79	volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	80	dev_pm_opp_put(opp);
8a31d9d9 VK	81
1dd538f0 SG	82	volt_old = regulator_get_voltage(arm_reg);
	83
	84	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	85	old_freq / 1000, volt_old / 1000,
d4019f0a VK	86	new_freq / 1000, volt / 1000);
5a571c35	87
1dd538f0	88	/* scaling up? scale voltage before frequency */
d4019f0a	89	if (new_freq > old_freq) {
22d0628a AH	90	if (!IS_ERR(pu_reg)) {
	91	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	92	if (ret) {
	93	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	94	return ret;
	95	}
b4573d1d AH	96	}
	97	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	98	if (ret) {
	99	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	100	return ret;
	101	}
1dd538f0 SG	102	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	103	if (ret) {
	104	dev_err(cpu_dev,
	105	"failed to scale vddarm up: %d\n", ret);
d4019f0a	106	return ret;
1dd538f0	107	}
1dd538f0 SG	108	}
	109
	110	/*
	111	* The setpoints are selected per PLL/PDF frequencies, so we need to
	112	* reprogram PLL for frequency scaling. The procedure of reprogramming
	113	* PLL1 is as below.
a35fc5a3 BP	114	* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	115	* flow is slightly different from other i.MX6 OSC.
	116	* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
1dd538f0 SG	117	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	118	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	119	* - Disable pll2_pfd2_396m_clk
	120	*/
3fafb4e7 OP	121	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	122	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	123	/*
	124	* When changing pll1_sw_clk's parent to pll1_sys_clk,
	125	* CPU may run at higher than 528MHz, this will lead to
	126	* the system unstable if the voltage is lower than the
	127	* voltage of 528MHz, so lower the CPU frequency to one
	128	* half before changing CPU frequency.
	129	*/
2332bd04 DA	130	clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
	131	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	132	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
	133	clk_set_parent(clks[SECONDARY_SEL].clk,
	134	clks[PLL2_BUS].clk);
a35fc5a3	135	else
2332bd04 DA	136	clk_set_parent(clks[SECONDARY_SEL].clk,
	137	clks[PLL2_PFD2_396M].clk);
	138	clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
	139	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
5028f5d2 AH	140	if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
	141	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	142	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	143	}
a35fc5a3	144	} else {
2332bd04 DA	145	clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
	146	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
	147	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
	148	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	149	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
fded5fc8 LC	150	} else {
	151	/* pll1_sys needs to be enabled for divider rate change to work. */
	152	pll1_sys_temp_enabled = true;
2332bd04	153	clk_prepare_enable(clks[PLL1_SYS].clk);
a35fc5a3	154	}
1dd538f0 SG	155	}
	156
	157	/* Ensure the arm clock divider is what we expect */
2332bd04	158	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
1dd538f0 SG	159	if (ret) {
	160	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
	161	regulator_set_voltage_tol(arm_reg, volt_old, 0);
d4019f0a	162	return ret;
1dd538f0 SG	163	}
1dd538f0 SG	164
fded5fc8 LC	165	/* PLL1 is only needed until after ARM-PODF is set. */
fded5fc8 LC	166	if (pll1_sys_temp_enabled)
2332bd04	167	clk_disable_unprepare(clks[PLL1_SYS].clk);
fded5fc8	168
1dd538f0	169	/* scaling down? scale voltage after frequency */
d4019f0a	170	if (new_freq < old_freq) {
1dd538f0	171	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	172	if (ret) {
1dd538f0 SG	173	dev_warn(cpu_dev,
1dd538f0 SG	174	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	175	ret = 0;
5a571c35 VK	176	}
b4573d1d AH	177	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	178	if (ret) {
	179	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
	180	ret = 0;
	181	}
22d0628a AH	182	if (!IS_ERR(pu_reg)) {
	183	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	184	if (ret) {
	185	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
	186	ret = 0;
	187	}
1dd538f0 SG	188	}
	189	}
	190
d4019f0a	191	return 0;
1dd538f0 SG	192	}
	193
	194	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	195	{
5aa1599f LC	196	int ret;
5aa1599f LC	197
2332bd04	198	policy->clk = clks[ARM].clk;
5aa1599f	199	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
8d768cdc	200	policy->suspend_freq = max_freq;
5aa1599f LC	201
5aa1599f LC	202	return ret;
1dd538f0 SG	203	}
1dd538f0 SG	204
1dd538f0	205	static struct cpufreq_driver imx6q_cpufreq_driver = {
ae6b4271	206	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
4f6ba385	207	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	208	.target_index = imx6q_set_target,
652ed95d	209	.get = cpufreq_generic_get,
1dd538f0	210	.init = imx6q_cpufreq_init,
1dd538f0	211	.name = "imx6q-cpufreq",
4f6ba385	212	.attr = cpufreq_generic_attr,
5aa1599f	213	.suspend = cpufreq_generic_suspend,
1dd538f0 SG	214	};
1dd538f0 SG	215
2b3d58a3 FE	216	#define OCOTP_CFG3 0x440
	217	#define OCOTP_CFG3_SPEED_SHIFT 16
	218	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	219	#define OCOTP_CFG3_SPEED_996MHZ 0x2
	220	#define OCOTP_CFG3_SPEED_852MHZ 0x1
	221
	222	static void imx6q_opp_check_speed_grading(struct device *dev)
	223	{
	224	struct device_node *np;
	225	void __iomem *base;
	226	u32 val;
	227
	228	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	229	if (!np)
	230	return;
	231
	232	base = of_iomap(np, 0);
	233	if (!base) {
	234	dev_err(dev, "failed to map ocotp\n");
	235	goto put_node;
	236	}
	237
	238	/*
	239	* SPEED_GRADING[1:0] defines the max speed of ARM:
	240	* 2b'11: 1200000000Hz;
	241	* 2b'10: 996000000Hz;
	242	* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	243	* 2b'00: 792000000Hz;
	244	* We need to set the max speed of ARM according to fuse map.
	245	*/
	246	val = readl_relaxed(base + OCOTP_CFG3);
	247	val >>= OCOTP_CFG3_SPEED_SHIFT;
	248	val &= 0x3;
	249
2b3d58a3 FE	250	if (val < OCOTP_CFG3_SPEED_996MHZ)
	251	if (dev_pm_opp_disable(dev, 996000000))
	252	dev_warn(dev, "failed to disable 996MHz OPP\n");
ccc153a6 LS	253
	254	if (of_machine_is_compatible("fsl,imx6q") \|\|
	255	of_machine_is_compatible("fsl,imx6qp")) {
2b3d58a3 FE	256	if (val != OCOTP_CFG3_SPEED_852MHZ)
	257	if (dev_pm_opp_disable(dev, 852000000))
	258	dev_warn(dev, "failed to disable 852MHz OPP\n");
ccc153a6 LS	259	if (val != OCOTP_CFG3_SPEED_1P2GHZ)
	260	if (dev_pm_opp_disable(dev, 1200000000))
	261	dev_warn(dev, "failed to disable 1.2GHz OPP\n");
2b3d58a3 FE	262	}
	263	iounmap(base);
	264	put_node:
	265	of_node_put(np);
	266	}
	267
5028f5d2 AH	268	#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
	269
	270	static void imx6ul_opp_check_speed_grading(struct device *dev)
	271	{
	272	struct device_node *np;
	273	void __iomem *base;
	274	u32 val;
	275
	276	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
	277	if (!np)
	278	return;
	279
	280	base = of_iomap(np, 0);
	281	if (!base) {
	282	dev_err(dev, "failed to map ocotp\n");
	283	goto put_node;
	284	}
	285
	286	/*
	287	* Speed GRADING[1:0] defines the max speed of ARM:
	288	* 2b'00: Reserved;
	289	* 2b'01: 528000000Hz;
	290	* 2b'10: 696000000Hz;
	291	* 2b'11: Reserved;
	292	* We need to set the max speed of ARM according to fuse map.
	293	*/
	294	val = readl_relaxed(base + OCOTP_CFG3);
	295	val >>= OCOTP_CFG3_SPEED_SHIFT;
	296	val &= 0x3;
	297	if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
	298	if (dev_pm_opp_disable(dev, 696000000))
	299	dev_warn(dev, "failed to disable 696MHz OPP\n");
	300	iounmap(base);
	301	put_node:
	302	of_node_put(np);
	303	}
	304
1dd538f0 SG	305	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	306	{
	307	struct device_node *np;
47d43ba7	308	struct dev_pm_opp *opp;
1dd538f0 SG	309	unsigned long min_volt, max_volt;
1dd538f0 SG	310	int num, ret;
b4573d1d AH	311	const struct property *prop;
	312	const __be32 *val;
	313	u32 nr, i, j;
1dd538f0	314
b494b48d SK	315	cpu_dev = get_cpu_device(0);
	316	if (!cpu_dev) {
	317	pr_err("failed to get cpu0 device\n");
	318	return -ENODEV;
	319	}
1dd538f0	320
cdc58d60	321	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	322	if (!np) {
	323	dev_err(cpu_dev, "failed to find cpu0 node\n");
	324	return -ENOENT;
	325	}
	326
3fafb4e7	327	if (of_machine_is_compatible("fsl,imx6ul") \|\|
2332bd04 DA	328	of_machine_is_compatible("fsl,imx6ull"))
	329	num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	330	else
	331	num_clks = IMX6Q_CPUFREQ_CLK_NUM;
	332
	333	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	334	if (ret)
	335	goto put_node;
a35fc5a3	336
f8269c19	337	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	338	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	339	soc_reg = regulator_get(cpu_dev, "soc");
54cad2fc IT	340	if (PTR_ERR(arm_reg) == -EPROBE_DEFER \|\|
	341	PTR_ERR(soc_reg) == -EPROBE_DEFER \|\|
	342	PTR_ERR(pu_reg) == -EPROBE_DEFER) {
	343	ret = -EPROBE_DEFER;
	344	dev_dbg(cpu_dev, "regulators not ready, defer\n");
	345	goto put_reg;
	346	}
22d0628a	347	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	348	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	349	ret = -ENOENT;
f8269c19	350	goto put_reg;
1dd538f0 SG	351	}
1dd538f0 SG	352
2b3d58a3 FE	353	ret = dev_pm_opp_of_add_table(cpu_dev);
	354	if (ret < 0) {
	355	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
	356	goto put_reg;
	357	}
20b7cbe2	358
5028f5d2 AH	359	if (of_machine_is_compatible("fsl,imx6ul"))
	360	imx6ul_opp_check_speed_grading(cpu_dev);
	361	else
	362	imx6q_opp_check_speed_grading(cpu_dev);
cc87b8a8	363
2b3d58a3 FE	364	/* Because we have added the OPPs here, we must free them */
	365	free_opp = true;
	366	num = dev_pm_opp_get_opp_count(cpu_dev);
	367	if (num < 0) {
	368	ret = num;
	369	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
	370	goto out_free_opp;
1dd538f0 SG	371	}
1dd538f0 SG	372
5d4879cd	373	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	374	if (ret) {
1dd538f0 SG	375	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
eafca851	376	goto out_free_opp;
1dd538f0 SG	377	}
1dd538f0 SG	378
b4573d1d AH	379	/* Make imx6_soc_volt array's size same as arm opp number */
	380	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(imx6_soc_volt) num, GFP_KERNEL);
	381	if (imx6_soc_volt == NULL) {
	382	ret = -ENOMEM;
	383	goto free_freq_table;
	384	}
	385
	386	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	387	if (!prop \|\| !prop->value)
	388	goto soc_opp_out;
	389
	390	/*
	391	* Each OPP is a set of tuples consisting of frequency and
	392	* voltage like <freq-kHz vol-uV>.
	393	*/
	394	nr = prop->length / sizeof(u32);
	395	if (nr % 2 \|\| (nr / 2) < num)
	396	goto soc_opp_out;
	397
	398	for (j = 0; j < num; j++) {
	399	val = prop->value;
	400	for (i = 0; i < nr / 2; i++) {
	401	unsigned long freq = be32_to_cpup(val++);
	402	unsigned long volt = be32_to_cpup(val++);
	403	if (freq_table[j].frequency == freq) {
	404	imx6_soc_volt[soc_opp_count++] = volt;
	405	break;
	406	}
	407	}
	408	}
	409
	410	soc_opp_out:
	411	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	412	if (soc_opp_count != num) {
	413	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	414	for (j = 0; j < num; j++)
	415	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	416	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	417	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	418	}
	419
1dd538f0 SG	420	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	421	transition_latency = CPUFREQ_ETERNAL;
	422
b4573d1d AH	423	/*
	424	* Calculate the ramp time for max voltage change in the
	425	* VDDSOC and VDDPU regulators.
	426	*/
	427	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	428	if (ret > 0)
	429	transition_latency += ret * 1000;
22d0628a AH	430	if (!IS_ERR(pu_reg)) {
	431	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	432	if (ret > 0)
	433	transition_latency += ret * 1000;
	434	}
b4573d1d	435
1dd538f0 SG	436	/*
	437	* OPP is maintained in order of increasing frequency, and
	438	* freq_table initialised from OPP is therefore sorted in the
	439	* same order.
	440	*/
8d768cdc	441	max_freq = freq_table[--num].frequency;
5d4879cd	442	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	443	freq_table[0].frequency * 1000, true);
5d4879cd	444	min_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	445	dev_pm_opp_put(opp);
8d768cdc	446	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
5d4879cd	447	max_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	448	dev_pm_opp_put(opp);
8a31d9d9 VK	449
1dd538f0 SG	450	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	451	if (ret > 0)
	452	transition_latency += ret * 1000;
	453
1dd538f0 SG	454	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	455	if (ret) {
	456	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	457	goto free_freq_table;
	458	}
	459
	460	of_node_put(np);
	461	return 0;
	462
	463	free_freq_table:
5d4879cd	464	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8 VK	465	out_free_opp:
cc87b8a8 VK	466	if (free_opp)
8f8d37b2	467	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19 PZ	468	put_reg:
	469	if (!IS_ERR(arm_reg))
	470	regulator_put(arm_reg);
	471	if (!IS_ERR(pu_reg))
	472	regulator_put(pu_reg);
	473	if (!IS_ERR(soc_reg))
	474	regulator_put(soc_reg);
2332bd04 DA	475
	476	clk_bulk_put(num_clks, clks);
	477	put_node:
1dd538f0	478	of_node_put(np);
2332bd04	479
1dd538f0 SG	480	return ret;
	481	}
	482
	483	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	484	{
	485	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	486	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8	487	if (free_opp)
8f8d37b2	488	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19	489	regulator_put(arm_reg);
22d0628a AH	490	if (!IS_ERR(pu_reg))
22d0628a AH	491	regulator_put(pu_reg);
f8269c19	492	regulator_put(soc_reg);
2332bd04 DA	493
2332bd04 DA	494	clk_bulk_put(num_clks, clks);
1dd538f0 SG	495
	496	return 0;
	497	}
	498
	499	static struct platform_driver imx6q_cpufreq_platdrv = {
	500	.driver = {
	501	.name = "imx6q-cpufreq",
1dd538f0 SG	502	},
	503	.probe = imx6q_cpufreq_probe,
	504	.remove = imx6q_cpufreq_remove,
	505	};
	506	module_platform_driver(imx6q_cpufreq_platdrv);
	507
d0404738	508	MODULE_ALIAS("platform:imx6q-cpufreq");
1dd538f0 SG	509	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	510	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	511	MODULE_LICENSE("GPL");