[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

enum IMX6_CPUFREQ_CLKS {
	ARM,
	PLL1_SYS,
	STEP,
	PLL1_SW,
	PLL2_PFD2_396M,
	/* MX6UL requires two more clks */
	PLL2_BUS,
	SECONDARY_SEL,
};
#define IMX6Q_CPUFREQ_CLK_NUM		5
#define IMX6UL_CPUFREQ_CLK_NUM		7

static int num_clks;
static struct clk_bulk_data clks[] = {
	{ .id = "arm" },
	{ .id = "pll1_sys" },
	{ .id = "step" },
	{ .id = "pll1_sw" },
	{ .id = "pll2_pfd2_396m" },
	{ .id = "pll2_bus" },
	{ .id = "secondary_sel" },
};

static struct device *cpu_dev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int max_freq;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	bool pll1_sys_temp_enabled = false;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(clks[ARM].clk) / 1000;

	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	 * flow is slightly different from other i.MX6 OSC.
	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
		clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_BUS].clk);
		else
			clk_set_parent(clks[SECONDARY_SEL].clk,
				       clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		}
	} else {
		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(clks[PLL1_SYS].clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
	if (ret) {
		int ret1;

		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
		if (ret1)
			dev_warn(cpu_dev,
				 "failed to restore vddarm voltage: %d\n", ret1);
		return ret;
	}

	/* PLL1 is only needed until after ARM-PODF is set. */
	if (pll1_sys_temp_enabled)
		clk_disable_unprepare(clks[PLL1_SYS].clk);

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret)
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret)
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret)
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
		}
	}

	return 0;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	policy->clk = clks[ARM].clk;
	cpufreq_generic_init(policy, freq_table, transition_latency);
	policy->suspend_freq = max_freq;
	dev_pm_opp_of_register_em(policy->cpus);

	return 0;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
		 CPUFREQ_IS_COOLING_DEV,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
	.suspend = cpufreq_generic_suspend,
};

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3
#define OCOTP_CFG3_SPEED_996MHZ		0x2
#define OCOTP_CFG3_SPEED_852MHZ		0x1

static void imx6q_opp_check_speed_grading(struct device *dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np)
		return;

	base = of_iomap(np, 0);
	if (!base) {
		dev_err(dev, "failed to map ocotp\n");
		goto put_node;
	}

	/*
	 * SPEED_GRADING[1:0] defines the max speed of ARM:
	 * 2b'11: 1200000000Hz;
	 * 2b'10: 996000000Hz;
	 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	 * 2b'00: 792000000Hz;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (val < OCOTP_CFG3_SPEED_996MHZ)
		if (dev_pm_opp_disable(dev, 996000000))
			dev_warn(dev, "failed to disable 996MHz OPP\n");

	if (of_machine_is_compatible("fsl,imx6q") ||
	    of_machine_is_compatible("fsl,imx6qp")) {
		if (val != OCOTP_CFG3_SPEED_852MHZ)
			if (dev_pm_opp_disable(dev, 852000000))
				dev_warn(dev, "failed to disable 852MHz OPP\n");
		if (val != OCOTP_CFG3_SPEED_1P2GHZ)
			if (dev_pm_opp_disable(dev, 1200000000))
				dev_warn(dev, "failed to disable 1.2GHz OPP\n");
	}
	iounmap(base);
put_node:
	of_node_put(np);
}

#define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2
#define OCOTP_CFG3_6ULL_SPEED_792MHZ	0x2
#define OCOTP_CFG3_6ULL_SPEED_900MHZ	0x3

static int imx6ul_opp_check_speed_grading(struct device *dev)
{
	u32 val;
	int ret = 0;

	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
		if (ret)
			return ret;
	} else {
		struct device_node *np;
		void __iomem *base;

		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
		if (!np)
			return -ENOENT;

		base = of_iomap(np, 0);
		of_node_put(np);
		if (!base) {
			dev_err(dev, "failed to map ocotp\n");
			return -EFAULT;
		}

		val = readl_relaxed(base + OCOTP_CFG3);
		iounmap(base);
	}

	/*
	 * Speed GRADING[1:0] defines the max speed of ARM:
	 * 2b'00: Reserved;
	 * 2b'01: 528000000Hz;
	 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
	 * 2b'11: 900000000Hz on i.MX6ULL only;
	 * We need to set the max speed of ARM according to fuse map.
	 */
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (of_machine_is_compatible("fsl,imx6ul")) {
		if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
			if (dev_pm_opp_disable(dev, 696000000))
				dev_warn(dev, "failed to disable 696MHz OPP\n");
	}

	if (of_machine_is_compatible("fsl,imx6ull")) {
		if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
			if (dev_pm_opp_disable(dev, 792000000))
				dev_warn(dev, "failed to disable 792MHz OPP\n");

		if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
			if (dev_pm_opp_disable(dev, 900000000))
				dev_warn(dev, "failed to disable 900MHz OPP\n");
	}

	return ret;
}

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull"))
		num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	else
		num_clks = IMX6Q_CPUFREQ_CLK_NUM;

	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	if (ret)
		goto put_node;

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		dev_dbg(cpu_dev, "regulators not ready, defer\n");
		goto put_reg;
	}
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	ret = dev_pm_opp_of_add_table(cpu_dev);
	if (ret < 0) {
		dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
		goto put_reg;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		ret = imx6ul_opp_check_speed_grading(cpu_dev);
		if (ret) {
			if (ret == -EPROBE_DEFER)
				goto put_node;

			dev_err(cpu_dev, "failed to read ocotp: %d\n",
				ret);
			goto put_node;
		}
	} else {
		imx6q_opp_check_speed_grading(cpu_dev);
	}

	/* Because we have added the OPPs here, we must free them */
	free_opp = true;
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = num;
		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
		goto out_free_opp;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_free_opp;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
				     GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	max_freq = freq_table[--num].frequency;
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_opp:
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);
put_node:
	of_node_put(np);

	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);

	clk_bulk_put(num_clks, clks);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_ALIAS("platform:imx6q-cpufreq");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1dd538f0 SG	2	/*
1dd538f0 SG	3	* Copyright (C) 2013 Freescale Semiconductor, Inc.
1dd538f0 SG	4	*/
	5
	6	#include <linux/clk.h>
b494b48d	7	#include <linux/cpu.h>
1dd538f0	8	#include <linux/cpufreq.h>
1dd538f0 SG	9	#include <linux/err.h>
1dd538f0 SG	10	#include <linux/module.h>
2733fb0d	11	#include <linux/nvmem-consumer.h>
1dd538f0	12	#include <linux/of.h>
2b3d58a3	13	#include <linux/of_address.h>
e4db1c74	14	#include <linux/pm_opp.h>
1dd538f0 SG	15	#include <linux/platform_device.h>
	16	#include <linux/regulator/consumer.h>
	17
	18	#define PU_SOC_VOLTAGE_NORMAL 1250000
	19	#define PU_SOC_VOLTAGE_HIGH 1275000
	20	#define FREQ_1P2_GHZ 1200000000
	21
	22	static struct regulator *arm_reg;
	23	static struct regulator *pu_reg;
	24	static struct regulator *soc_reg;
	25
2332bd04 DA	26	enum IMX6_CPUFREQ_CLKS {
	27	ARM,
	28	PLL1_SYS,
	29	STEP,
	30	PLL1_SW,
	31	PLL2_PFD2_396M,
	32	/* MX6UL requires two more clks */
	33	PLL2_BUS,
	34	SECONDARY_SEL,
	35	};
	36	#define IMX6Q_CPUFREQ_CLK_NUM 5
	37	#define IMX6UL_CPUFREQ_CLK_NUM 7
	38
	39	static int num_clks;
	40	static struct clk_bulk_data clks[] = {
	41	{ .id = "arm" },
	42	{ .id = "pll1_sys" },
	43	{ .id = "step" },
	44	{ .id = "pll1_sw" },
	45	{ .id = "pll2_pfd2_396m" },
	46	{ .id = "pll2_bus" },
	47	{ .id = "secondary_sel" },
	48	};
a35fc5a3	49
1dd538f0	50	static struct device *cpu_dev;
cc87b8a8	51	static bool free_opp;
1dd538f0	52	static struct cpufreq_frequency_table *freq_table;
8d768cdc	53	static unsigned int max_freq;
1dd538f0 SG	54	static unsigned int transition_latency;
1dd538f0 SG	55
b4573d1d AH	56	static u32 *imx6_soc_volt;
	57	static u32 soc_opp_count;
	58
9c0ebcf7	59	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	60	{
47d43ba7	61	struct dev_pm_opp *opp;
1dd538f0	62	unsigned long freq_hz, volt, volt_old;
d4019f0a	63	unsigned int old_freq, new_freq;
fded5fc8	64	bool pll1_sys_temp_enabled = false;
1dd538f0 SG	65	int ret;
1dd538f0 SG	66
d4019f0a VK	67	new_freq = freq_table[index].frequency;
d4019f0a VK	68	freq_hz = new_freq * 1000;
2332bd04	69	old_freq = clk_get_rate(clks[ARM].clk) / 1000;
1dd538f0	70
5d4879cd	71	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0	72	if (IS_ERR(opp)) {
1dd538f0 SG	73	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	74	return PTR_ERR(opp);
	75	}
	76
5d4879cd	77	volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	78	dev_pm_opp_put(opp);
8a31d9d9 VK	79
1dd538f0 SG	80	volt_old = regulator_get_voltage(arm_reg);
	81
	82	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	83	old_freq / 1000, volt_old / 1000,
d4019f0a VK	84	new_freq / 1000, volt / 1000);
5a571c35	85
1dd538f0	86	/* scaling up? scale voltage before frequency */
d4019f0a	87	if (new_freq > old_freq) {
22d0628a AH	88	if (!IS_ERR(pu_reg)) {
	89	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	90	if (ret) {
	91	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	92	return ret;
	93	}
b4573d1d AH	94	}
	95	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	96	if (ret) {
	97	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	98	return ret;
	99	}
1dd538f0 SG	100	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	101	if (ret) {
	102	dev_err(cpu_dev,
	103	"failed to scale vddarm up: %d\n", ret);
d4019f0a	104	return ret;
1dd538f0	105	}
1dd538f0 SG	106	}
	107
	108	/*
	109	* The setpoints are selected per PLL/PDF frequencies, so we need to
	110	* reprogram PLL for frequency scaling. The procedure of reprogramming
	111	* PLL1 is as below.
a35fc5a3 BP	112	* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	113	* flow is slightly different from other i.MX6 OSC.
	114	* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
1dd538f0 SG	115	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	116	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	117	* - Disable pll2_pfd2_396m_clk
	118	*/
3fafb4e7 OP	119	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	120	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	121	/*
	122	* When changing pll1_sw_clk's parent to pll1_sys_clk,
	123	* CPU may run at higher than 528MHz, this will lead to
	124	* the system unstable if the voltage is lower than the
	125	* voltage of 528MHz, so lower the CPU frequency to one
	126	* half before changing CPU frequency.
	127	*/
2332bd04 DA	128	clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
	129	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	130	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
	131	clk_set_parent(clks[SECONDARY_SEL].clk,
	132	clks[PLL2_BUS].clk);
a35fc5a3	133	else
2332bd04 DA	134	clk_set_parent(clks[SECONDARY_SEL].clk,
	135	clks[PLL2_PFD2_396M].clk);
	136	clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
	137	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
5028f5d2 AH	138	if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
	139	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	140	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
	141	}
a35fc5a3	142	} else {
2332bd04 DA	143	clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
	144	clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
	145	if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
	146	clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
	147	clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
fded5fc8 LC	148	} else {
	149	/* pll1_sys needs to be enabled for divider rate change to work. */
	150	pll1_sys_temp_enabled = true;
2332bd04	151	clk_prepare_enable(clks[PLL1_SYS].clk);
a35fc5a3	152	}
1dd538f0 SG	153	}
	154
	155	/* Ensure the arm clock divider is what we expect */
2332bd04	156	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
1dd538f0	157	if (ret) {
6ef28a04 AH	158	int ret1;
6ef28a04 AH	159
1dd538f0	160	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
6ef28a04 AH	161	ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
	162	if (ret1)
	163	dev_warn(cpu_dev,
	164	"failed to restore vddarm voltage: %d\n", ret1);
d4019f0a	165	return ret;
1dd538f0 SG	166	}
1dd538f0 SG	167
fded5fc8 LC	168	/* PLL1 is only needed until after ARM-PODF is set. */
fded5fc8 LC	169	if (pll1_sys_temp_enabled)
2332bd04	170	clk_disable_unprepare(clks[PLL1_SYS].clk);
fded5fc8	171
1dd538f0	172	/* scaling down? scale voltage after frequency */
d4019f0a	173	if (new_freq < old_freq) {
1dd538f0	174	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
58ad4e61	175	if (ret)
1dd538f0 SG	176	dev_warn(cpu_dev,
1dd538f0 SG	177	"failed to scale vddarm down: %d\n", ret);
b4573d1d	178	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
58ad4e61	179	if (ret)
b4573d1d	180	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
22d0628a AH	181	if (!IS_ERR(pu_reg)) {
22d0628a AH	182	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
58ad4e61	183	if (ret)
22d0628a	184	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
1dd538f0 SG	185	}
	186	}
	187
d4019f0a	188	return 0;
1dd538f0 SG	189	}
	190
	191	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	192	{
2332bd04	193	policy->clk = clks[ARM].clk;
c4dcc8a1	194	cpufreq_generic_init(policy, freq_table, transition_latency);
8d768cdc	195	policy->suspend_freq = max_freq;
3ad63a6b	196	dev_pm_opp_of_register_em(policy->cpus);
5aa1599f	197
c4dcc8a1	198	return 0;
1dd538f0 SG	199	}
1dd538f0 SG	200
1dd538f0	201	static struct cpufreq_driver imx6q_cpufreq_driver = {
4b498869 AK	202	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK \|
4b498869 AK	203	CPUFREQ_IS_COOLING_DEV,
4f6ba385	204	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	205	.target_index = imx6q_set_target,
652ed95d	206	.get = cpufreq_generic_get,
1dd538f0	207	.init = imx6q_cpufreq_init,
1dd538f0	208	.name = "imx6q-cpufreq",
4f6ba385	209	.attr = cpufreq_generic_attr,
5aa1599f	210	.suspend = cpufreq_generic_suspend,
1dd538f0 SG	211	};
1dd538f0 SG	212
2b3d58a3 FE	213	#define OCOTP_CFG3 0x440
	214	#define OCOTP_CFG3_SPEED_SHIFT 16
	215	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	216	#define OCOTP_CFG3_SPEED_996MHZ 0x2
	217	#define OCOTP_CFG3_SPEED_852MHZ 0x1
	218
	219	static void imx6q_opp_check_speed_grading(struct device *dev)
	220	{
	221	struct device_node *np;
	222	void __iomem *base;
	223	u32 val;
	224
	225	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	226	if (!np)
	227	return;
	228
	229	base = of_iomap(np, 0);
	230	if (!base) {
	231	dev_err(dev, "failed to map ocotp\n");
	232	goto put_node;
	233	}
	234
	235	/*
	236	* SPEED_GRADING[1:0] defines the max speed of ARM:
	237	* 2b'11: 1200000000Hz;
	238	* 2b'10: 996000000Hz;
	239	* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
	240	* 2b'00: 792000000Hz;
	241	* We need to set the max speed of ARM according to fuse map.
	242	*/
	243	val = readl_relaxed(base + OCOTP_CFG3);
	244	val >>= OCOTP_CFG3_SPEED_SHIFT;
	245	val &= 0x3;
	246
2b3d58a3 FE	247	if (val < OCOTP_CFG3_SPEED_996MHZ)
	248	if (dev_pm_opp_disable(dev, 996000000))
	249	dev_warn(dev, "failed to disable 996MHz OPP\n");
ccc153a6 LS	250
	251	if (of_machine_is_compatible("fsl,imx6q") \|\|
	252	of_machine_is_compatible("fsl,imx6qp")) {
2b3d58a3 FE	253	if (val != OCOTP_CFG3_SPEED_852MHZ)
	254	if (dev_pm_opp_disable(dev, 852000000))
	255	dev_warn(dev, "failed to disable 852MHz OPP\n");
ccc153a6 LS	256	if (val != OCOTP_CFG3_SPEED_1P2GHZ)
	257	if (dev_pm_opp_disable(dev, 1200000000))
	258	dev_warn(dev, "failed to disable 1.2GHz OPP\n");
2b3d58a3 FE	259	}
	260	iounmap(base);
	261	put_node:
	262	of_node_put(np);
	263	}
	264
5028f5d2	265	#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
0aa9abd4 SS	266	#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
0aa9abd4 SS	267	#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
5028f5d2	268
2733fb0d	269	static int imx6ul_opp_check_speed_grading(struct device *dev)
5028f5d2	270	{
5028f5d2	271	u32 val;
2733fb0d	272	int ret = 0;
5028f5d2	273
2733fb0d AH	274	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
	275	ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
	276	if (ret)
	277	return ret;
	278	} else {
	279	struct device_node *np;
	280	void __iomem *base;
	281
	282	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
	283	if (!np)
	284	return -ENOENT;
	285
	286	base = of_iomap(np, 0);
	287	of_node_put(np);
	288	if (!base) {
	289	dev_err(dev, "failed to map ocotp\n");
	290	return -EFAULT;
	291	}
5028f5d2	292
2733fb0d AH	293	val = readl_relaxed(base + OCOTP_CFG3);
2733fb0d AH	294	iounmap(base);
5028f5d2 AH	295	}
	296
	297	/*
	298	* Speed GRADING[1:0] defines the max speed of ARM:
	299	* 2b'00: Reserved;
	300	* 2b'01: 528000000Hz;
0aa9abd4 SS	301	* 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
0aa9abd4 SS	302	* 2b'11: 900000000Hz on i.MX6ULL only;
5028f5d2 AH	303	* We need to set the max speed of ARM according to fuse map.
5028f5d2 AH	304	*/
5028f5d2 AH	305	val >>= OCOTP_CFG3_SPEED_SHIFT;
5028f5d2 AH	306	val &= 0x3;
0aa9abd4 SS	307
	308	if (of_machine_is_compatible("fsl,imx6ul")) {
	309	if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
	310	if (dev_pm_opp_disable(dev, 696000000))
	311	dev_warn(dev, "failed to disable 696MHz OPP\n");
	312	}
	313
	314	if (of_machine_is_compatible("fsl,imx6ull")) {
	315	if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
	316	if (dev_pm_opp_disable(dev, 792000000))
	317	dev_warn(dev, "failed to disable 792MHz OPP\n");
	318
	319	if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
	320	if (dev_pm_opp_disable(dev, 900000000))
	321	dev_warn(dev, "failed to disable 900MHz OPP\n");
	322	}
	323
2733fb0d	324	return ret;
5028f5d2 AH	325	}
5028f5d2 AH	326
1dd538f0 SG	327	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	328	{
	329	struct device_node *np;
47d43ba7	330	struct dev_pm_opp *opp;
1dd538f0 SG	331	unsigned long min_volt, max_volt;
1dd538f0 SG	332	int num, ret;
b4573d1d AH	333	const struct property *prop;
	334	const __be32 *val;
	335	u32 nr, i, j;
1dd538f0	336
b494b48d SK	337	cpu_dev = get_cpu_device(0);
	338	if (!cpu_dev) {
	339	pr_err("failed to get cpu0 device\n");
	340	return -ENODEV;
	341	}
1dd538f0	342
cdc58d60	343	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	344	if (!np) {
	345	dev_err(cpu_dev, "failed to find cpu0 node\n");
	346	return -ENOENT;
	347	}
	348
3fafb4e7	349	if (of_machine_is_compatible("fsl,imx6ul") \|\|
2332bd04 DA	350	of_machine_is_compatible("fsl,imx6ull"))
	351	num_clks = IMX6UL_CPUFREQ_CLK_NUM;
	352	else
	353	num_clks = IMX6Q_CPUFREQ_CLK_NUM;
	354
	355	ret = clk_bulk_get(cpu_dev, num_clks, clks);
	356	if (ret)
	357	goto put_node;
a35fc5a3	358
f8269c19	359	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	360	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	361	soc_reg = regulator_get(cpu_dev, "soc");
54cad2fc IT	362	if (PTR_ERR(arm_reg) == -EPROBE_DEFER \|\|
	363	PTR_ERR(soc_reg) == -EPROBE_DEFER \|\|
	364	PTR_ERR(pu_reg) == -EPROBE_DEFER) {
	365	ret = -EPROBE_DEFER;
	366	dev_dbg(cpu_dev, "regulators not ready, defer\n");
	367	goto put_reg;
	368	}
22d0628a	369	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	370	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	371	ret = -ENOENT;
f8269c19	372	goto put_reg;
1dd538f0 SG	373	}
1dd538f0 SG	374
2b3d58a3 FE	375	ret = dev_pm_opp_of_add_table(cpu_dev);
	376	if (ret < 0) {
	377	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
	378	goto put_reg;
	379	}
20b7cbe2	380
0aa9abd4	381	if (of_machine_is_compatible("fsl,imx6ul") \|\|
2733fb0d AH	382	of_machine_is_compatible("fsl,imx6ull")) {
2733fb0d AH	383	ret = imx6ul_opp_check_speed_grading(cpu_dev);
2733fb0d	384	if (ret) {
cccf6ae5	385	if (ret == -EPROBE_DEFER)
ddb64c5d	386	goto put_node;
cccf6ae5	387
2733fb0d AH	388	dev_err(cpu_dev, "failed to read ocotp: %d\n",
2733fb0d AH	389	ret);
ddb64c5d	390	goto put_node;
2733fb0d AH	391	}
2733fb0d AH	392	} else {
5028f5d2	393	imx6q_opp_check_speed_grading(cpu_dev);
2733fb0d	394	}
cc87b8a8	395
2b3d58a3 FE	396	/* Because we have added the OPPs here, we must free them */
	397	free_opp = true;
	398	num = dev_pm_opp_get_opp_count(cpu_dev);
	399	if (num < 0) {
	400	ret = num;
	401	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
	402	goto out_free_opp;
1dd538f0 SG	403	}
1dd538f0 SG	404
5d4879cd	405	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	406	if (ret) {
1dd538f0 SG	407	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
eafca851	408	goto out_free_opp;
1dd538f0 SG	409	}
1dd538f0 SG	410
b4573d1d	411	/* Make imx6_soc_volt array's size same as arm opp number */
a86854d0 KC	412	imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
a86854d0 KC	413	GFP_KERNEL);
b4573d1d AH	414	if (imx6_soc_volt == NULL) {
	415	ret = -ENOMEM;
	416	goto free_freq_table;
	417	}
	418
	419	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	420	if (!prop \|\| !prop->value)
	421	goto soc_opp_out;
	422
	423	/*
	424	* Each OPP is a set of tuples consisting of frequency and
	425	* voltage like <freq-kHz vol-uV>.
	426	*/
	427	nr = prop->length / sizeof(u32);
	428	if (nr % 2 \|\| (nr / 2) < num)
	429	goto soc_opp_out;
	430
	431	for (j = 0; j < num; j++) {
	432	val = prop->value;
	433	for (i = 0; i < nr / 2; i++) {
	434	unsigned long freq = be32_to_cpup(val++);
	435	unsigned long volt = be32_to_cpup(val++);
	436	if (freq_table[j].frequency == freq) {
	437	imx6_soc_volt[soc_opp_count++] = volt;
	438	break;
	439	}
	440	}
	441	}
	442
	443	soc_opp_out:
	444	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	445	if (soc_opp_count != num) {
	446	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	447	for (j = 0; j < num; j++)
	448	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	449	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	450	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	451	}
	452
1dd538f0 SG	453	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	454	transition_latency = CPUFREQ_ETERNAL;
	455
b4573d1d AH	456	/*
	457	* Calculate the ramp time for max voltage change in the
	458	* VDDSOC and VDDPU regulators.
	459	*/
	460	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	461	if (ret > 0)
	462	transition_latency += ret * 1000;
22d0628a AH	463	if (!IS_ERR(pu_reg)) {
	464	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	465	if (ret > 0)
	466	transition_latency += ret * 1000;
	467	}
b4573d1d	468
1dd538f0 SG	469	/*
	470	* OPP is maintained in order of increasing frequency, and
	471	* freq_table initialised from OPP is therefore sorted in the
	472	* same order.
	473	*/
8d768cdc	474	max_freq = freq_table[--num].frequency;
5d4879cd	475	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	476	freq_table[0].frequency * 1000, true);
5d4879cd	477	min_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	478	dev_pm_opp_put(opp);
8d768cdc	479	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
5d4879cd	480	max_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	481	dev_pm_opp_put(opp);
8a31d9d9 VK	482
1dd538f0 SG	483	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	484	if (ret > 0)
	485	transition_latency += ret * 1000;
	486
1dd538f0 SG	487	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	488	if (ret) {
	489	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	490	goto free_freq_table;
	491	}
	492
	493	of_node_put(np);
	494	return 0;
	495
	496	free_freq_table:
5d4879cd	497	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8 VK	498	out_free_opp:
cc87b8a8 VK	499	if (free_opp)
8f8d37b2	500	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19 PZ	501	put_reg:
	502	if (!IS_ERR(arm_reg))
	503	regulator_put(arm_reg);
	504	if (!IS_ERR(pu_reg))
	505	regulator_put(pu_reg);
	506	if (!IS_ERR(soc_reg))
	507	regulator_put(soc_reg);
2332bd04 DA	508
	509	clk_bulk_put(num_clks, clks);
	510	put_node:
1dd538f0	511	of_node_put(np);
2332bd04	512
1dd538f0 SG	513	return ret;
	514	}
	515
	516	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	517	{
	518	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	519	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8	520	if (free_opp)
8f8d37b2	521	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19	522	regulator_put(arm_reg);
22d0628a AH	523	if (!IS_ERR(pu_reg))
22d0628a AH	524	regulator_put(pu_reg);
f8269c19	525	regulator_put(soc_reg);
2332bd04 DA	526
2332bd04 DA	527	clk_bulk_put(num_clks, clks);
1dd538f0 SG	528
	529	return 0;
	530	}
	531
	532	static struct platform_driver imx6q_cpufreq_platdrv = {
	533	.driver = {
	534	.name = "imx6q-cpufreq",
1dd538f0 SG	535	},
	536	.probe = imx6q_cpufreq_probe,
	537	.remove = imx6q_cpufreq_remove,
	538	};
	539	module_platform_driver(imx6q_cpufreq_platdrv);
	540
d0404738	541	MODULE_ALIAS("platform:imx6q-cpufreq");
1dd538f0 SG	542	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	543	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	544	MODULE_LICENSE("GPL");