[linux-2.6-block.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

static struct clk *arm_clk;
static struct clk *pll1_sys_clk;
static struct clk *pll1_sw_clk;
static struct clk *step_clk;
static struct clk *pll2_pfd2_396m_clk;

/* clk used by i.MX6UL */
static struct clk *pll2_bus_clk;
static struct clk *secondary_sel_clk;

static struct device *cpu_dev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	bool pll1_sys_temp_enabled = false;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(arm_clk) / 1000;

	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	 * flow is slightly different from other i.MX6 OSC.
	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		/*
		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
		 * CPU may run at higher than 528MHz, this will lead to
		 * the system unstable if the voltage is lower than the
		 * voltage of 528MHz, so lower the CPU frequency to one
		 * half before changing CPU frequency.
		 */
		clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
			clk_set_parent(secondary_sel_clk, pll2_bus_clk);
		else
			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
		clk_set_parent(step_clk, secondary_sel_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
	} else {
		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
		clk_set_parent(pll1_sw_clk, step_clk);
		if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
			clk_set_rate(pll1_sys_clk, new_freq * 1000);
			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
		} else {
			/* pll1_sys needs to be enabled for divider rate change to work. */
			pll1_sys_temp_enabled = true;
			clk_prepare_enable(pll1_sys_clk);
		}
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, new_freq * 1000);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		regulator_set_voltage_tol(arm_reg, volt_old, 0);
		return ret;
	}

	/* PLL1 is only needed until after ARM-PODF is set. */
	if (pll1_sys_temp_enabled)
		clk_disable_unprepare(pll1_sys_clk);

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
			ret = 0;
		}
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
				ret = 0;
			}
		}
	}

	return 0;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->clk = arm_clk;
	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	policy->suspend_freq = policy->max;

	return ret;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
	.suspend = cpufreq_generic_suspend,
};

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	arm_clk = clk_get(cpu_dev, "arm");
	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	step_clk = clk_get(cpu_dev, "step");
	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
		dev_err(cpu_dev, "failed to get clocks\n");
		ret = -ENOENT;
		goto put_clk;
	}

	if (of_machine_is_compatible("fsl,imx6ul") ||
	    of_machine_is_compatible("fsl,imx6ull")) {
		pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
		secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
		if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
			dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
			ret = -ENOENT;
			goto put_clk;
		}
	}

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		dev_dbg(cpu_dev, "regulators not ready, defer\n");
		goto put_reg;
	}
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	/*
	 * We expect an OPP table supplied by platform.
	 * Just, incase the platform did not supply the OPP
	 * table, it will try to get it.
	 */
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = dev_pm_opp_of_add_table(cpu_dev);
		if (ret < 0) {
			dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
			goto put_reg;
		}

		/* Because we have added the OPPs here, we must free them */
		free_opp = true;

		num = dev_pm_opp_get_opp_count(cpu_dev);
		if (num < 0) {
			ret = num;
			dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
			goto out_free_opp;
		}
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_free_opp;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[--num].frequency * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_opp:
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);
put_clk:
	if (!IS_ERR(arm_clk))
		clk_put(arm_clk);
	if (!IS_ERR(pll1_sys_clk))
		clk_put(pll1_sys_clk);
	if (!IS_ERR(pll1_sw_clk))
		clk_put(pll1_sw_clk);
	if (!IS_ERR(step_clk))
		clk_put(step_clk);
	if (!IS_ERR(pll2_pfd2_396m_clk))
		clk_put(pll2_pfd2_396m_clk);
	if (!IS_ERR(pll2_bus_clk))
		clk_put(pll2_bus_clk);
	if (!IS_ERR(secondary_sel_clk))
		clk_put(secondary_sel_clk);
	of_node_put(np);
	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	if (free_opp)
		dev_pm_opp_of_remove_table(cpu_dev);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);
	clk_put(arm_clk);
	clk_put(pll1_sys_clk);
	clk_put(pll1_sw_clk);
	clk_put(step_clk);
	clk_put(pll2_pfd2_396m_clk);
	clk_put(pll2_bus_clk);
	clk_put(secondary_sel_clk);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0	11	#include <linux/cpufreq.h>
1dd538f0 SG	12	#include <linux/err.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
e4db1c74	15	#include <linux/pm_opp.h>
1dd538f0 SG	16	#include <linux/platform_device.h>
	17	#include <linux/regulator/consumer.h>
	18
	19	#define PU_SOC_VOLTAGE_NORMAL 1250000
	20	#define PU_SOC_VOLTAGE_HIGH 1275000
	21	#define FREQ_1P2_GHZ 1200000000
	22
	23	static struct regulator *arm_reg;
	24	static struct regulator *pu_reg;
	25	static struct regulator *soc_reg;
	26
	27	static struct clk *arm_clk;
	28	static struct clk *pll1_sys_clk;
	29	static struct clk *pll1_sw_clk;
	30	static struct clk *step_clk;
	31	static struct clk *pll2_pfd2_396m_clk;
	32
a35fc5a3 BP	33	/* clk used by i.MX6UL */
	34	static struct clk *pll2_bus_clk;
	35	static struct clk *secondary_sel_clk;
	36
1dd538f0	37	static struct device *cpu_dev;
cc87b8a8	38	static bool free_opp;
1dd538f0 SG	39	static struct cpufreq_frequency_table *freq_table;
	40	static unsigned int transition_latency;
	41
b4573d1d AH	42	static u32 *imx6_soc_volt;
	43	static u32 soc_opp_count;
	44
9c0ebcf7	45	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	46	{
47d43ba7	47	struct dev_pm_opp *opp;
1dd538f0	48	unsigned long freq_hz, volt, volt_old;
d4019f0a	49	unsigned int old_freq, new_freq;
fded5fc8	50	bool pll1_sys_temp_enabled = false;
1dd538f0 SG	51	int ret;
1dd538f0 SG	52
d4019f0a VK	53	new_freq = freq_table[index].frequency;
	54	freq_hz = new_freq * 1000;
	55	old_freq = clk_get_rate(arm_clk) / 1000;
1dd538f0	56
5d4879cd	57	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0	58	if (IS_ERR(opp)) {
1dd538f0 SG	59	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	60	return PTR_ERR(opp);
	61	}
	62
5d4879cd	63	volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	64	dev_pm_opp_put(opp);
8a31d9d9 VK	65
1dd538f0 SG	66	volt_old = regulator_get_voltage(arm_reg);
	67
	68	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	69	old_freq / 1000, volt_old / 1000,
d4019f0a VK	70	new_freq / 1000, volt / 1000);
5a571c35	71
1dd538f0	72	/* scaling up? scale voltage before frequency */
d4019f0a	73	if (new_freq > old_freq) {
22d0628a AH	74	if (!IS_ERR(pu_reg)) {
	75	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	76	if (ret) {
	77	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	78	return ret;
	79	}
b4573d1d AH	80	}
	81	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	82	if (ret) {
	83	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	84	return ret;
	85	}
1dd538f0 SG	86	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	87	if (ret) {
	88	dev_err(cpu_dev,
	89	"failed to scale vddarm up: %d\n", ret);
d4019f0a	90	return ret;
1dd538f0	91	}
1dd538f0 SG	92	}
	93
	94	/*
	95	* The setpoints are selected per PLL/PDF frequencies, so we need to
	96	* reprogram PLL for frequency scaling. The procedure of reprogramming
	97	* PLL1 is as below.
a35fc5a3 BP	98	* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
	99	* flow is slightly different from other i.MX6 OSC.
	100	* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
1dd538f0 SG	101	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	102	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	103	* - Disable pll2_pfd2_396m_clk
	104	*/
3fafb4e7 OP	105	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	106	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	107	/*
	108	* When changing pll1_sw_clk's parent to pll1_sys_clk,
	109	* CPU may run at higher than 528MHz, this will lead to
	110	* the system unstable if the voltage is lower than the
	111	* voltage of 528MHz, so lower the CPU frequency to one
	112	* half before changing CPU frequency.
	113	*/
	114	clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
1dd538f0	115	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
a35fc5a3 BP	116	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
	117	clk_set_parent(secondary_sel_clk, pll2_bus_clk);
	118	else
	119	clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
	120	clk_set_parent(step_clk, secondary_sel_clk);
	121	clk_set_parent(pll1_sw_clk, step_clk);
	122	} else {
	123	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	124	clk_set_parent(pll1_sw_clk, step_clk);
	125	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
	126	clk_set_rate(pll1_sys_clk, new_freq * 1000);
	127	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
fded5fc8 LC	128	} else {
	129	/* pll1_sys needs to be enabled for divider rate change to work. */
	130	pll1_sys_temp_enabled = true;
	131	clk_prepare_enable(pll1_sys_clk);
a35fc5a3	132	}
1dd538f0 SG	133	}
	134
	135	/* Ensure the arm clock divider is what we expect */
d4019f0a	136	ret = clk_set_rate(arm_clk, new_freq * 1000);
1dd538f0 SG	137	if (ret) {
	138	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
	139	regulator_set_voltage_tol(arm_reg, volt_old, 0);
d4019f0a	140	return ret;
1dd538f0 SG	141	}
1dd538f0 SG	142
fded5fc8 LC	143	/* PLL1 is only needed until after ARM-PODF is set. */
	144	if (pll1_sys_temp_enabled)
	145	clk_disable_unprepare(pll1_sys_clk);
	146
1dd538f0	147	/* scaling down? scale voltage after frequency */
d4019f0a	148	if (new_freq < old_freq) {
1dd538f0	149	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	150	if (ret) {
1dd538f0 SG	151	dev_warn(cpu_dev,
1dd538f0 SG	152	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	153	ret = 0;
5a571c35 VK	154	}
b4573d1d AH	155	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	156	if (ret) {
	157	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
	158	ret = 0;
	159	}
22d0628a AH	160	if (!IS_ERR(pu_reg)) {
	161	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	162	if (ret) {
	163	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
	164	ret = 0;
	165	}
1dd538f0 SG	166	}
	167	}
	168
d4019f0a	169	return 0;
1dd538f0 SG	170	}
	171
	172	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	173	{
5aa1599f LC	174	int ret;
5aa1599f LC	175
652ed95d	176	policy->clk = arm_clk;
5aa1599f LC	177	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	178	policy->suspend_freq = policy->max;
	179
	180	return ret;
1dd538f0 SG	181	}
1dd538f0 SG	182
1dd538f0	183	static struct cpufreq_driver imx6q_cpufreq_driver = {
ae6b4271	184	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
4f6ba385	185	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	186	.target_index = imx6q_set_target,
652ed95d	187	.get = cpufreq_generic_get,
1dd538f0	188	.init = imx6q_cpufreq_init,
1dd538f0	189	.name = "imx6q-cpufreq",
4f6ba385	190	.attr = cpufreq_generic_attr,
5aa1599f	191	.suspend = cpufreq_generic_suspend,
1dd538f0 SG	192	};
	193
	194	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	195	{
	196	struct device_node *np;
47d43ba7	197	struct dev_pm_opp *opp;
1dd538f0 SG	198	unsigned long min_volt, max_volt;
1dd538f0 SG	199	int num, ret;
b4573d1d AH	200	const struct property *prop;
	201	const __be32 *val;
	202	u32 nr, i, j;
1dd538f0	203
b494b48d SK	204	cpu_dev = get_cpu_device(0);
	205	if (!cpu_dev) {
	206	pr_err("failed to get cpu0 device\n");
	207	return -ENODEV;
	208	}
1dd538f0	209
cdc58d60	210	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	211	if (!np) {
	212	dev_err(cpu_dev, "failed to find cpu0 node\n");
	213	return -ENOENT;
	214	}
	215
f8269c19 PZ	216	arm_clk = clk_get(cpu_dev, "arm");
	217	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	218	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	219	step_clk = clk_get(cpu_dev, "step");
	220	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
1dd538f0 SG	221	if (IS_ERR(arm_clk) \|\| IS_ERR(pll1_sys_clk) \|\| IS_ERR(pll1_sw_clk) \|\|
	222	IS_ERR(step_clk) \|\| IS_ERR(pll2_pfd2_396m_clk)) {
	223	dev_err(cpu_dev, "failed to get clocks\n");
	224	ret = -ENOENT;
f8269c19	225	goto put_clk;
1dd538f0 SG	226	}
1dd538f0 SG	227
3fafb4e7 OP	228	if (of_machine_is_compatible("fsl,imx6ul") \|\|
3fafb4e7 OP	229	of_machine_is_compatible("fsl,imx6ull")) {
a35fc5a3 BP	230	pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
	231	secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
	232	if (IS_ERR(pll2_bus_clk) \|\| IS_ERR(secondary_sel_clk)) {
	233	dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
	234	ret = -ENOENT;
	235	goto put_clk;
	236	}
	237	}
	238
f8269c19	239	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	240	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	241	soc_reg = regulator_get(cpu_dev, "soc");
54cad2fc IT	242	if (PTR_ERR(arm_reg) == -EPROBE_DEFER \|\|
	243	PTR_ERR(soc_reg) == -EPROBE_DEFER \|\|
	244	PTR_ERR(pu_reg) == -EPROBE_DEFER) {
	245	ret = -EPROBE_DEFER;
	246	dev_dbg(cpu_dev, "regulators not ready, defer\n");
	247	goto put_reg;
	248	}
22d0628a	249	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	250	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	251	ret = -ENOENT;
f8269c19	252	goto put_reg;
1dd538f0 SG	253	}
1dd538f0 SG	254
20b7cbe2 JT	255	/*
	256	* We expect an OPP table supplied by platform.
	257	* Just, incase the platform did not supply the OPP
	258	* table, it will try to get it.
	259	*/
5d4879cd	260	num = dev_pm_opp_get_opp_count(cpu_dev);
1dd538f0	261	if (num < 0) {
8f8d37b2	262	ret = dev_pm_opp_of_add_table(cpu_dev);
20b7cbe2 JT	263	if (ret < 0) {
20b7cbe2 JT	264	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
f8269c19	265	goto put_reg;
20b7cbe2 JT	266	}
20b7cbe2 JT	267
cc87b8a8 VK	268	/* Because we have added the OPPs here, we must free them */
	269	free_opp = true;
	270
20b7cbe2 JT	271	num = dev_pm_opp_get_opp_count(cpu_dev);
	272	if (num < 0) {
	273	ret = num;
	274	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
cc87b8a8	275	goto out_free_opp;
20b7cbe2	276	}
1dd538f0 SG	277	}
1dd538f0 SG	278
5d4879cd	279	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	280	if (ret) {
1dd538f0 SG	281	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
eafca851	282	goto out_free_opp;
1dd538f0 SG	283	}
1dd538f0 SG	284
b4573d1d AH	285	/* Make imx6_soc_volt array's size same as arm opp number */
	286	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(imx6_soc_volt) num, GFP_KERNEL);
	287	if (imx6_soc_volt == NULL) {
	288	ret = -ENOMEM;
	289	goto free_freq_table;
	290	}
	291
	292	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	293	if (!prop \|\| !prop->value)
	294	goto soc_opp_out;
	295
	296	/*
	297	* Each OPP is a set of tuples consisting of frequency and
	298	* voltage like <freq-kHz vol-uV>.
	299	*/
	300	nr = prop->length / sizeof(u32);
	301	if (nr % 2 \|\| (nr / 2) < num)
	302	goto soc_opp_out;
	303
	304	for (j = 0; j < num; j++) {
	305	val = prop->value;
	306	for (i = 0; i < nr / 2; i++) {
	307	unsigned long freq = be32_to_cpup(val++);
	308	unsigned long volt = be32_to_cpup(val++);
	309	if (freq_table[j].frequency == freq) {
	310	imx6_soc_volt[soc_opp_count++] = volt;
	311	break;
	312	}
	313	}
	314	}
	315
	316	soc_opp_out:
	317	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	318	if (soc_opp_count != num) {
	319	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	320	for (j = 0; j < num; j++)
	321	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	322	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	323	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	324	}
	325
1dd538f0 SG	326	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	327	transition_latency = CPUFREQ_ETERNAL;
	328
b4573d1d AH	329	/*
	330	* Calculate the ramp time for max voltage change in the
	331	* VDDSOC and VDDPU regulators.
	332	*/
	333	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	334	if (ret > 0)
	335	transition_latency += ret * 1000;
22d0628a AH	336	if (!IS_ERR(pu_reg)) {
	337	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	338	if (ret > 0)
	339	transition_latency += ret * 1000;
	340	}
b4573d1d	341
1dd538f0 SG	342	/*
	343	* OPP is maintained in order of increasing frequency, and
	344	* freq_table initialised from OPP is therefore sorted in the
	345	* same order.
	346	*/
5d4879cd	347	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	348	freq_table[0].frequency * 1000, true);
5d4879cd	349	min_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	350	dev_pm_opp_put(opp);
5d4879cd	351	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	352	freq_table[--num].frequency * 1000, true);
5d4879cd	353	max_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9 VK	354	dev_pm_opp_put(opp);
8a31d9d9 VK	355
1dd538f0 SG	356	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	357	if (ret > 0)
	358	transition_latency += ret * 1000;
	359
1dd538f0 SG	360	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	361	if (ret) {
	362	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	363	goto free_freq_table;
	364	}
	365
	366	of_node_put(np);
	367	return 0;
	368
	369	free_freq_table:
5d4879cd	370	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8 VK	371	out_free_opp:
cc87b8a8 VK	372	if (free_opp)
8f8d37b2	373	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19 PZ	374	put_reg:
	375	if (!IS_ERR(arm_reg))
	376	regulator_put(arm_reg);
	377	if (!IS_ERR(pu_reg))
	378	regulator_put(pu_reg);
	379	if (!IS_ERR(soc_reg))
	380	regulator_put(soc_reg);
	381	put_clk:
	382	if (!IS_ERR(arm_clk))
	383	clk_put(arm_clk);
	384	if (!IS_ERR(pll1_sys_clk))
	385	clk_put(pll1_sys_clk);
	386	if (!IS_ERR(pll1_sw_clk))
	387	clk_put(pll1_sw_clk);
	388	if (!IS_ERR(step_clk))
	389	clk_put(step_clk);
	390	if (!IS_ERR(pll2_pfd2_396m_clk))
	391	clk_put(pll2_pfd2_396m_clk);
a35fc5a3 BP	392	if (!IS_ERR(pll2_bus_clk))
	393	clk_put(pll2_bus_clk);
	394	if (!IS_ERR(secondary_sel_clk))
	395	clk_put(secondary_sel_clk);
1dd538f0 SG	396	of_node_put(np);
	397	return ret;
	398	}
	399
	400	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	401	{
	402	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	403	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
cc87b8a8	404	if (free_opp)
8f8d37b2	405	dev_pm_opp_of_remove_table(cpu_dev);
f8269c19	406	regulator_put(arm_reg);
22d0628a AH	407	if (!IS_ERR(pu_reg))
22d0628a AH	408	regulator_put(pu_reg);
f8269c19 PZ	409	regulator_put(soc_reg);
	410	clk_put(arm_clk);
	411	clk_put(pll1_sys_clk);
	412	clk_put(pll1_sw_clk);
	413	clk_put(step_clk);
	414	clk_put(pll2_pfd2_396m_clk);
a35fc5a3 BP	415	clk_put(pll2_bus_clk);
a35fc5a3 BP	416	clk_put(secondary_sel_clk);
1dd538f0 SG	417
	418	return 0;
	419	}
	420
	421	static struct platform_driver imx6q_cpufreq_platdrv = {
	422	.driver = {
	423	.name = "imx6q-cpufreq",
1dd538f0 SG	424	},
	425	.probe = imx6q_cpufreq_probe,
	426	.remove = imx6q_cpufreq_remove,
	427	};
	428	module_platform_driver(imx6q_cpufreq_platdrv);
	429
	430	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	431	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	432	MODULE_LICENSE("GPL");