Merge tag 'pm+acpi-3.13-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6-block.git] / drivers / cpufreq / exynos4210-cpufreq.c
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f7d77079 1/*
7d30e8b3 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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3 * http://www.samsung.com
4 *
a125a17f 5 * EXYNOS4210 - CPU frequency scaling support
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6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
6c523c61 12#include <linux/module.h>
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13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/slab.h>
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18#include <linux/cpufreq.h>
19
f40f91fe 20#include <mach/regs-clock.h>
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21
22#include "exynos-cpufreq.h"
f40f91fe 23
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24static struct clk *cpu_clk;
25static struct clk *moutcore;
26static struct clk *mout_mpll;
27static struct clk *mout_apll;
28
9d0554ff 29static unsigned int exynos4210_volt_table[] = {
a125a17f 30 1250000, 1150000, 1050000, 975000, 950000,
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31};
32
a125a17f 33static struct cpufreq_frequency_table exynos4210_freq_table[] = {
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34 {L0, 1200 * 1000},
35 {L1, 1000 * 1000},
36 {L2, 800 * 1000},
37 {L3, 500 * 1000},
38 {L4, 200 * 1000},
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39 {0, CPUFREQ_TABLE_END},
40};
41
9d0554ff 42static struct apll_freq apll_freq_4210[] = {
f40f91fe 43 /*
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44 * values:
45 * freq
46 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
47 * clock divider for COPY, HPM, RESERVED
48 * PLL M, P, S
f40f91fe 49 */
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50 APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
51 APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
52 APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
53 APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
54 APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
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55};
56
a125a17f 57static void exynos4210_set_clkdiv(unsigned int div_index)
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58{
59 unsigned int tmp;
60
61 /* Change Divider - CPU0 */
62
9d0554ff 63 tmp = apll_freq_4210[div_index].clk_div_cpu0;
f40f91fe 64
09cee1ab 65 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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66
67 do {
09cee1ab 68 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
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69 } while (tmp & 0x1111111);
70
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71 /* Change Divider - CPU1 */
72
9d0554ff 73 tmp = apll_freq_4210[div_index].clk_div_cpu1;
bf5ce054 74
09cee1ab 75 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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76
77 do {
09cee1ab 78 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
bf5ce054 79 } while (tmp & 0x11);
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80}
81
a125a17f 82static void exynos4210_set_apll(unsigned int index)
bf5ce054 83{
7ad65d59 84 unsigned int tmp, freq = apll_freq_4210[index].freq;
bf5ce054 85
7ad65d59 86 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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87 clk_set_parent(moutcore, mout_mpll);
88
89 do {
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90 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
91 >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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92 tmp &= 0x7;
93 } while (tmp != 0x2);
94
7ad65d59 95 clk_set_rate(mout_apll, freq * 1000);
bf5ce054 96
7ad65d59 97 /* MUX_CORE_SEL = APLL */
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98 clk_set_parent(moutcore, mout_apll);
99
100 do {
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101 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
102 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
103 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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104}
105
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106static void exynos4210_set_frequency(unsigned int old_index,
107 unsigned int new_index)
bf5ce054 108{
bf5ce054 109 if (old_index > new_index) {
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110 exynos4210_set_clkdiv(new_index);
111 exynos4210_set_apll(new_index);
27f805dc 112 } else if (old_index < new_index) {
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113 exynos4210_set_apll(new_index);
114 exynos4210_set_clkdiv(new_index);
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115 }
116}
117
a125a17f 118int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
f40f91fe 119{
a125a17f 120 unsigned long rate;
27f805dc 121
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122 cpu_clk = clk_get(NULL, "armclk");
123 if (IS_ERR(cpu_clk))
124 return PTR_ERR(cpu_clk);
125
126 moutcore = clk_get(NULL, "moutcore");
127 if (IS_ERR(moutcore))
a125a17f 128 goto err_moutcore;
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129
130 mout_mpll = clk_get(NULL, "mout_mpll");
131 if (IS_ERR(mout_mpll))
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132 goto err_mout_mpll;
133
134 rate = clk_get_rate(mout_mpll) / 1000;
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135
136 mout_apll = clk_get(NULL, "mout_apll");
137 if (IS_ERR(mout_apll))
a125a17f 138 goto err_mout_apll;
0073f538 139
a125a17f 140 info->mpll_freq_khz = rate;
9d0554ff 141 /* 800Mhz */
a125a17f 142 info->pll_safe_idx = L2;
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143 info->cpu_clk = cpu_clk;
144 info->volt_table = exynos4210_volt_table;
145 info->freq_table = exynos4210_freq_table;
146 info->set_freq = exynos4210_set_frequency;
f40f91fe 147
a125a17f 148 return 0;
f40f91fe 149
a125a17f 150err_mout_apll:
184cddd1 151 clk_put(mout_mpll);
a125a17f 152err_mout_mpll:
184cddd1 153 clk_put(moutcore);
a125a17f 154err_moutcore:
184cddd1 155 clk_put(cpu_clk);
f40f91fe 156
a125a17f 157 pr_debug("%s: failed initialization\n", __func__);
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158 return -EINVAL;
159}