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a125a17f JL |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - CPU frequency scaling support for EXYNOS series | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a125a17f JL |
12 | #include <linux/kernel.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | #include <linux/cpufreq.h> | |
d568b6f7 | 19 | #include <linux/platform_device.h> |
a125a17f | 20 | |
6c523c61 | 21 | #include <plat/cpu.h> |
a125a17f | 22 | |
c4aaa295 KK |
23 | #include "exynos-cpufreq.h" |
24 | ||
a125a17f | 25 | static struct exynos_dvfs_info *exynos_info; |
a125a17f | 26 | static struct regulator *arm_regulator; |
a125a17f | 27 | static unsigned int locking_frequency; |
a125a17f | 28 | |
0e0e425f JC |
29 | static int exynos_cpufreq_get_index(unsigned int freq) |
30 | { | |
31 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
041526f9 | 32 | struct cpufreq_frequency_table *pos; |
0e0e425f | 33 | |
041526f9 SK |
34 | cpufreq_for_each_entry(pos, freq_table) |
35 | if (pos->frequency == freq) | |
0e0e425f JC |
36 | break; |
37 | ||
041526f9 | 38 | if (pos->frequency == CPUFREQ_TABLE_END) |
0e0e425f JC |
39 | return -EINVAL; |
40 | ||
041526f9 | 41 | return pos - freq_table; |
0e0e425f JC |
42 | } |
43 | ||
44 | static int exynos_cpufreq_scale(unsigned int target_freq) | |
a125a17f | 45 | { |
a125a17f JL |
46 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; |
47 | unsigned int *volt_table = exynos_info->volt_table; | |
0e0e425f JC |
48 | struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
49 | unsigned int arm_volt, safe_arm_volt = 0; | |
a125a17f | 50 | unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; |
d4019f0a | 51 | unsigned int old_freq; |
d271d077 | 52 | int index, old_index; |
0e0e425f | 53 | int ret = 0; |
a125a17f | 54 | |
d4019f0a | 55 | old_freq = policy->cur; |
a125a17f | 56 | |
53df1ad5 JL |
57 | /* |
58 | * The policy max have been changed so that we cannot get proper | |
59 | * old_index with cpufreq_frequency_table_target(). Thus, ignore | |
0585123e | 60 | * policy and get the index from the raw frequency table. |
53df1ad5 | 61 | */ |
d4019f0a | 62 | old_index = exynos_cpufreq_get_index(old_freq); |
0e0e425f JC |
63 | if (old_index < 0) { |
64 | ret = old_index; | |
a125a17f JL |
65 | goto out; |
66 | } | |
67 | ||
0e0e425f JC |
68 | index = exynos_cpufreq_get_index(target_freq); |
69 | if (index < 0) { | |
70 | ret = index; | |
a125a17f JL |
71 | goto out; |
72 | } | |
73 | ||
a125a17f JL |
74 | /* |
75 | * ARM clock source will be changed APLL to MPLL temporary | |
76 | * To support this level, need to control regulator for | |
77 | * required voltage level | |
78 | */ | |
79 | if (exynos_info->need_apll_change != NULL) { | |
80 | if (exynos_info->need_apll_change(old_index, index) && | |
81 | (freq_table[index].frequency < mpll_freq_khz) && | |
82 | (freq_table[old_index].frequency < mpll_freq_khz)) | |
83 | safe_arm_volt = volt_table[exynos_info->pll_safe_idx]; | |
84 | } | |
85 | arm_volt = volt_table[index]; | |
86 | ||
a125a17f | 87 | /* When the new frequency is higher than current frequency */ |
d4019f0a | 88 | if ((target_freq > old_freq) && !safe_arm_volt) { |
a125a17f | 89 | /* Firstly, voltage up to increase frequency */ |
0e0e425f JC |
90 | ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt); |
91 | if (ret) { | |
92 | pr_err("%s: failed to set cpu voltage to %d\n", | |
93 | __func__, arm_volt); | |
d4019f0a | 94 | return ret; |
0e0e425f | 95 | } |
a125a17f JL |
96 | } |
97 | ||
0e0e425f JC |
98 | if (safe_arm_volt) { |
99 | ret = regulator_set_voltage(arm_regulator, safe_arm_volt, | |
a125a17f | 100 | safe_arm_volt); |
0e0e425f JC |
101 | if (ret) { |
102 | pr_err("%s: failed to set cpu voltage to %d\n", | |
103 | __func__, safe_arm_volt); | |
d4019f0a | 104 | return ret; |
0e0e425f JC |
105 | } |
106 | } | |
857d90f7 JC |
107 | |
108 | exynos_info->set_freq(old_index, index); | |
a125a17f | 109 | |
a125a17f | 110 | /* When the new frequency is lower than current frequency */ |
d4019f0a VK |
111 | if ((target_freq < old_freq) || |
112 | ((target_freq > old_freq) && safe_arm_volt)) { | |
a125a17f | 113 | /* down the voltage after frequency change */ |
006454ae | 114 | ret = regulator_set_voltage(arm_regulator, arm_volt, |
a125a17f | 115 | arm_volt); |
0e0e425f JC |
116 | if (ret) { |
117 | pr_err("%s: failed to set cpu voltage to %d\n", | |
118 | __func__, arm_volt); | |
119 | goto out; | |
120 | } | |
a125a17f JL |
121 | } |
122 | ||
0e0e425f | 123 | out: |
0e0e425f JC |
124 | cpufreq_cpu_put(policy); |
125 | ||
126 | return ret; | |
127 | } | |
128 | ||
9c0ebcf7 | 129 | static int exynos_target(struct cpufreq_policy *policy, unsigned int index) |
0e0e425f | 130 | { |
d248bb89 | 131 | return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency); |
a125a17f JL |
132 | } |
133 | ||
a125a17f JL |
134 | static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) |
135 | { | |
652ed95d | 136 | policy->clk = exynos_info->cpu_clk; |
d248bb89 | 137 | policy->suspend_freq = locking_frequency; |
b249abae | 138 | return cpufreq_generic_init(policy, exynos_info->freq_table, 100000); |
a125a17f JL |
139 | } |
140 | ||
141 | static struct cpufreq_driver exynos_driver = { | |
ae6b4271 | 142 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
eea6181e | 143 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 144 | .target_index = exynos_target, |
652ed95d | 145 | .get = cpufreq_generic_get, |
a125a17f JL |
146 | .init = exynos_cpufreq_cpu_init, |
147 | .name = "exynos_cpufreq", | |
eea6181e | 148 | .attr = cpufreq_generic_attr, |
c683c2c9 LM |
149 | #ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW |
150 | .boost_supported = true, | |
151 | #endif | |
a125a17f | 152 | #ifdef CONFIG_PM |
d248bb89 | 153 | .suspend = cpufreq_generic_suspend, |
a125a17f JL |
154 | #endif |
155 | }; | |
156 | ||
d568b6f7 | 157 | static int exynos_cpufreq_probe(struct platform_device *pdev) |
a125a17f JL |
158 | { |
159 | int ret = -EINVAL; | |
160 | ||
d5b73cd8 | 161 | exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL); |
a125a17f JL |
162 | if (!exynos_info) |
163 | return -ENOMEM; | |
164 | ||
165 | if (soc_is_exynos4210()) | |
166 | ret = exynos4210_cpufreq_init(exynos_info); | |
a35c5051 JL |
167 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
168 | ret = exynos4x12_cpufreq_init(exynos_info); | |
562a6cbe JL |
169 | else if (soc_is_exynos5250()) |
170 | ret = exynos5250_cpufreq_init(exynos_info); | |
a125a17f | 171 | else |
c1585207 | 172 | return 0; |
a125a17f JL |
173 | |
174 | if (ret) | |
175 | goto err_vdd_arm; | |
176 | ||
177 | if (exynos_info->set_freq == NULL) { | |
178 | pr_err("%s: No set_freq function (ERR)\n", __func__); | |
179 | goto err_vdd_arm; | |
180 | } | |
181 | ||
182 | arm_regulator = regulator_get(NULL, "vdd_arm"); | |
183 | if (IS_ERR(arm_regulator)) { | |
184 | pr_err("%s: failed to get resource vdd_arm\n", __func__); | |
185 | goto err_vdd_arm; | |
186 | } | |
187 | ||
d248bb89 | 188 | /* Done here as we want to capture boot frequency */ |
652ed95d | 189 | locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000; |
6e45eb12 | 190 | |
d248bb89 VK |
191 | if (!cpufreq_register_driver(&exynos_driver)) |
192 | return 0; | |
a125a17f | 193 | |
d248bb89 | 194 | pr_err("%s: failed to register cpufreq driver\n", __func__); |
184cddd1 | 195 | regulator_put(arm_regulator); |
a125a17f JL |
196 | err_vdd_arm: |
197 | kfree(exynos_info); | |
a125a17f JL |
198 | return -EINVAL; |
199 | } | |
d568b6f7 LM |
200 | |
201 | static struct platform_driver exynos_cpufreq_platdrv = { | |
202 | .driver = { | |
203 | .name = "exynos-cpufreq", | |
204 | .owner = THIS_MODULE, | |
205 | }, | |
206 | .probe = exynos_cpufreq_probe, | |
207 | }; | |
208 | module_platform_driver(exynos_cpufreq_platdrv); |