[linux-2.6-block.git] / drivers / cpufreq / exynos-cpufreq.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - CPU frequency scaling support for EXYNOS series
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/cpufreq.h>
#include <linux/suspend.h>

#include <mach/cpufreq.h>

#include <plat/cpu.h>

static struct exynos_dvfs_info *exynos_info;

static struct regulator *arm_regulator;
static struct cpufreq_freqs freqs;

static unsigned int locking_frequency;
static bool frequency_locked;
static DEFINE_MUTEX(cpufreq_lock);

static int exynos_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy,
					      exynos_info->freq_table);
}

static unsigned int exynos_getspeed(unsigned int cpu)
{
	return clk_get_rate(exynos_info->cpu_clk) / 1000;
}

static int exynos_cpufreq_get_index(unsigned int freq)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	int index;

	for (index = 0;
		freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
		if (freq_table[index].frequency == freq)
			break;

	if (freq_table[index].frequency == CPUFREQ_TABLE_END)
		return -EINVAL;

	return index;
}

static int exynos_cpufreq_scale(unsigned int target_freq)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	unsigned int *volt_table = exynos_info->volt_table;
	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
	unsigned int arm_volt, safe_arm_volt = 0;
	unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
	unsigned int index, old_index;
	int ret = 0;

	freqs.old = policy->cur;
	freqs.cpu = policy->cpu;

	if (target_freq == freqs.old)
		goto out;

	/*
	 * The policy max have been changed so that we cannot get proper
	 * old_index with cpufreq_frequency_table_target(). Thus, ignore
	 * policy and get the index from the raw freqeuncy table.
	 */
	old_index = exynos_cpufreq_get_index(freqs.old);
	if (old_index < 0) {
		ret = old_index;
		goto out;
	}

	index = exynos_cpufreq_get_index(target_freq);
	if (index < 0) {
		ret = index;
		goto out;
	}

	/*
	 * ARM clock source will be changed APLL to MPLL temporary
	 * To support this level, need to control regulator for
	 * required voltage level
	 */
	if (exynos_info->need_apll_change != NULL) {
		if (exynos_info->need_apll_change(old_index, index) &&
		   (freq_table[index].frequency < mpll_freq_khz) &&
		   (freq_table[old_index].frequency < mpll_freq_khz))
			safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
	}
	arm_volt = volt_table[index];

	for_each_cpu(freqs.cpu, policy->cpus)
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* When the new frequency is higher than current frequency */
	if ((freqs.new > freqs.old) && !safe_arm_volt) {
		/* Firstly, voltage up to increase frequency */
		ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, arm_volt);
			goto out;
		}
	}

	if (safe_arm_volt) {
		ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
				      safe_arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, safe_arm_volt);
			goto out;
		}
	}

	exynos_info->set_freq(old_index, index);

	for_each_cpu(freqs.cpu, policy->cpus)
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	/* When the new frequency is lower than current frequency */
	if ((freqs.new < freqs.old) ||
	   ((freqs.new > freqs.old) && safe_arm_volt)) {
		/* down the voltage after frequency change */
		regulator_set_voltage(arm_regulator, arm_volt,
				arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, arm_volt);
			goto out;
		}
	}

out:

	cpufreq_cpu_put(policy);

	return ret;
}

static int exynos_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	unsigned int index;
	int ret;

	mutex_lock(&cpufreq_lock);

	if (frequency_locked)
		goto out;

	if (cpufreq_frequency_table_target(policy, freq_table,
					   target_freq, relation, &index)) {
		ret = -EINVAL;
		goto out;
	}

	freqs.new = freq_table[index].frequency;

	ret = exynos_cpufreq_scale(freqs.new);

out:
	mutex_unlock(&cpufreq_lock);

	return ret;
}

#ifdef CONFIG_PM
static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

/**
 * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
 *			context
 * @notifier
 * @pm_event
 * @v
 *
 * While frequency_locked == true, target() ignores every frequency but
 * locking_frequency. The locking_frequency value is the initial frequency,
 * which is set by the bootloader. In order to eliminate possible
 * inconsistency in clock values, we save and restore frequencies during
 * suspend and resume and block CPUFREQ activities. Note that the standard
 * suspend/resume cannot be used as they are too deep (syscore_ops) for
 * regulator actions.
 */
static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
				       unsigned long pm_event, void *v)
{
	int ret;

	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		mutex_lock(&cpufreq_lock);
		frequency_locked = true;
		mutex_unlock(&cpufreq_lock);

		ret = exynos_cpufreq_scale(locking_frequency);
		if (ret < 0)
			return NOTIFY_BAD;

		break;

	case PM_POST_SUSPEND:
		mutex_lock(&cpufreq_lock);
		frequency_locked = false;
		mutex_unlock(&cpufreq_lock);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos_cpufreq_nb = {
	.notifier_call = exynos_cpufreq_pm_notifier,
};

static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);

	cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);

	locking_frequency = exynos_getspeed(0);

	/* set the transition latency value */
	policy->cpuinfo.transition_latency = 100000;

	/*
	 * EXYNOS4 multi-core processors has 2 cores
	 * that the frequency cannot be set independently.
	 * Each cpu is bound to the same speed.
	 * So the affected cpu is all of the cpus.
	 */
	if (num_online_cpus() == 1) {
		cpumask_copy(policy->related_cpus, cpu_possible_mask);
		cpumask_copy(policy->cpus, cpu_online_mask);
	} else {
		policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
		cpumask_setall(policy->cpus);
	}

	return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
}

static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static struct freq_attr *exynos_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver exynos_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= exynos_verify_speed,
	.target		= exynos_target,
	.get		= exynos_getspeed,
	.init		= exynos_cpufreq_cpu_init,
	.exit		= exynos_cpufreq_cpu_exit,
	.name		= "exynos_cpufreq",
	.attr		= exynos_cpufreq_attr,
#ifdef CONFIG_PM
	.suspend	= exynos_cpufreq_suspend,
	.resume		= exynos_cpufreq_resume,
#endif
};

static int __init exynos_cpufreq_init(void)
{
	int ret = -EINVAL;

	exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
	if (!exynos_info)
		return -ENOMEM;

	if (soc_is_exynos4210())
		ret = exynos4210_cpufreq_init(exynos_info);
	else if (soc_is_exynos4212() || soc_is_exynos4412())
		ret = exynos4x12_cpufreq_init(exynos_info);
	else if (soc_is_exynos5250())
		ret = exynos5250_cpufreq_init(exynos_info);
	else
		pr_err("%s: CPU type not found\n", __func__);

	if (ret)
		goto err_vdd_arm;

	if (exynos_info->set_freq == NULL) {
		pr_err("%s: No set_freq function (ERR)\n", __func__);
		goto err_vdd_arm;
	}

	arm_regulator = regulator_get(NULL, "vdd_arm");
	if (IS_ERR(arm_regulator)) {
		pr_err("%s: failed to get resource vdd_arm\n", __func__);
		goto err_vdd_arm;
	}

	register_pm_notifier(&exynos_cpufreq_nb);

	if (cpufreq_register_driver(&exynos_driver)) {
		pr_err("%s: failed to register cpufreq driver\n", __func__);
		goto err_cpufreq;
	}

	return 0;
err_cpufreq:
	unregister_pm_notifier(&exynos_cpufreq_nb);

	regulator_put(arm_regulator);
err_vdd_arm:
	kfree(exynos_info);
	pr_debug("%s: failed initialization\n", __func__);
	return -EINVAL;
}
late_initcall(exynos_cpufreq_init);
Commit	Line	Data
a125a17f JL	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* EXYNOS - CPU frequency scaling support for EXYNOS series
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
a125a17f JL	12	#include <linux/kernel.h>
	13	#include <linux/err.h>
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
	16	#include <linux/slab.h>
	17	#include <linux/regulator/consumer.h>
	18	#include <linux/cpufreq.h>
	19	#include <linux/suspend.h>
a125a17f	20
a125a17f JL	21	#include <mach/cpufreq.h>
a125a17f JL	22
6c523c61	23	#include <plat/cpu.h>
a125a17f JL	24
	25	static struct exynos_dvfs_info *exynos_info;
	26
	27	static struct regulator *arm_regulator;
	28	static struct cpufreq_freqs freqs;
	29
	30	static unsigned int locking_frequency;
	31	static bool frequency_locked;
	32	static DEFINE_MUTEX(cpufreq_lock);
	33
5542721a	34	static int exynos_verify_speed(struct cpufreq_policy *policy)
a125a17f JL	35	{
	36	return cpufreq_frequency_table_verify(policy,
	37	exynos_info->freq_table);
	38	}
	39
5542721a	40	static unsigned int exynos_getspeed(unsigned int cpu)
a125a17f JL	41	{
	42	return clk_get_rate(exynos_info->cpu_clk) / 1000;
	43	}
	44
0e0e425f JC	45	static int exynos_cpufreq_get_index(unsigned int freq)
	46	{
	47	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	48	int index;
	49
	50	for (index = 0;
	51	freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
	52	if (freq_table[index].frequency == freq)
	53	break;
	54
	55	if (freq_table[index].frequency == CPUFREQ_TABLE_END)
	56	return -EINVAL;
	57
	58	return index;
	59	}
	60
	61	static int exynos_cpufreq_scale(unsigned int target_freq)
a125a17f	62	{
a125a17f JL	63	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
a125a17f JL	64	unsigned int *volt_table = exynos_info->volt_table;
0e0e425f JC	65	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
0e0e425f JC	66	unsigned int arm_volt, safe_arm_volt = 0;
a125a17f	67	unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
0e0e425f JC	68	unsigned int index, old_index;
0e0e425f JC	69	int ret = 0;
a125a17f JL	70
a125a17f JL	71	freqs.old = policy->cur;
0e0e425f	72	freqs.cpu = policy->cpu;
a125a17f	73
0e0e425f	74	if (target_freq == freqs.old)
a125a17f	75	goto out;
a125a17f	76
53df1ad5 JL	77	/*
	78	* The policy max have been changed so that we cannot get proper
	79	* old_index with cpufreq_frequency_table_target(). Thus, ignore
	80	* policy and get the index from the raw freqeuncy table.
	81	*/
0e0e425f JC	82	old_index = exynos_cpufreq_get_index(freqs.old);
	83	if (old_index < 0) {
	84	ret = old_index;
a125a17f JL	85	goto out;
	86	}
	87
0e0e425f JC	88	index = exynos_cpufreq_get_index(target_freq);
	89	if (index < 0) {
	90	ret = index;
a125a17f JL	91	goto out;
	92	}
	93
a125a17f JL	94	/*
	95	* ARM clock source will be changed APLL to MPLL temporary
	96	* To support this level, need to control regulator for
	97	* required voltage level
	98	*/
	99	if (exynos_info->need_apll_change != NULL) {
	100	if (exynos_info->need_apll_change(old_index, index) &&
	101	(freq_table[index].frequency < mpll_freq_khz) &&
	102	(freq_table[old_index].frequency < mpll_freq_khz))
	103	safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
	104	}
	105	arm_volt = volt_table[index];
	106
fd06a208 TF	107	for_each_cpu(freqs.cpu, policy->cpus)
fd06a208 TF	108	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
a125a17f JL	109
	110	/* When the new frequency is higher than current frequency */
	111	if ((freqs.new > freqs.old) && !safe_arm_volt) {
	112	/* Firstly, voltage up to increase frequency */
0e0e425f JC	113	ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	114	if (ret) {
	115	pr_err("%s: failed to set cpu voltage to %d\n",
	116	__func__, arm_volt);
	117	goto out;
	118	}
a125a17f JL	119	}
a125a17f JL	120
0e0e425f JC	121	if (safe_arm_volt) {
0e0e425f JC	122	ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
a125a17f	123	safe_arm_volt);
0e0e425f JC	124	if (ret) {
	125	pr_err("%s: failed to set cpu voltage to %d\n",
	126	__func__, safe_arm_volt);
	127	goto out;
	128	}
	129	}
857d90f7 JC	130
857d90f7 JC	131	exynos_info->set_freq(old_index, index);
a125a17f	132
fd06a208 TF	133	for_each_cpu(freqs.cpu, policy->cpus)
fd06a208 TF	134	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
a125a17f JL	135
	136	/* When the new frequency is lower than current frequency */
	137	if ((freqs.new < freqs.old) \|\|
	138	((freqs.new > freqs.old) && safe_arm_volt)) {
	139	/* down the voltage after frequency change */
	140	regulator_set_voltage(arm_regulator, arm_volt,
	141	arm_volt);
0e0e425f JC	142	if (ret) {
	143	pr_err("%s: failed to set cpu voltage to %d\n",
	144	__func__, arm_volt);
	145	goto out;
	146	}
	147	}
	148
	149	out:
	150
	151	cpufreq_cpu_put(policy);
	152
	153	return ret;
	154	}
	155
	156	static int exynos_target(struct cpufreq_policy *policy,
	157	unsigned int target_freq,
	158	unsigned int relation)
	159	{
	160	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	161	unsigned int index;
	162	int ret;
	163
	164	mutex_lock(&cpufreq_lock);
	165
	166	if (frequency_locked)
	167	goto out;
	168
	169	if (cpufreq_frequency_table_target(policy, freq_table,
	170	target_freq, relation, &index)) {
	171	ret = -EINVAL;
	172	goto out;
a125a17f JL	173	}
a125a17f JL	174
0e0e425f JC	175	freqs.new = freq_table[index].frequency;
	176
	177	ret = exynos_cpufreq_scale(freqs.new);
	178
a125a17f JL	179	out:
	180	mutex_unlock(&cpufreq_lock);
	181
	182	return ret;
	183	}
	184
	185	#ifdef CONFIG_PM
	186	static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
	187	{
	188	return 0;
	189	}
	190
	191	static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
	192	{
	193	return 0;
	194	}
	195	#endif
	196
	197	/**
	198	* exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
	199	* context
	200	* @notifier
	201	* @pm_event
	202	* @v
	203	*
	204	* While frequency_locked == true, target() ignores every frequency but
	205	* locking_frequency. The locking_frequency value is the initial frequency,
	206	* which is set by the bootloader. In order to eliminate possible
	207	* inconsistency in clock values, we save and restore frequencies during
	208	* suspend and resume and block CPUFREQ activities. Note that the standard
	209	* suspend/resume cannot be used as they are too deep (syscore_ops) for
	210	* regulator actions.
	211	*/
	212	static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
	213	unsigned long pm_event, void *v)
	214	{
0e0e425f	215	int ret;
a125a17f	216
a125a17f JL	217	switch (pm_event) {
a125a17f JL	218	case PM_SUSPEND_PREPARE:
0e0e425f	219	mutex_lock(&cpufreq_lock);
a125a17f	220	frequency_locked = true;
0e0e425f	221	mutex_unlock(&cpufreq_lock);
a125a17f	222
0e0e425f JC	223	ret = exynos_cpufreq_scale(locking_frequency);
	224	if (ret < 0)
	225	return NOTIFY_BAD;
a125a17f	226
a125a17f JL	227	break;
	228
	229	case PM_POST_SUSPEND:
0e0e425f	230	mutex_lock(&cpufreq_lock);
a125a17f	231	frequency_locked = false;
0e0e425f	232	mutex_unlock(&cpufreq_lock);
a125a17f JL	233	break;
a125a17f JL	234	}
a125a17f JL	235
	236	return NOTIFY_OK;
	237	}
	238
	239	static struct notifier_block exynos_cpufreq_nb = {
	240	.notifier_call = exynos_cpufreq_pm_notifier,
	241	};
	242
	243	static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
	244	{
	245	policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
	246
	247	cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
	248
60d2725d TB	249	locking_frequency = exynos_getspeed(0);
60d2725d TB	250
a125a17f JL	251	/* set the transition latency value */
	252	policy->cpuinfo.transition_latency = 100000;
	253
	254	/*
	255	* EXYNOS4 multi-core processors has 2 cores
	256	* that the frequency cannot be set independently.
	257	* Each cpu is bound to the same speed.
	258	* So the affected cpu is all of the cpus.
	259	*/
	260	if (num_online_cpus() == 1) {
	261	cpumask_copy(policy->related_cpus, cpu_possible_mask);
	262	cpumask_copy(policy->cpus, cpu_online_mask);
	263	} else {
fd06a208	264	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
a125a17f JL	265	cpumask_setall(policy->cpus);
	266	}
	267
	268	return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
	269	}
	270
1298271b IS	271	static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
	272	{
	273	cpufreq_frequency_table_put_attr(policy->cpu);
	274	return 0;
	275	}
	276
	277	static struct freq_attr *exynos_cpufreq_attr[] = {
	278	&cpufreq_freq_attr_scaling_available_freqs,
	279	NULL,
	280	};
	281
a125a17f JL	282	static struct cpufreq_driver exynos_driver = {
	283	.flags = CPUFREQ_STICKY,
	284	.verify = exynos_verify_speed,
	285	.target = exynos_target,
	286	.get = exynos_getspeed,
	287	.init = exynos_cpufreq_cpu_init,
1298271b	288	.exit = exynos_cpufreq_cpu_exit,
a125a17f	289	.name = "exynos_cpufreq",
1298271b	290	.attr = exynos_cpufreq_attr,
a125a17f JL	291	#ifdef CONFIG_PM
	292	.suspend = exynos_cpufreq_suspend,
	293	.resume = exynos_cpufreq_resume,
	294	#endif
	295	};
	296
	297	static int __init exynos_cpufreq_init(void)
	298	{
	299	int ret = -EINVAL;
	300
	301	exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
	302	if (!exynos_info)
	303	return -ENOMEM;
	304
	305	if (soc_is_exynos4210())
	306	ret = exynos4210_cpufreq_init(exynos_info);
a35c5051 JL	307	else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
a35c5051 JL	308	ret = exynos4x12_cpufreq_init(exynos_info);
562a6cbe JL	309	else if (soc_is_exynos5250())
562a6cbe JL	310	ret = exynos5250_cpufreq_init(exynos_info);
a125a17f JL	311	else
	312	pr_err("%s: CPU type not found\n", __func__);
	313
	314	if (ret)
	315	goto err_vdd_arm;
	316
	317	if (exynos_info->set_freq == NULL) {
	318	pr_err("%s: No set_freq function (ERR)\n", __func__);
	319	goto err_vdd_arm;
	320	}
	321
	322	arm_regulator = regulator_get(NULL, "vdd_arm");
	323	if (IS_ERR(arm_regulator)) {
	324	pr_err("%s: failed to get resource vdd_arm\n", __func__);
	325	goto err_vdd_arm;
	326	}
	327
	328	register_pm_notifier(&exynos_cpufreq_nb);
	329
	330	if (cpufreq_register_driver(&exynos_driver)) {
	331	pr_err("%s: failed to register cpufreq driver\n", __func__);
	332	goto err_cpufreq;
	333	}
	334
	335	return 0;
	336	err_cpufreq:
	337	unregister_pm_notifier(&exynos_cpufreq_nb);
	338
184cddd1	339	regulator_put(arm_regulator);
a125a17f JL	340	err_vdd_arm:
	341	kfree(exynos_info);
	342	pr_debug("%s: failed initialization\n", __func__);
	343	return -EINVAL;
	344	}
	345	late_initcall(exynos_cpufreq_init);