Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/mfleming...
[linux-2.6-block.git] / drivers / cpufreq / exynos-cpufreq.c
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1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - CPU frequency scaling support for EXYNOS series
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
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12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/regulator/consumer.h>
18#include <linux/cpufreq.h>
d568b6f7 19#include <linux/platform_device.h>
be1f7c8d 20#include <linux/of.h>
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21#include <linux/cpu_cooling.h>
22#include <linux/cpu.h>
a125a17f 23
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24#include "exynos-cpufreq.h"
25
a125a17f 26static struct exynos_dvfs_info *exynos_info;
e725d26c 27static struct thermal_cooling_device *cdev;
a125a17f 28static struct regulator *arm_regulator;
a125a17f 29static unsigned int locking_frequency;
a125a17f 30
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31static int exynos_cpufreq_get_index(unsigned int freq)
32{
33 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
041526f9 34 struct cpufreq_frequency_table *pos;
0e0e425f 35
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36 cpufreq_for_each_entry(pos, freq_table)
37 if (pos->frequency == freq)
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38 break;
39
041526f9 40 if (pos->frequency == CPUFREQ_TABLE_END)
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41 return -EINVAL;
42
041526f9 43 return pos - freq_table;
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44}
45
46static int exynos_cpufreq_scale(unsigned int target_freq)
a125a17f 47{
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48 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
49 unsigned int *volt_table = exynos_info->volt_table;
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50 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
51 unsigned int arm_volt, safe_arm_volt = 0;
a125a17f 52 unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
e5eaa445 53 struct device *dev = exynos_info->dev;
d4019f0a 54 unsigned int old_freq;
d271d077 55 int index, old_index;
0e0e425f 56 int ret = 0;
a125a17f 57
d4019f0a 58 old_freq = policy->cur;
a125a17f 59
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60 /*
61 * The policy max have been changed so that we cannot get proper
62 * old_index with cpufreq_frequency_table_target(). Thus, ignore
0585123e 63 * policy and get the index from the raw frequency table.
53df1ad5 64 */
d4019f0a 65 old_index = exynos_cpufreq_get_index(old_freq);
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66 if (old_index < 0) {
67 ret = old_index;
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68 goto out;
69 }
70
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71 index = exynos_cpufreq_get_index(target_freq);
72 if (index < 0) {
73 ret = index;
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74 goto out;
75 }
76
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77 /*
78 * ARM clock source will be changed APLL to MPLL temporary
79 * To support this level, need to control regulator for
80 * required voltage level
81 */
82 if (exynos_info->need_apll_change != NULL) {
83 if (exynos_info->need_apll_change(old_index, index) &&
84 (freq_table[index].frequency < mpll_freq_khz) &&
85 (freq_table[old_index].frequency < mpll_freq_khz))
86 safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
87 }
88 arm_volt = volt_table[index];
89
a125a17f 90 /* When the new frequency is higher than current frequency */
d4019f0a 91 if ((target_freq > old_freq) && !safe_arm_volt) {
a125a17f 92 /* Firstly, voltage up to increase frequency */
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93 ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
94 if (ret) {
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CC
95 dev_err(dev, "failed to set cpu voltage to %d\n",
96 arm_volt);
d4019f0a 97 return ret;
0e0e425f 98 }
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99 }
100
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101 if (safe_arm_volt) {
102 ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
a125a17f 103 safe_arm_volt);
0e0e425f 104 if (ret) {
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105 dev_err(dev, "failed to set cpu voltage to %d\n",
106 safe_arm_volt);
d4019f0a 107 return ret;
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108 }
109 }
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110
111 exynos_info->set_freq(old_index, index);
a125a17f 112
a125a17f 113 /* When the new frequency is lower than current frequency */
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114 if ((target_freq < old_freq) ||
115 ((target_freq > old_freq) && safe_arm_volt)) {
a125a17f 116 /* down the voltage after frequency change */
006454ae 117 ret = regulator_set_voltage(arm_regulator, arm_volt,
a125a17f 118 arm_volt);
0e0e425f 119 if (ret) {
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120 dev_err(dev, "failed to set cpu voltage to %d\n",
121 arm_volt);
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122 goto out;
123 }
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124 }
125
0e0e425f 126out:
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127 cpufreq_cpu_put(policy);
128
129 return ret;
130}
131
9c0ebcf7 132static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
0e0e425f 133{
d248bb89 134 return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency);
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135}
136
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137static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
138{
652ed95d 139 policy->clk = exynos_info->cpu_clk;
d248bb89 140 policy->suspend_freq = locking_frequency;
b249abae 141 return cpufreq_generic_init(policy, exynos_info->freq_table, 100000);
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142}
143
144static struct cpufreq_driver exynos_driver = {
ae6b4271 145 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
eea6181e 146 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 147 .target_index = exynos_target,
652ed95d 148 .get = cpufreq_generic_get,
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149 .init = exynos_cpufreq_cpu_init,
150 .name = "exynos_cpufreq",
eea6181e 151 .attr = cpufreq_generic_attr,
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152#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW
153 .boost_supported = true,
154#endif
a125a17f 155#ifdef CONFIG_PM
d248bb89 156 .suspend = cpufreq_generic_suspend,
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157#endif
158};
159
d568b6f7 160static int exynos_cpufreq_probe(struct platform_device *pdev)
a125a17f 161{
0fc83929 162 struct device_node *cpu0;
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163 int ret = -EINVAL;
164
d5b73cd8 165 exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
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166 if (!exynos_info)
167 return -ENOMEM;
168
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169 exynos_info->dev = &pdev->dev;
170
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171 if (of_machine_is_compatible("samsung,exynos4210")) {
172 exynos_info->type = EXYNOS_SOC_4210;
a125a17f 173 ret = exynos4210_cpufreq_init(exynos_info);
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174 } else if (of_machine_is_compatible("samsung,exynos4212")) {
175 exynos_info->type = EXYNOS_SOC_4212;
a35c5051 176 ret = exynos4x12_cpufreq_init(exynos_info);
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177 } else if (of_machine_is_compatible("samsung,exynos4412")) {
178 exynos_info->type = EXYNOS_SOC_4412;
179 ret = exynos4x12_cpufreq_init(exynos_info);
180 } else if (of_machine_is_compatible("samsung,exynos5250")) {
181 exynos_info->type = EXYNOS_SOC_5250;
562a6cbe 182 ret = exynos5250_cpufreq_init(exynos_info);
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183 } else {
184 pr_err("%s: Unknown SoC type\n", __func__);
185 return -ENODEV;
186 }
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187
188 if (ret)
189 goto err_vdd_arm;
190
191 if (exynos_info->set_freq == NULL) {
e5eaa445 192 dev_err(&pdev->dev, "No set_freq function (ERR)\n");
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193 goto err_vdd_arm;
194 }
195
196 arm_regulator = regulator_get(NULL, "vdd_arm");
197 if (IS_ERR(arm_regulator)) {
e5eaa445 198 dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
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199 goto err_vdd_arm;
200 }
201
d248bb89 202 /* Done here as we want to capture boot frequency */
652ed95d 203 locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;
6e45eb12 204
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205 ret = cpufreq_register_driver(&exynos_driver);
206 if (ret)
207 goto err_cpufreq_reg;
208
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209 cpu0 = of_get_cpu_node(0, NULL);
210 if (!cpu0) {
211 pr_err("failed to find cpu0 node\n");
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212 return 0;
213 }
214
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215 if (of_find_property(cpu0, "#cooling-cells", NULL)) {
216 cdev = of_cpufreq_cooling_register(cpu0,
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217 cpu_present_mask);
218 if (IS_ERR(cdev))
219 pr_err("running cpufreq without cooling device: %ld\n",
220 PTR_ERR(cdev));
221 }
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222
223 return 0;
a125a17f 224
e725d26c 225err_cpufreq_reg:
e5eaa445 226 dev_err(&pdev->dev, "failed to register cpufreq driver\n");
184cddd1 227 regulator_put(arm_regulator);
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228err_vdd_arm:
229 kfree(exynos_info);
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230 return -EINVAL;
231}
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232
233static struct platform_driver exynos_cpufreq_platdrv = {
234 .driver = {
235 .name = "exynos-cpufreq",
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236 },
237 .probe = exynos_cpufreq_probe,
238};
239module_platform_driver(exynos_cpufreq_platdrv);