Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux-2.6-block.git] / drivers / cpufreq / elanfreq.c
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1da177e4 1/*
32ee8c3e 2 * elanfreq: cpufreq driver for the AMD ELAN family
1da177e4
LT
3 *
4 * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
5 *
32ee8c3e 6 * Parts of this code are (c) Sven Geggus <sven@geggus.net>
1da177e4 7 *
32ee8c3e 8 * All Rights Reserved.
1da177e4
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9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
32ee8c3e 13 * 2 of the License, or (at your option) any later version.
1da177e4
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14 *
15 * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22
1da177e4
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23#include <linux/delay.h>
24#include <linux/cpufreq.h>
25
fa8031ae 26#include <asm/cpu_device_id.h>
1da177e4 27#include <asm/msr.h>
18c6faa9
PC
28#include <linux/timex.h>
29#include <linux/io.h>
1da177e4 30
32ee8c3e 31#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
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32#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
33
34/* Module parameter */
35static int max_freq;
36
37struct s_elan_multiplier {
38 int clock; /* frequency in kHz */
39 int val40h; /* PMU Force Mode register */
40 int val80h; /* CPU Clock Speed Register */
41};
42
43/*
32ee8c3e 44 * It is important that the frequencies
1da177e4
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45 * are listed in ascending order here!
46 */
460f5ef2 47static struct s_elan_multiplier elan_multiplier[] = {
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48 {1000, 0x02, 0x18},
49 {2000, 0x02, 0x10},
50 {4000, 0x02, 0x08},
51 {8000, 0x00, 0x00},
52 {16000, 0x00, 0x02},
53 {33000, 0x00, 0x04},
54 {66000, 0x01, 0x04},
55 {99000, 0x01, 0x05}
56};
57
58static struct cpufreq_frequency_table elanfreq_table[] = {
7f4b0461
VK
59 {0, 0, 1000},
60 {0, 1, 2000},
61 {0, 2, 4000},
62 {0, 3, 8000},
63 {0, 4, 16000},
64 {0, 5, 33000},
65 {0, 6, 66000},
66 {0, 7, 99000},
67 {0, 0, CPUFREQ_TABLE_END},
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68};
69
70
71/**
72 * elanfreq_get_cpu_frequency: determine current cpu speed
73 *
74 * Finds out at which frequency the CPU of the Elan SOC runs
32ee8c3e 75 * at the moment. Frequencies from 1 to 33 MHz are generated
1da177e4 76 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
32ee8c3e 77 * and have the rest of the chip running with 33 MHz.
1da177e4
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78 */
79
80static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
81{
32ee8c3e
DJ
82 u8 clockspeed_reg; /* Clock Speed Register */
83
1da177e4 84 local_irq_disable();
18c6faa9 85 outb_p(0x80, REG_CSCIR);
32ee8c3e 86 clockspeed_reg = inb_p(REG_CSCDR);
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87 local_irq_enable();
88
32ee8c3e
DJ
89 if ((clockspeed_reg & 0xE0) == 0xE0)
90 return 0;
1da177e4 91
32ee8c3e
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92 /* Are we in CPU clock multiplied mode (66/99 MHz)? */
93 if ((clockspeed_reg & 0xE0) == 0xC0) {
94 if ((clockspeed_reg & 0x01) == 0)
1da177e4 95 return 66000;
32ee8c3e
DJ
96 else
97 return 99000;
98 }
1da177e4
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99
100 /* 33 MHz is not 32 MHz... */
18c6faa9 101 if ((clockspeed_reg & 0xE0) == 0xA0)
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102 return 33000;
103
18c6faa9 104 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;
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105}
106
107
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108static int elanfreq_target(struct cpufreq_policy *policy,
109 unsigned int state)
32ee8c3e 110{
32ee8c3e
DJ
111 /*
112 * Access to the Elan's internal registers is indexed via
113 * 0x22: Chip Setup & Control Register Index Register (CSCI)
114 * 0x23: Chip Setup & Control Register Data Register (CSCD)
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115 *
116 */
117
32ee8c3e
DJ
118 /*
119 * 0x40 is the Power Management Unit's Force Mode Register.
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120 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency)
121 */
122
123 local_irq_disable();
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124 outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */
125 outb_p(0x00, REG_CSCDR);
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126 local_irq_enable(); /* wait till internal pipelines and */
127 udelay(1000); /* buffers have cleaned up */
128
129 local_irq_disable();
130
131 /* now, set the CPU clock speed register (0x80) */
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132 outb_p(0x80, REG_CSCIR);
133 outb_p(elan_multiplier[state].val80h, REG_CSCDR);
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134
135 /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */
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136 outb_p(0x40, REG_CSCIR);
137 outb_p(elan_multiplier[state].val40h, REG_CSCDR);
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138 udelay(10000);
139 local_irq_enable();
140
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141 return 0;
142}
1da177e4
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143/*
144 * Module init and exit code
145 */
146
147static int elanfreq_cpu_init(struct cpufreq_policy *policy)
148{
92cb7612 149 struct cpuinfo_x86 *c = &cpu_data(0);
041526f9 150 struct cpufreq_frequency_table *pos;
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151
152 /* capability check */
153 if ((c->x86_vendor != X86_VENDOR_AMD) ||
18c6faa9 154 (c->x86 != 4) || (c->x86_model != 10))
1da177e4
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155 return -ENODEV;
156
157 /* max freq */
158 if (!max_freq)
159 max_freq = elanfreq_get_cpu_frequency(0);
160
161 /* table init */
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SK
162 cpufreq_for_each_entry(pos, elanfreq_table)
163 if (pos->frequency > max_freq)
164 pos->frequency = CPUFREQ_ENTRY_INVALID;
1da177e4
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165
166 /* cpuinfo and default policy values */
1da177e4 167 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1da177e4 168
55bb85b7 169 return cpufreq_table_validate_and_show(policy, elanfreq_table);
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170}
171
172
1da177e4
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173#ifndef MODULE
174/**
175 * elanfreq_setup - elanfreq command line parameter parsing
176 *
177 * elanfreq command line parameter. Use:
178 * elanfreq=66000
179 * to set the maximum CPU frequency to 66 MHz. Note that in
180 * case you do not give this boot parameter, the maximum
181 * frequency will fall back to _current_ CPU frequency which
182 * might be lower. If you build this as a module, use the
183 * max_freq module parameter instead.
184 */
185static int __init elanfreq_setup(char *str)
186{
187 max_freq = simple_strtoul(str, &str, 0);
188 printk(KERN_WARNING "You're using the deprecated elanfreq command line option. Use elanfreq.max_freq instead, please!\n");
189 return 1;
190}
191__setup("elanfreq=", elanfreq_setup);
192#endif
193
194
221dee28 195static struct cpufreq_driver elanfreq_driver = {
32ee8c3e 196 .get = elanfreq_get_cpu_frequency,
06494eb7 197 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 198 .target_index = elanfreq_target,
1da177e4 199 .init = elanfreq_cpu_init,
1da177e4 200 .name = "elanfreq",
06494eb7 201 .attr = cpufreq_generic_attr,
1da177e4
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202};
203
fa8031ae
AK
204static const struct x86_cpu_id elan_id[] = {
205 { X86_VENDOR_AMD, 4, 10, },
206 {}
207};
208MODULE_DEVICE_TABLE(x86cpu, elan_id);
1da177e4 209
32ee8c3e
DJ
210static int __init elanfreq_init(void)
211{
fa8031ae 212 if (!x86_match_cpu(elan_id))
18c6faa9 213 return -ENODEV;
1da177e4
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214 return cpufreq_register_driver(&elanfreq_driver);
215}
216
217
32ee8c3e 218static void __exit elanfreq_exit(void)
1da177e4
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219{
220 cpufreq_unregister_driver(&elanfreq_driver);
221}
222
223
18c6faa9 224module_param(max_freq, int, 0444);
1da177e4
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225
226MODULE_LICENSE("GPL");
04cd1a99
DJ
227MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, "
228 "Sven Geggus <sven@geggus.net>");
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229MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
230
231module_init(elanfreq_init);
232module_exit(elanfreq_exit);