Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
6ccf58ab | 2 | * (C) 2004-2006 Sebastian Witt <se.witt@gmx.net> |
1da177e4 LT |
3 | * |
4 | * Licensed under the terms of the GNU GPL License version 2. | |
5 | * Based upon reverse engineered information | |
6 | * | |
7 | * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/cpufreq.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | ||
18 | #define NFORCE2_XTAL 25 | |
19 | #define NFORCE2_BOOTFSB 0x48 | |
20 | #define NFORCE2_PLLENABLE 0xa8 | |
21 | #define NFORCE2_PLLREG 0xa4 | |
22 | #define NFORCE2_PLLADR 0xa0 | |
23 | #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) | |
24 | ||
25 | #define NFORCE2_MIN_FSB 50 | |
26 | #define NFORCE2_SAFE_DISTANCE 50 | |
27 | ||
28 | /* Delay in ms between FSB changes */ | |
219835f1 | 29 | /* #define NFORCE2_DELAY 10 */ |
1da177e4 | 30 | |
219835f1 PC |
31 | /* |
32 | * nforce2_chipset: | |
1da177e4 LT |
33 | * FSB is changed using the chipset |
34 | */ | |
b5c91666 | 35 | static struct pci_dev *nforce2_dev; |
1da177e4 LT |
36 | |
37 | /* fid: | |
38 | * multiplier * 10 | |
39 | */ | |
219835f1 | 40 | static int fid; |
1da177e4 LT |
41 | |
42 | /* min_fsb, max_fsb: | |
32ee8c3e | 43 | * minimum and maximum FSB (= FSB at boot time) |
1da177e4 | 44 | */ |
219835f1 PC |
45 | static int min_fsb; |
46 | static int max_fsb; | |
1da177e4 LT |
47 | |
48 | MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>"); | |
49 | MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver"); | |
50 | MODULE_LICENSE("GPL"); | |
51 | ||
52 | module_param(fid, int, 0444); | |
53 | module_param(min_fsb, int, 0444); | |
54 | ||
55 | MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)"); | |
56 | MODULE_PARM_DESC(min_fsb, | |
219835f1 | 57 | "Minimum FSB to use, if not defined: current FSB - 50"); |
1da177e4 | 58 | |
20174b65 | 59 | #define PFX "cpufreq-nforce2: " |
1da177e4 | 60 | |
32ee8c3e | 61 | /** |
1da177e4 LT |
62 | * nforce2_calc_fsb - calculate FSB |
63 | * @pll: PLL value | |
32ee8c3e | 64 | * |
1da177e4 LT |
65 | * Calculates FSB from PLL value |
66 | */ | |
67 | static int nforce2_calc_fsb(int pll) | |
68 | { | |
69 | unsigned char mul, div; | |
70 | ||
71 | mul = (pll >> 8) & 0xff; | |
72 | div = pll & 0xff; | |
73 | ||
74 | if (div > 0) | |
75 | return NFORCE2_XTAL * mul / div; | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
32ee8c3e | 80 | /** |
1da177e4 LT |
81 | * nforce2_calc_pll - calculate PLL value |
82 | * @fsb: FSB | |
32ee8c3e | 83 | * |
1da177e4 LT |
84 | * Calculate PLL value for given FSB |
85 | */ | |
86 | static int nforce2_calc_pll(unsigned int fsb) | |
87 | { | |
88 | unsigned char xmul, xdiv; | |
89 | unsigned char mul = 0, div = 0; | |
90 | int tried = 0; | |
91 | ||
92 | /* Try to calculate multiplier and divider up to 4 times */ | |
93 | while (((mul == 0) || (div == 0)) && (tried <= 3)) { | |
6ccf58ab | 94 | for (xdiv = 2; xdiv <= 0x80; xdiv++) |
1da177e4 LT |
95 | for (xmul = 1; xmul <= 0xfe; xmul++) |
96 | if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) == | |
97 | fsb + tried) { | |
98 | mul = xmul; | |
99 | div = xdiv; | |
100 | } | |
101 | tried++; | |
102 | } | |
103 | ||
104 | if ((mul == 0) || (div == 0)) | |
105 | return -1; | |
106 | ||
107 | return NFORCE2_PLL(mul, div); | |
108 | } | |
109 | ||
32ee8c3e | 110 | /** |
1da177e4 LT |
111 | * nforce2_write_pll - write PLL value to chipset |
112 | * @pll: PLL value | |
32ee8c3e | 113 | * |
1da177e4 LT |
114 | * Writes new FSB PLL value to chipset |
115 | */ | |
116 | static void nforce2_write_pll(int pll) | |
117 | { | |
118 | int temp; | |
119 | ||
120 | /* Set the pll addr. to 0x00 */ | |
b5c91666 | 121 | pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0); |
1da177e4 LT |
122 | |
123 | /* Now write the value in all 64 registers */ | |
32ee8c3e | 124 | for (temp = 0; temp <= 0x3f; temp++) |
b5c91666 | 125 | pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); |
1da177e4 LT |
126 | |
127 | return; | |
128 | } | |
129 | ||
32ee8c3e | 130 | /** |
1da177e4 LT |
131 | * nforce2_fsb_read - Read FSB |
132 | * | |
133 | * Read FSB from chipset | |
134 | * If bootfsb != 0, return FSB at boot-time | |
135 | */ | |
136 | static unsigned int nforce2_fsb_read(int bootfsb) | |
137 | { | |
138 | struct pci_dev *nforce2_sub5; | |
139 | u32 fsb, temp = 0; | |
140 | ||
1da177e4 | 141 | /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */ |
b5c91666 DJ |
142 | nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF, |
143 | PCI_ANY_ID, PCI_ANY_ID, NULL); | |
1da177e4 LT |
144 | if (!nforce2_sub5) |
145 | return 0; | |
146 | ||
147 | pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb); | |
148 | fsb /= 1000000; | |
32ee8c3e | 149 | |
1da177e4 | 150 | /* Check if PLL register is already set */ |
b5c91666 | 151 | pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp); |
32ee8c3e | 152 | |
219835f1 | 153 | if (bootfsb || !temp) |
1da177e4 | 154 | return fsb; |
219835f1 | 155 | |
1da177e4 | 156 | /* Use PLL register FSB value */ |
b5c91666 | 157 | pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp); |
1da177e4 LT |
158 | fsb = nforce2_calc_fsb(temp); |
159 | ||
160 | return fsb; | |
161 | } | |
162 | ||
32ee8c3e | 163 | /** |
1da177e4 LT |
164 | * nforce2_set_fsb - set new FSB |
165 | * @fsb: New FSB | |
32ee8c3e | 166 | * |
1da177e4 LT |
167 | * Sets new FSB |
168 | */ | |
169 | static int nforce2_set_fsb(unsigned int fsb) | |
170 | { | |
d4921914 | 171 | u32 temp = 0; |
1da177e4 LT |
172 | unsigned int tfsb; |
173 | int diff; | |
d4921914 | 174 | int pll = 0; |
1da177e4 LT |
175 | |
176 | if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) { | |
20174b65 | 177 | printk(KERN_ERR PFX "FSB %d is out of range!\n", fsb); |
1da177e4 LT |
178 | return -EINVAL; |
179 | } | |
32ee8c3e | 180 | |
1da177e4 LT |
181 | tfsb = nforce2_fsb_read(0); |
182 | if (!tfsb) { | |
20174b65 | 183 | printk(KERN_ERR PFX "Error while reading the FSB\n"); |
1da177e4 LT |
184 | return -EINVAL; |
185 | } | |
186 | ||
187 | /* First write? Then set actual value */ | |
b5c91666 | 188 | pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp); |
1da177e4 LT |
189 | if (!temp) { |
190 | pll = nforce2_calc_pll(tfsb); | |
191 | ||
192 | if (pll < 0) | |
193 | return -EINVAL; | |
194 | ||
195 | nforce2_write_pll(pll); | |
196 | } | |
197 | ||
198 | /* Enable write access */ | |
199 | temp = 0x01; | |
b5c91666 | 200 | pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp); |
1da177e4 LT |
201 | |
202 | diff = tfsb - fsb; | |
203 | ||
204 | if (!diff) | |
205 | return 0; | |
206 | ||
207 | while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) { | |
208 | if (diff < 0) | |
209 | tfsb++; | |
210 | else | |
211 | tfsb--; | |
212 | ||
213 | /* Calculate the PLL reg. value */ | |
219835f1 PC |
214 | pll = nforce2_calc_pll(tfsb); |
215 | if (pll == -1) | |
1da177e4 | 216 | return -EINVAL; |
32ee8c3e | 217 | |
1da177e4 LT |
218 | nforce2_write_pll(pll); |
219 | #ifdef NFORCE2_DELAY | |
220 | mdelay(NFORCE2_DELAY); | |
221 | #endif | |
222 | } | |
223 | ||
224 | temp = 0x40; | |
b5c91666 | 225 | pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp); |
1da177e4 LT |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
230 | /** | |
231 | * nforce2_get - get the CPU frequency | |
232 | * @cpu: CPU number | |
32ee8c3e | 233 | * |
1da177e4 LT |
234 | * Returns the CPU frequency |
235 | */ | |
236 | static unsigned int nforce2_get(unsigned int cpu) | |
237 | { | |
238 | if (cpu) | |
239 | return 0; | |
240 | return nforce2_fsb_read(0) * fid * 100; | |
241 | } | |
242 | ||
243 | /** | |
244 | * nforce2_target - set a new CPUFreq policy | |
245 | * @policy: new policy | |
246 | * @target_freq: the target frequency | |
b5c91666 DJ |
247 | * @relation: how that frequency relates to achieved frequency |
248 | * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H) | |
1da177e4 LT |
249 | * |
250 | * Sets a new CPUFreq policy. | |
251 | */ | |
252 | static int nforce2_target(struct cpufreq_policy *policy, | |
253 | unsigned int target_freq, unsigned int relation) | |
254 | { | |
219835f1 | 255 | /* unsigned long flags; */ |
1da177e4 LT |
256 | struct cpufreq_freqs freqs; |
257 | unsigned int target_fsb; | |
258 | ||
259 | if ((target_freq > policy->max) || (target_freq < policy->min)) | |
260 | return -EINVAL; | |
261 | ||
262 | target_fsb = target_freq / (fid * 100); | |
263 | ||
264 | freqs.old = nforce2_get(policy->cpu); | |
265 | freqs.new = target_fsb * fid * 100; | |
1da177e4 LT |
266 | |
267 | if (freqs.old == freqs.new) | |
268 | return 0; | |
269 | ||
2d06d8c4 | 270 | pr_debug("Old CPU frequency %d kHz, new %d kHz\n", |
1da177e4 LT |
271 | freqs.old, freqs.new); |
272 | ||
b43a7ffb | 273 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
1da177e4 LT |
274 | |
275 | /* Disable IRQs */ | |
219835f1 | 276 | /* local_irq_save(flags); */ |
1da177e4 LT |
277 | |
278 | if (nforce2_set_fsb(target_fsb) < 0) | |
20174b65 | 279 | printk(KERN_ERR PFX "Changing FSB to %d failed\n", |
219835f1 | 280 | target_fsb); |
1da177e4 | 281 | else |
2d06d8c4 | 282 | pr_debug("Changed FSB successfully to %d\n", |
219835f1 | 283 | target_fsb); |
1da177e4 LT |
284 | |
285 | /* Enable IRQs */ | |
219835f1 | 286 | /* local_irq_restore(flags); */ |
1da177e4 | 287 | |
b43a7ffb | 288 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
1da177e4 LT |
289 | |
290 | return 0; | |
291 | } | |
292 | ||
293 | /** | |
294 | * nforce2_verify - verifies a new CPUFreq policy | |
295 | * @policy: new policy | |
296 | */ | |
297 | static int nforce2_verify(struct cpufreq_policy *policy) | |
298 | { | |
299 | unsigned int fsb_pol_max; | |
300 | ||
301 | fsb_pol_max = policy->max / (fid * 100); | |
302 | ||
303 | if (policy->min < (fsb_pol_max * fid * 100)) | |
304 | policy->max = (fsb_pol_max + 1) * fid * 100; | |
305 | ||
306 | cpufreq_verify_within_limits(policy, | |
219835f1 PC |
307 | policy->cpuinfo.min_freq, |
308 | policy->cpuinfo.max_freq); | |
1da177e4 LT |
309 | return 0; |
310 | } | |
311 | ||
312 | static int nforce2_cpu_init(struct cpufreq_policy *policy) | |
313 | { | |
314 | unsigned int fsb; | |
315 | unsigned int rfid; | |
316 | ||
317 | /* capability check */ | |
318 | if (policy->cpu != 0) | |
319 | return -ENODEV; | |
320 | ||
321 | /* Get current FSB */ | |
322 | fsb = nforce2_fsb_read(0); | |
323 | ||
324 | if (!fsb) | |
325 | return -EIO; | |
326 | ||
327 | /* FIX: Get FID from CPU */ | |
328 | if (!fid) { | |
329 | if (!cpu_khz) { | |
20174b65 DJ |
330 | printk(KERN_WARNING PFX |
331 | "cpu_khz not set, can't calculate multiplier!\n"); | |
1da177e4 LT |
332 | return -ENODEV; |
333 | } | |
334 | ||
335 | fid = cpu_khz / (fsb * 100); | |
336 | rfid = fid % 5; | |
337 | ||
338 | if (rfid) { | |
339 | if (rfid > 2) | |
340 | fid += 5 - rfid; | |
341 | else | |
342 | fid -= rfid; | |
343 | } | |
344 | } | |
345 | ||
20174b65 | 346 | printk(KERN_INFO PFX "FSB currently at %i MHz, FID %d.%d\n", fsb, |
1da177e4 | 347 | fid / 10, fid % 10); |
32ee8c3e | 348 | |
1da177e4 LT |
349 | /* Set maximum FSB to FSB at boot time */ |
350 | max_fsb = nforce2_fsb_read(1); | |
32ee8c3e | 351 | |
219835f1 | 352 | if (!max_fsb) |
1da177e4 LT |
353 | return -EIO; |
354 | ||
355 | if (!min_fsb) | |
356 | min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE; | |
357 | ||
358 | if (min_fsb < NFORCE2_MIN_FSB) | |
359 | min_fsb = NFORCE2_MIN_FSB; | |
360 | ||
361 | /* cpuinfo and default policy values */ | |
eb2f50ff VK |
362 | policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100; |
363 | policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100; | |
1da177e4 LT |
364 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
365 | policy->cur = nforce2_get(policy->cpu); | |
1da177e4 LT |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
370 | static int nforce2_cpu_exit(struct cpufreq_policy *policy) | |
371 | { | |
372 | return 0; | |
373 | } | |
374 | ||
221dee28 | 375 | static struct cpufreq_driver nforce2_driver = { |
1da177e4 LT |
376 | .name = "nforce2", |
377 | .verify = nforce2_verify, | |
378 | .target = nforce2_target, | |
379 | .get = nforce2_get, | |
380 | .init = nforce2_cpu_init, | |
381 | .exit = nforce2_cpu_exit, | |
1da177e4 LT |
382 | }; |
383 | ||
fa8031ae AK |
384 | #ifdef MODULE |
385 | static DEFINE_PCI_DEVICE_TABLE(nforce2_ids) = { | |
386 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 }, | |
387 | {} | |
388 | }; | |
389 | MODULE_DEVICE_TABLE(pci, nforce2_ids); | |
390 | #endif | |
391 | ||
1da177e4 LT |
392 | /** |
393 | * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic | |
394 | * | |
395 | * Detects nForce2 A2 and C1 stepping | |
32ee8c3e | 396 | * |
1da177e4 | 397 | */ |
b2a33c17 | 398 | static int nforce2_detect_chipset(void) |
1da177e4 | 399 | { |
b5c91666 | 400 | nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, |
32ee8c3e DJ |
401 | PCI_DEVICE_ID_NVIDIA_NFORCE2, |
402 | PCI_ANY_ID, PCI_ANY_ID, NULL); | |
1da177e4 | 403 | |
b5c91666 | 404 | if (nforce2_dev == NULL) |
1da177e4 LT |
405 | return -ENODEV; |
406 | ||
20174b65 | 407 | printk(KERN_INFO PFX "Detected nForce2 chipset revision %X\n", |
b5c91666 | 408 | nforce2_dev->revision); |
20174b65 DJ |
409 | printk(KERN_INFO PFX |
410 | "FSB changing is maybe unstable and can lead to " | |
b5c91666 | 411 | "crashes and data loss.\n"); |
1da177e4 LT |
412 | |
413 | return 0; | |
414 | } | |
415 | ||
416 | /** | |
417 | * nforce2_init - initializes the nForce2 CPUFreq driver | |
418 | * | |
419 | * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported | |
420 | * devices, -EINVAL on problems during initiatization, and zero on | |
421 | * success. | |
422 | */ | |
423 | static int __init nforce2_init(void) | |
424 | { | |
425 | /* TODO: do we need to detect the processor? */ | |
426 | ||
427 | /* detect chipset */ | |
428 | if (nforce2_detect_chipset()) { | |
eb3092ce | 429 | printk(KERN_INFO PFX "No nForce2 chipset.\n"); |
1da177e4 LT |
430 | return -ENODEV; |
431 | } | |
432 | ||
433 | return cpufreq_register_driver(&nforce2_driver); | |
434 | } | |
435 | ||
436 | /** | |
437 | * nforce2_exit - unregisters cpufreq module | |
438 | * | |
439 | * Unregisters nForce2 FSB change support. | |
440 | */ | |
441 | static void __exit nforce2_exit(void) | |
442 | { | |
443 | cpufreq_unregister_driver(&nforce2_driver); | |
444 | } | |
445 | ||
446 | module_init(nforce2_init); | |
447 | module_exit(nforce2_exit); | |
448 |