Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f56aad1d VK |
2 | /* |
3 | * Copyright (C) 2016 Linaro. | |
4 | * Viresh Kumar <viresh.kumar@linaro.org> | |
f56aad1d VK |
5 | */ |
6 | ||
7 | #include <linux/err.h> | |
8 | #include <linux/of.h> | |
edeec420 | 9 | #include <linux/of_device.h> |
f56aad1d VK |
10 | #include <linux/platform_device.h> |
11 | ||
297a6622 VK |
12 | #include "cpufreq-dt.h" |
13 | ||
edeec420 VK |
14 | /* |
15 | * Machines for which the cpufreq device is *always* created, mostly used for | |
16 | * platforms using "operating-points" (V1) property. | |
17 | */ | |
18 | static const struct of_device_id whitelist[] __initconst = { | |
117d4f59 VK |
19 | { .compatible = "allwinner,sun4i-a10", }, |
20 | { .compatible = "allwinner,sun5i-a10s", }, | |
21 | { .compatible = "allwinner,sun5i-a13", }, | |
22 | { .compatible = "allwinner,sun5i-r8", }, | |
23 | { .compatible = "allwinner,sun6i-a31", }, | |
24 | { .compatible = "allwinner,sun6i-a31s", }, | |
25 | { .compatible = "allwinner,sun7i-a20", }, | |
26 | { .compatible = "allwinner,sun8i-a23", }, | |
117d4f59 VK |
27 | { .compatible = "allwinner,sun8i-a83t", }, |
28 | { .compatible = "allwinner,sun8i-h3", }, | |
29 | ||
e11b6293 HT |
30 | { .compatible = "apm,xgene-shadowcat", }, |
31 | ||
650ec6cf LW |
32 | { .compatible = "arm,integrator-ap", }, |
33 | { .compatible = "arm,integrator-cp", }, | |
34 | ||
a0df7734 | 35 | { .compatible = "hisilicon,hi3660", }, |
3920be47 | 36 | |
7ead83f6 VK |
37 | { .compatible = "fsl,imx27", }, |
38 | { .compatible = "fsl,imx51", }, | |
39 | { .compatible = "fsl,imx53", }, | |
7ead83f6 | 40 | |
a59511d1 | 41 | { .compatible = "marvell,berlin", }, |
dcd2ea41 RJ |
42 | { .compatible = "marvell,pxa250", }, |
43 | { .compatible = "marvell,pxa270", }, | |
a59511d1 | 44 | |
2249c00a VK |
45 | { .compatible = "samsung,exynos3250", }, |
46 | { .compatible = "samsung,exynos4210", }, | |
2249c00a VK |
47 | { .compatible = "samsung,exynos5250", }, |
48 | #ifndef CONFIG_BL_SWITCHER | |
2249c00a VK |
49 | { .compatible = "samsung,exynos5800", }, |
50 | #endif | |
7694ca6e | 51 | |
a399dc9f VK |
52 | { .compatible = "renesas,emev2", }, |
53 | { .compatible = "renesas,r7s72100", }, | |
54 | { .compatible = "renesas,r8a73a4", }, | |
55 | { .compatible = "renesas,r8a7740", }, | |
f0da898b | 56 | { .compatible = "renesas,r8a7743", }, |
d1e13031 | 57 | { .compatible = "renesas,r8a7744", }, |
f0da898b | 58 | { .compatible = "renesas,r8a7745", }, |
a399dc9f VK |
59 | { .compatible = "renesas,r8a7778", }, |
60 | { .compatible = "renesas,r8a7779", }, | |
61 | { .compatible = "renesas,r8a7790", }, | |
62 | { .compatible = "renesas,r8a7791", }, | |
ffdf8b86 | 63 | { .compatible = "renesas,r8a7792", }, |
a399dc9f VK |
64 | { .compatible = "renesas,r8a7793", }, |
65 | { .compatible = "renesas,r8a7794", }, | |
66 | { .compatible = "renesas,sh73a0", }, | |
67 | ||
014400c1 FX |
68 | { .compatible = "rockchip,rk2928", }, |
69 | { .compatible = "rockchip,rk3036", }, | |
70 | { .compatible = "rockchip,rk3066a", }, | |
71 | { .compatible = "rockchip,rk3066b", }, | |
72 | { .compatible = "rockchip,rk3188", }, | |
73 | { .compatible = "rockchip,rk3228", }, | |
74 | { .compatible = "rockchip,rk3288", }, | |
319af40a | 75 | { .compatible = "rockchip,rk3328", }, |
014400c1 FX |
76 | { .compatible = "rockchip,rk3366", }, |
77 | { .compatible = "rockchip,rk3368", }, | |
9d21d33c DT |
78 | { .compatible = "rockchip,rk3399", |
79 | .data = &(struct cpufreq_dt_platform_data) | |
80 | { .have_governor_per_policy = true, }, | |
81 | }, | |
014400c1 | 82 | |
ff6c349f LW |
83 | { .compatible = "st-ericsson,u8500", }, |
84 | { .compatible = "st-ericsson,u8540", }, | |
85 | { .compatible = "st-ericsson,u9500", }, | |
86 | { .compatible = "st-ericsson,u9540", }, | |
87 | ||
7694ca6e VK |
88 | { .compatible = "ti,omap2", }, |
89 | { .compatible = "ti,omap3", }, | |
90 | { .compatible = "ti,omap4", }, | |
91 | { .compatible = "ti,omap5", }, | |
5e4249c6 VK |
92 | |
93 | { .compatible = "xlnx,zynq-7000", }, | |
a5685781 | 94 | { .compatible = "xlnx,zynqmp", }, |
bd37e022 WY |
95 | |
96 | { } | |
f56aad1d VK |
97 | }; |
98 | ||
edeec420 VK |
99 | /* |
100 | * Machines for which the cpufreq device is *not* created, mostly used for | |
101 | * platforms using "operating-points-v2" property. | |
102 | */ | |
103 | static const struct of_device_id blacklist[] __initconst = { | |
f328584f YL |
104 | { .compatible = "allwinner,sun50i-h6", }, |
105 | ||
ff76898c VK |
106 | { .compatible = "calxeda,highbank", }, |
107 | { .compatible = "calxeda,ecx-2000", }, | |
108 | ||
e6abacab | 109 | { .compatible = "fsl,imx7d", }, |
4d28ba1d LC |
110 | { .compatible = "fsl,imx8mq", }, |
111 | { .compatible = "fsl,imx8mm", }, | |
8ec50350 | 112 | { .compatible = "fsl,imx8mn", }, |
4d28ba1d | 113 | |
ff76898c VK |
114 | { .compatible = "marvell,armadaxp", }, |
115 | ||
6066998c AC |
116 | { .compatible = "mediatek,mt2701", }, |
117 | { .compatible = "mediatek,mt2712", }, | |
118 | { .compatible = "mediatek,mt7622", }, | |
119 | { .compatible = "mediatek,mt7623", }, | |
120 | { .compatible = "mediatek,mt817x", }, | |
121 | { .compatible = "mediatek,mt8173", }, | |
122 | { .compatible = "mediatek,mt8176", }, | |
9176b425 | 123 | { .compatible = "mediatek,mt8183", }, |
6066998c | 124 | |
ff76898c | 125 | { .compatible = "nvidia,tegra124", }, |
43c36002 | 126 | { .compatible = "nvidia,tegra210", }, |
ff76898c | 127 | |
46e2856b IL |
128 | { .compatible = "qcom,apq8096", }, |
129 | { .compatible = "qcom,msm8996", }, | |
248b5f29 | 130 | { .compatible = "qcom,qcs404", }, |
46e2856b | 131 | |
ff76898c VK |
132 | { .compatible = "st,stih407", }, |
133 | { .compatible = "st,stih410", }, | |
134 | ||
135 | { .compatible = "sigma,tango4", }, | |
136 | ||
d477bf3a SM |
137 | { .compatible = "ti,am33xx", }, |
138 | { .compatible = "ti,am43", }, | |
139 | { .compatible = "ti,dra7", }, | |
140 | ||
edeec420 VK |
141 | { } |
142 | }; | |
143 | ||
144 | static bool __init cpu0_node_has_opp_v2_prop(void) | |
145 | { | |
146 | struct device_node *np = of_cpu_device_node_get(0); | |
147 | bool ret = false; | |
148 | ||
149 | if (of_get_property(np, "operating-points-v2", NULL)) | |
150 | ret = true; | |
151 | ||
152 | of_node_put(np); | |
153 | return ret; | |
154 | } | |
155 | ||
f56aad1d VK |
156 | static int __init cpufreq_dt_platdev_init(void) |
157 | { | |
158 | struct device_node *np = of_find_node_by_path("/"); | |
ca5eda5d | 159 | const struct of_device_id *match; |
edeec420 | 160 | const void *data = NULL; |
f56aad1d VK |
161 | |
162 | if (!np) | |
163 | return -ENODEV; | |
164 | ||
edeec420 VK |
165 | match = of_match_node(whitelist, np); |
166 | if (match) { | |
167 | data = match->data; | |
168 | goto create_pdev; | |
169 | } | |
170 | ||
171 | if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np)) | |
172 | goto create_pdev; | |
173 | ||
ca5eda5d | 174 | of_node_put(np); |
edeec420 | 175 | return -ENODEV; |
f56aad1d | 176 | |
edeec420 VK |
177 | create_pdev: |
178 | of_node_put(np); | |
297a6622 | 179 | return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt", |
edeec420 | 180 | -1, data, |
297a6622 | 181 | sizeof(struct cpufreq_dt_platform_data))); |
f56aad1d VK |
182 | } |
183 | device_initcall(cpufreq_dt_platdev_init); |