Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f56aad1d VK |
2 | /* |
3 | * Copyright (C) 2016 Linaro. | |
4 | * Viresh Kumar <viresh.kumar@linaro.org> | |
f56aad1d VK |
5 | */ |
6 | ||
7 | #include <linux/err.h> | |
8 | #include <linux/of.h> | |
9 | #include <linux/platform_device.h> | |
10 | ||
297a6622 VK |
11 | #include "cpufreq-dt.h" |
12 | ||
edeec420 VK |
13 | /* |
14 | * Machines for which the cpufreq device is *always* created, mostly used for | |
15 | * platforms using "operating-points" (V1) property. | |
16 | */ | |
4814d9c5 | 17 | static const struct of_device_id allowlist[] __initconst = { |
117d4f59 VK |
18 | { .compatible = "allwinner,sun4i-a10", }, |
19 | { .compatible = "allwinner,sun5i-a10s", }, | |
20 | { .compatible = "allwinner,sun5i-a13", }, | |
21 | { .compatible = "allwinner,sun5i-r8", }, | |
22 | { .compatible = "allwinner,sun6i-a31", }, | |
23 | { .compatible = "allwinner,sun6i-a31s", }, | |
24 | { .compatible = "allwinner,sun7i-a20", }, | |
25 | { .compatible = "allwinner,sun8i-a23", }, | |
117d4f59 VK |
26 | { .compatible = "allwinner,sun8i-a83t", }, |
27 | { .compatible = "allwinner,sun8i-h3", }, | |
28 | ||
e11b6293 HT |
29 | { .compatible = "apm,xgene-shadowcat", }, |
30 | ||
650ec6cf LW |
31 | { .compatible = "arm,integrator-ap", }, |
32 | { .compatible = "arm,integrator-cp", }, | |
33 | ||
a0df7734 | 34 | { .compatible = "hisilicon,hi3660", }, |
3920be47 | 35 | |
7ead83f6 VK |
36 | { .compatible = "fsl,imx27", }, |
37 | { .compatible = "fsl,imx51", }, | |
38 | { .compatible = "fsl,imx53", }, | |
7ead83f6 | 39 | |
a59511d1 | 40 | { .compatible = "marvell,berlin", }, |
dcd2ea41 RJ |
41 | { .compatible = "marvell,pxa250", }, |
42 | { .compatible = "marvell,pxa270", }, | |
a59511d1 | 43 | |
2249c00a VK |
44 | { .compatible = "samsung,exynos3250", }, |
45 | { .compatible = "samsung,exynos4210", }, | |
2249c00a VK |
46 | { .compatible = "samsung,exynos5250", }, |
47 | #ifndef CONFIG_BL_SWITCHER | |
2249c00a VK |
48 | { .compatible = "samsung,exynos5800", }, |
49 | #endif | |
7694ca6e | 50 | |
a399dc9f VK |
51 | { .compatible = "renesas,emev2", }, |
52 | { .compatible = "renesas,r7s72100", }, | |
53 | { .compatible = "renesas,r8a73a4", }, | |
54 | { .compatible = "renesas,r8a7740", }, | |
a6d1bfa0 | 55 | { .compatible = "renesas,r8a7742", }, |
f0da898b | 56 | { .compatible = "renesas,r8a7743", }, |
d1e13031 | 57 | { .compatible = "renesas,r8a7744", }, |
f0da898b | 58 | { .compatible = "renesas,r8a7745", }, |
a399dc9f VK |
59 | { .compatible = "renesas,r8a7778", }, |
60 | { .compatible = "renesas,r8a7779", }, | |
61 | { .compatible = "renesas,r8a7790", }, | |
62 | { .compatible = "renesas,r8a7791", }, | |
ffdf8b86 | 63 | { .compatible = "renesas,r8a7792", }, |
a399dc9f VK |
64 | { .compatible = "renesas,r8a7793", }, |
65 | { .compatible = "renesas,r8a7794", }, | |
66 | { .compatible = "renesas,sh73a0", }, | |
67 | ||
014400c1 FX |
68 | { .compatible = "rockchip,rk2928", }, |
69 | { .compatible = "rockchip,rk3036", }, | |
70 | { .compatible = "rockchip,rk3066a", }, | |
71 | { .compatible = "rockchip,rk3066b", }, | |
72 | { .compatible = "rockchip,rk3188", }, | |
73 | { .compatible = "rockchip,rk3228", }, | |
74 | { .compatible = "rockchip,rk3288", }, | |
319af40a | 75 | { .compatible = "rockchip,rk3328", }, |
014400c1 FX |
76 | { .compatible = "rockchip,rk3366", }, |
77 | { .compatible = "rockchip,rk3368", }, | |
9d21d33c DT |
78 | { .compatible = "rockchip,rk3399", |
79 | .data = &(struct cpufreq_dt_platform_data) | |
80 | { .have_governor_per_policy = true, }, | |
81 | }, | |
014400c1 | 82 | |
ff6c349f LW |
83 | { .compatible = "st-ericsson,u8500", }, |
84 | { .compatible = "st-ericsson,u8540", }, | |
85 | { .compatible = "st-ericsson,u9500", }, | |
86 | { .compatible = "st-ericsson,u9540", }, | |
87 | ||
7694ca6e | 88 | { .compatible = "ti,omap2", }, |
7694ca6e VK |
89 | { .compatible = "ti,omap4", }, |
90 | { .compatible = "ti,omap5", }, | |
5e4249c6 VK |
91 | |
92 | { .compatible = "xlnx,zynq-7000", }, | |
a5685781 | 93 | { .compatible = "xlnx,zynqmp", }, |
bd37e022 WY |
94 | |
95 | { } | |
f56aad1d VK |
96 | }; |
97 | ||
edeec420 VK |
98 | /* |
99 | * Machines for which the cpufreq device is *not* created, mostly used for | |
100 | * platforms using "operating-points-v2" property. | |
101 | */ | |
4814d9c5 | 102 | static const struct of_device_id blocklist[] __initconst = { |
f328584f YL |
103 | { .compatible = "allwinner,sun50i-h6", }, |
104 | ||
6286bbb4 HM |
105 | { .compatible = "apple,arm-platform", }, |
106 | ||
fbb31cb8 SH |
107 | { .compatible = "arm,vexpress", }, |
108 | ||
ff76898c VK |
109 | { .compatible = "calxeda,highbank", }, |
110 | { .compatible = "calxeda,ecx-2000", }, | |
111 | ||
a08e1b6c | 112 | { .compatible = "fsl,imx7ulp", }, |
e6abacab | 113 | { .compatible = "fsl,imx7d", }, |
bc8b0c27 | 114 | { .compatible = "fsl,imx7s", }, |
4d28ba1d LC |
115 | { .compatible = "fsl,imx8mq", }, |
116 | { .compatible = "fsl,imx8mm", }, | |
8ec50350 | 117 | { .compatible = "fsl,imx8mn", }, |
24f371f7 | 118 | { .compatible = "fsl,imx8mp", }, |
4d28ba1d | 119 | |
ff76898c VK |
120 | { .compatible = "marvell,armadaxp", }, |
121 | ||
6066998c AC |
122 | { .compatible = "mediatek,mt2701", }, |
123 | { .compatible = "mediatek,mt2712", }, | |
124 | { .compatible = "mediatek,mt7622", }, | |
125 | { .compatible = "mediatek,mt7623", }, | |
de4ca309 | 126 | { .compatible = "mediatek,mt8167", }, |
6066998c AC |
127 | { .compatible = "mediatek,mt817x", }, |
128 | { .compatible = "mediatek,mt8173", }, | |
129 | { .compatible = "mediatek,mt8176", }, | |
9176b425 | 130 | { .compatible = "mediatek,mt8183", }, |
be4b61ec | 131 | { .compatible = "mediatek,mt8186", }, |
70d99a8f | 132 | { .compatible = "mediatek,mt8365", }, |
75118c8e | 133 | { .compatible = "mediatek,mt8516", }, |
6066998c | 134 | |
26a7a475 DO |
135 | { .compatible = "nvidia,tegra20", }, |
136 | { .compatible = "nvidia,tegra30", }, | |
ff76898c | 137 | { .compatible = "nvidia,tegra124", }, |
43c36002 | 138 | { .compatible = "nvidia,tegra210", }, |
01c5bb0c | 139 | { .compatible = "nvidia,tegra234", }, |
ff76898c | 140 | |
46e2856b IL |
141 | { .compatible = "qcom,apq8096", }, |
142 | { .compatible = "qcom,msm8996", }, | |
248b5f29 | 143 | { .compatible = "qcom,qcs404", }, |
5e79d6d9 | 144 | { .compatible = "qcom,sa8155p" }, |
72951a77 | 145 | { .compatible = "qcom,sa8540p" }, |
fb091802 | 146 | { .compatible = "qcom,sc7180", }, |
17a8b0b6 | 147 | { .compatible = "qcom,sc7280", }, |
d66cd5de | 148 | { .compatible = "qcom,sc8180x", }, |
72951a77 | 149 | { .compatible = "qcom,sc8280xp", }, |
49ef1221 | 150 | { .compatible = "qcom,sdm845", }, |
0612d928 | 151 | { .compatible = "qcom,sm6115", }, |
5e79d6d9 | 152 | { .compatible = "qcom,sm6350", }, |
faf28e24 | 153 | { .compatible = "qcom,sm6375", }, |
417598f9 | 154 | { .compatible = "qcom,sm7225", }, |
5d79e5ce | 155 | { .compatible = "qcom,sm8150", }, |
5e79d6d9 BA |
156 | { .compatible = "qcom,sm8250", }, |
157 | { .compatible = "qcom,sm8350", }, | |
46e2856b | 158 | |
ff76898c VK |
159 | { .compatible = "st,stih407", }, |
160 | { .compatible = "st,stih410", }, | |
305accf3 | 161 | { .compatible = "st,stih418", }, |
ff76898c | 162 | |
d477bf3a SM |
163 | { .compatible = "ti,am33xx", }, |
164 | { .compatible = "ti,am43", }, | |
165 | { .compatible = "ti,dra7", }, | |
b7dbe349 | 166 | { .compatible = "ti,omap3", }, |
e66e20d7 | 167 | { .compatible = "ti,am625", }, |
d477bf3a | 168 | |
a8811ec7 AS |
169 | { .compatible = "qcom,ipq8064", }, |
170 | { .compatible = "qcom,apq8064", }, | |
171 | { .compatible = "qcom,msm8974", }, | |
172 | { .compatible = "qcom,msm8960", }, | |
173 | ||
edeec420 VK |
174 | { } |
175 | }; | |
176 | ||
177 | static bool __init cpu0_node_has_opp_v2_prop(void) | |
178 | { | |
179 | struct device_node *np = of_cpu_device_node_get(0); | |
180 | bool ret = false; | |
181 | ||
b8f3a396 | 182 | if (of_property_present(np, "operating-points-v2")) |
edeec420 VK |
183 | ret = true; |
184 | ||
185 | of_node_put(np); | |
186 | return ret; | |
187 | } | |
188 | ||
f56aad1d VK |
189 | static int __init cpufreq_dt_platdev_init(void) |
190 | { | |
191 | struct device_node *np = of_find_node_by_path("/"); | |
ca5eda5d | 192 | const struct of_device_id *match; |
edeec420 | 193 | const void *data = NULL; |
f56aad1d VK |
194 | |
195 | if (!np) | |
196 | return -ENODEV; | |
197 | ||
4814d9c5 | 198 | match = of_match_node(allowlist, np); |
edeec420 VK |
199 | if (match) { |
200 | data = match->data; | |
201 | goto create_pdev; | |
202 | } | |
203 | ||
4814d9c5 | 204 | if (cpu0_node_has_opp_v2_prop() && !of_match_node(blocklist, np)) |
edeec420 VK |
205 | goto create_pdev; |
206 | ||
ca5eda5d | 207 | of_node_put(np); |
edeec420 | 208 | return -ENODEV; |
f56aad1d | 209 | |
edeec420 VK |
210 | create_pdev: |
211 | of_node_put(np); | |
297a6622 | 212 | return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt", |
edeec420 | 213 | -1, data, |
297a6622 | 214 | sizeof(struct cpufreq_dt_platform_data))); |
f56aad1d | 215 | } |
57db08f4 | 216 | core_initcall(cpufreq_dt_platdev_init); |