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de322e08 MM |
1 | /* |
2 | * CPU frequency scaling for Broadcom SoCs with AVS firmware that | |
3 | * supports DVS or DVFS | |
4 | * | |
5 | * Copyright (c) 2016 Broadcom | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * "AVS" is the name of a firmware developed at Broadcom. It derives | |
19 | * its name from the technique called "Adaptive Voltage Scaling". | |
20 | * Adaptive voltage scaling was the original purpose of this firmware. | |
21 | * The AVS firmware still supports "AVS mode", where all it does is | |
22 | * adaptive voltage scaling. However, on some newer Broadcom SoCs, the | |
23 | * AVS Firmware, despite its unchanged name, also supports DFS mode and | |
24 | * DVFS mode. | |
25 | * | |
26 | * In the context of this document and the related driver, "AVS" by | |
27 | * itself always means the Broadcom firmware and never refers to the | |
28 | * technique called "Adaptive Voltage Scaling". | |
29 | * | |
30 | * The Broadcom STB AVS CPUfreq driver provides voltage and frequency | |
31 | * scaling on Broadcom SoCs using AVS firmware with support for DFS and | |
32 | * DVFS. The AVS firmware is running on its own co-processor. The | |
33 | * driver supports both uniprocessor (UP) and symmetric multiprocessor | |
34 | * (SMP) systems which share clock and voltage across all CPUs. | |
35 | * | |
36 | * Actual voltage and frequency scaling is done solely by the AVS | |
37 | * firmware. This driver does not change frequency or voltage itself. | |
38 | * It provides a standard CPUfreq interface to the rest of the kernel | |
39 | * and to userland. It interfaces with the AVS firmware to effect the | |
40 | * requested changes and to report back the current system status in a | |
41 | * way that is expected by existing tools. | |
42 | */ | |
43 | ||
44 | #include <linux/cpufreq.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/module.h> | |
48 | #include <linux/of_address.h> | |
49 | #include <linux/platform_device.h> | |
50 | #include <linux/semaphore.h> | |
51 | ||
52 | /* Max number of arguments AVS calls take */ | |
53 | #define AVS_MAX_CMD_ARGS 4 | |
54 | /* | |
55 | * This macro is used to generate AVS parameter register offsets. For | |
56 | * x >= AVS_MAX_CMD_ARGS, it returns 0 to protect against accidental memory | |
57 | * access outside of the parameter range. (Offset 0 is the first parameter.) | |
58 | */ | |
59 | #define AVS_PARAM_MULT(x) ((x) < AVS_MAX_CMD_ARGS ? (x) : 0) | |
60 | ||
61 | /* AVS Mailbox Register offsets */ | |
62 | #define AVS_MBOX_COMMAND 0x00 | |
63 | #define AVS_MBOX_STATUS 0x04 | |
64 | #define AVS_MBOX_VOLTAGE0 0x08 | |
65 | #define AVS_MBOX_TEMP0 0x0c | |
66 | #define AVS_MBOX_PV0 0x10 | |
67 | #define AVS_MBOX_MV0 0x14 | |
68 | #define AVS_MBOX_PARAM(x) (0x18 + AVS_PARAM_MULT(x) * sizeof(u32)) | |
69 | #define AVS_MBOX_REVISION 0x28 | |
70 | #define AVS_MBOX_PSTATE 0x2c | |
71 | #define AVS_MBOX_HEARTBEAT 0x30 | |
72 | #define AVS_MBOX_MAGIC 0x34 | |
73 | #define AVS_MBOX_SIGMA_HVT 0x38 | |
74 | #define AVS_MBOX_SIGMA_SVT 0x3c | |
75 | #define AVS_MBOX_VOLTAGE1 0x40 | |
76 | #define AVS_MBOX_TEMP1 0x44 | |
77 | #define AVS_MBOX_PV1 0x48 | |
78 | #define AVS_MBOX_MV1 0x4c | |
79 | #define AVS_MBOX_FREQUENCY 0x50 | |
80 | ||
81 | /* AVS Commands */ | |
82 | #define AVS_CMD_AVAILABLE 0x00 | |
83 | #define AVS_CMD_DISABLE 0x10 | |
84 | #define AVS_CMD_ENABLE 0x11 | |
85 | #define AVS_CMD_S2_ENTER 0x12 | |
86 | #define AVS_CMD_S2_EXIT 0x13 | |
87 | #define AVS_CMD_BBM_ENTER 0x14 | |
88 | #define AVS_CMD_BBM_EXIT 0x15 | |
89 | #define AVS_CMD_S3_ENTER 0x16 | |
90 | #define AVS_CMD_S3_EXIT 0x17 | |
91 | #define AVS_CMD_BALANCE 0x18 | |
92 | /* PMAP and P-STATE commands */ | |
93 | #define AVS_CMD_GET_PMAP 0x30 | |
94 | #define AVS_CMD_SET_PMAP 0x31 | |
95 | #define AVS_CMD_GET_PSTATE 0x40 | |
96 | #define AVS_CMD_SET_PSTATE 0x41 | |
97 | ||
98 | /* Different modes AVS supports (for GET_PMAP/SET_PMAP) */ | |
99 | #define AVS_MODE_AVS 0x0 | |
100 | #define AVS_MODE_DFS 0x1 | |
101 | #define AVS_MODE_DVS 0x2 | |
102 | #define AVS_MODE_DVFS 0x3 | |
103 | ||
104 | /* | |
105 | * PMAP parameter p1 | |
106 | * unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0 | |
107 | */ | |
108 | #define NDIV_INT_SHIFT 0 | |
109 | #define NDIV_INT_MASK 0x3ff | |
110 | #define PDIV_SHIFT 10 | |
111 | #define PDIV_MASK 0xf | |
112 | #define MDIV_P0_SHIFT 16 | |
113 | #define MDIV_P0_MASK 0xff | |
114 | /* | |
115 | * PMAP parameter p2 | |
116 | * mdiv_p4:31-24, mdiv_p3:23-16, mdiv_p2:15:8, mdiv_p1:7:0 | |
117 | */ | |
118 | #define MDIV_P1_SHIFT 0 | |
119 | #define MDIV_P1_MASK 0xff | |
120 | #define MDIV_P2_SHIFT 8 | |
121 | #define MDIV_P2_MASK 0xff | |
122 | #define MDIV_P3_SHIFT 16 | |
123 | #define MDIV_P3_MASK 0xff | |
124 | #define MDIV_P4_SHIFT 24 | |
125 | #define MDIV_P4_MASK 0xff | |
126 | ||
127 | /* Different P-STATES AVS supports (for GET_PSTATE/SET_PSTATE) */ | |
128 | #define AVS_PSTATE_P0 0x0 | |
129 | #define AVS_PSTATE_P1 0x1 | |
130 | #define AVS_PSTATE_P2 0x2 | |
131 | #define AVS_PSTATE_P3 0x3 | |
132 | #define AVS_PSTATE_P4 0x4 | |
133 | #define AVS_PSTATE_MAX AVS_PSTATE_P4 | |
134 | ||
135 | /* CPU L2 Interrupt Controller Registers */ | |
136 | #define AVS_CPU_L2_SET0 0x04 | |
137 | #define AVS_CPU_L2_INT_MASK BIT(31) | |
138 | ||
139 | /* AVS Command Status Values */ | |
140 | #define AVS_STATUS_CLEAR 0x00 | |
141 | /* Command/notification accepted */ | |
142 | #define AVS_STATUS_SUCCESS 0xf0 | |
143 | /* Command/notification rejected */ | |
144 | #define AVS_STATUS_FAILURE 0xff | |
145 | /* Invalid command/notification (unknown) */ | |
146 | #define AVS_STATUS_INVALID 0xf1 | |
147 | /* Non-AVS modes are not supported */ | |
148 | #define AVS_STATUS_NO_SUPP 0xf2 | |
149 | /* Cannot set P-State until P-Map supplied */ | |
150 | #define AVS_STATUS_NO_MAP 0xf3 | |
151 | /* Cannot change P-Map after initial P-Map set */ | |
152 | #define AVS_STATUS_MAP_SET 0xf4 | |
153 | /* Max AVS status; higher numbers are used for debugging */ | |
154 | #define AVS_STATUS_MAX 0xff | |
155 | ||
156 | /* Other AVS related constants */ | |
157 | #define AVS_LOOP_LIMIT 10000 | |
158 | #define AVS_TIMEOUT 300 /* in ms; expected completion is < 10ms */ | |
159 | #define AVS_FIRMWARE_MAGIC 0xa11600d1 | |
160 | ||
161 | #define BRCM_AVS_CPUFREQ_PREFIX "brcmstb-avs" | |
162 | #define BRCM_AVS_CPUFREQ_NAME BRCM_AVS_CPUFREQ_PREFIX "-cpufreq" | |
163 | #define BRCM_AVS_CPU_DATA "brcm,avs-cpu-data-mem" | |
164 | #define BRCM_AVS_CPU_INTR "brcm,avs-cpu-l2-intr" | |
165 | #define BRCM_AVS_HOST_INTR "sw_intr" | |
166 | ||
167 | struct pmap { | |
168 | unsigned int mode; | |
169 | unsigned int p1; | |
170 | unsigned int p2; | |
171 | unsigned int state; | |
172 | }; | |
173 | ||
174 | struct private_data { | |
175 | void __iomem *base; | |
176 | void __iomem *avs_intr_base; | |
177 | struct device *dev; | |
178 | struct completion done; | |
179 | struct semaphore sem; | |
180 | struct pmap pmap; | |
181 | }; | |
182 | ||
183 | static void __iomem *__map_region(const char *name) | |
184 | { | |
185 | struct device_node *np; | |
186 | void __iomem *ptr; | |
187 | ||
188 | np = of_find_compatible_node(NULL, NULL, name); | |
189 | if (!np) | |
190 | return NULL; | |
191 | ||
192 | ptr = of_iomap(np, 0); | |
193 | of_node_put(np); | |
194 | ||
195 | return ptr; | |
196 | } | |
197 | ||
198 | static int __issue_avs_command(struct private_data *priv, int cmd, bool is_send, | |
199 | u32 args[]) | |
200 | { | |
201 | unsigned long time_left = msecs_to_jiffies(AVS_TIMEOUT); | |
202 | void __iomem *base = priv->base; | |
203 | unsigned int i; | |
204 | int ret; | |
205 | u32 val; | |
206 | ||
207 | ret = down_interruptible(&priv->sem); | |
208 | if (ret) | |
209 | return ret; | |
210 | ||
211 | /* | |
212 | * Make sure no other command is currently running: cmd is 0 if AVS | |
213 | * co-processor is idle. Due to the guard above, we should almost never | |
214 | * have to wait here. | |
215 | */ | |
216 | for (i = 0, val = 1; val != 0 && i < AVS_LOOP_LIMIT; i++) | |
217 | val = readl(base + AVS_MBOX_COMMAND); | |
218 | ||
219 | /* Give the caller a chance to retry if AVS is busy. */ | |
220 | if (i == AVS_LOOP_LIMIT) { | |
221 | ret = -EAGAIN; | |
222 | goto out; | |
223 | } | |
224 | ||
225 | /* Clear status before we begin. */ | |
226 | writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); | |
227 | ||
228 | /* We need to send arguments for this command. */ | |
229 | if (args && is_send) { | |
230 | for (i = 0; i < AVS_MAX_CMD_ARGS; i++) | |
231 | writel(args[i], base + AVS_MBOX_PARAM(i)); | |
232 | } | |
233 | ||
234 | /* Protect from spurious interrupts. */ | |
235 | reinit_completion(&priv->done); | |
236 | ||
237 | /* Now issue the command & tell firmware to wake up to process it. */ | |
238 | writel(cmd, base + AVS_MBOX_COMMAND); | |
239 | writel(AVS_CPU_L2_INT_MASK, priv->avs_intr_base + AVS_CPU_L2_SET0); | |
240 | ||
241 | /* Wait for AVS co-processor to finish processing the command. */ | |
242 | time_left = wait_for_completion_timeout(&priv->done, time_left); | |
243 | ||
244 | /* | |
245 | * If the AVS status is not in the expected range, it means AVS didn't | |
246 | * complete our command in time, and we return an error. Also, if there | |
247 | * is no "time left", we timed out waiting for the interrupt. | |
248 | */ | |
249 | val = readl(base + AVS_MBOX_STATUS); | |
250 | if (time_left == 0 || val == 0 || val > AVS_STATUS_MAX) { | |
251 | dev_err(priv->dev, "AVS command %#x didn't complete in time\n", | |
252 | cmd); | |
253 | dev_err(priv->dev, " Time left: %u ms, AVS status: %#x\n", | |
254 | jiffies_to_msecs(time_left), val); | |
255 | ret = -ETIMEDOUT; | |
256 | goto out; | |
257 | } | |
258 | ||
259 | /* This command returned arguments, so we read them back. */ | |
260 | if (args && !is_send) { | |
261 | for (i = 0; i < AVS_MAX_CMD_ARGS; i++) | |
262 | args[i] = readl(base + AVS_MBOX_PARAM(i)); | |
263 | } | |
264 | ||
265 | /* Clear status to tell AVS co-processor we are done. */ | |
266 | writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); | |
267 | ||
268 | /* Convert firmware errors to errno's as much as possible. */ | |
269 | switch (val) { | |
270 | case AVS_STATUS_INVALID: | |
271 | ret = -EINVAL; | |
272 | break; | |
273 | case AVS_STATUS_NO_SUPP: | |
274 | ret = -ENOTSUPP; | |
275 | break; | |
276 | case AVS_STATUS_NO_MAP: | |
277 | ret = -ENOENT; | |
278 | break; | |
279 | case AVS_STATUS_MAP_SET: | |
280 | ret = -EEXIST; | |
281 | break; | |
282 | case AVS_STATUS_FAILURE: | |
283 | ret = -EIO; | |
284 | break; | |
285 | } | |
286 | ||
287 | out: | |
288 | up(&priv->sem); | |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
293 | static irqreturn_t irq_handler(int irq, void *data) | |
294 | { | |
295 | struct private_data *priv = data; | |
296 | ||
297 | /* AVS command completed execution. Wake up __issue_avs_command(). */ | |
298 | complete(&priv->done); | |
299 | ||
300 | return IRQ_HANDLED; | |
301 | } | |
302 | ||
303 | static char *brcm_avs_mode_to_string(unsigned int mode) | |
304 | { | |
305 | switch (mode) { | |
306 | case AVS_MODE_AVS: | |
307 | return "AVS"; | |
308 | case AVS_MODE_DFS: | |
309 | return "DFS"; | |
310 | case AVS_MODE_DVS: | |
311 | return "DVS"; | |
312 | case AVS_MODE_DVFS: | |
313 | return "DVFS"; | |
314 | } | |
315 | return NULL; | |
316 | } | |
317 | ||
318 | static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, | |
319 | unsigned int *ndiv) | |
320 | { | |
321 | *mdiv_p0 = (p1 >> MDIV_P0_SHIFT) & MDIV_P0_MASK; | |
322 | *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; | |
323 | *ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK; | |
324 | } | |
325 | ||
326 | static void brcm_avs_parse_p2(u32 p2, unsigned int *mdiv_p1, | |
327 | unsigned int *mdiv_p2, unsigned int *mdiv_p3, | |
328 | unsigned int *mdiv_p4) | |
329 | { | |
330 | *mdiv_p4 = (p2 >> MDIV_P4_SHIFT) & MDIV_P4_MASK; | |
331 | *mdiv_p3 = (p2 >> MDIV_P3_SHIFT) & MDIV_P3_MASK; | |
332 | *mdiv_p2 = (p2 >> MDIV_P2_SHIFT) & MDIV_P2_MASK; | |
333 | *mdiv_p1 = (p2 >> MDIV_P1_SHIFT) & MDIV_P1_MASK; | |
334 | } | |
335 | ||
336 | static int brcm_avs_get_pmap(struct private_data *priv, struct pmap *pmap) | |
337 | { | |
338 | u32 args[AVS_MAX_CMD_ARGS]; | |
339 | int ret; | |
340 | ||
341 | ret = __issue_avs_command(priv, AVS_CMD_GET_PMAP, false, args); | |
342 | if (ret || !pmap) | |
343 | return ret; | |
344 | ||
345 | pmap->mode = args[0]; | |
346 | pmap->p1 = args[1]; | |
347 | pmap->p2 = args[2]; | |
348 | pmap->state = args[3]; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int brcm_avs_set_pmap(struct private_data *priv, struct pmap *pmap) | |
354 | { | |
355 | u32 args[AVS_MAX_CMD_ARGS]; | |
356 | ||
357 | args[0] = pmap->mode; | |
358 | args[1] = pmap->p1; | |
359 | args[2] = pmap->p2; | |
360 | args[3] = pmap->state; | |
361 | ||
362 | return __issue_avs_command(priv, AVS_CMD_SET_PMAP, true, args); | |
363 | } | |
364 | ||
365 | static int brcm_avs_get_pstate(struct private_data *priv, unsigned int *pstate) | |
366 | { | |
367 | u32 args[AVS_MAX_CMD_ARGS]; | |
368 | int ret; | |
369 | ||
370 | ret = __issue_avs_command(priv, AVS_CMD_GET_PSTATE, false, args); | |
371 | if (ret) | |
372 | return ret; | |
373 | *pstate = args[0]; | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate) | |
379 | { | |
380 | u32 args[AVS_MAX_CMD_ARGS]; | |
381 | ||
382 | args[0] = pstate; | |
383 | ||
384 | return __issue_avs_command(priv, AVS_CMD_SET_PSTATE, true, args); | |
385 | } | |
386 | ||
4c5681fc | 387 | static u32 brcm_avs_get_voltage(void __iomem *base) |
de322e08 MM |
388 | { |
389 | return readl(base + AVS_MBOX_VOLTAGE1); | |
390 | } | |
391 | ||
4c5681fc | 392 | static u32 brcm_avs_get_frequency(void __iomem *base) |
de322e08 MM |
393 | { |
394 | return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */ | |
395 | } | |
396 | ||
397 | /* | |
398 | * We determine which frequencies are supported by cycling through all P-states | |
399 | * and reading back what frequency we are running at for each P-state. | |
400 | */ | |
401 | static struct cpufreq_frequency_table * | |
402 | brcm_avs_get_freq_table(struct device *dev, struct private_data *priv) | |
403 | { | |
404 | struct cpufreq_frequency_table *table; | |
405 | unsigned int pstate; | |
406 | int i, ret; | |
407 | ||
408 | /* Remember P-state for later */ | |
409 | ret = brcm_avs_get_pstate(priv, &pstate); | |
410 | if (ret) | |
411 | return ERR_PTR(ret); | |
412 | ||
a86854d0 | 413 | table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1, sizeof(*table), |
de322e08 MM |
414 | GFP_KERNEL); |
415 | if (!table) | |
416 | return ERR_PTR(-ENOMEM); | |
417 | ||
418 | for (i = AVS_PSTATE_P0; i <= AVS_PSTATE_MAX; i++) { | |
419 | ret = brcm_avs_set_pstate(priv, i); | |
420 | if (ret) | |
421 | return ERR_PTR(ret); | |
422 | table[i].frequency = brcm_avs_get_frequency(priv->base); | |
423 | table[i].driver_data = i; | |
424 | } | |
425 | table[i].frequency = CPUFREQ_TABLE_END; | |
426 | ||
427 | /* Restore P-state */ | |
428 | ret = brcm_avs_set_pstate(priv, pstate); | |
429 | if (ret) | |
430 | return ERR_PTR(ret); | |
431 | ||
432 | return table; | |
433 | } | |
434 | ||
435 | /* | |
436 | * To ensure the right firmware is running we need to | |
437 | * - check the MAGIC matches what we expect | |
438 | * - brcm_avs_get_pmap() doesn't return -ENOTSUPP or -EINVAL | |
439 | * We need to set up our interrupt handling before calling brcm_avs_get_pmap()! | |
440 | */ | |
441 | static bool brcm_avs_is_firmware_loaded(struct private_data *priv) | |
442 | { | |
443 | u32 magic; | |
444 | int rc; | |
445 | ||
446 | rc = brcm_avs_get_pmap(priv, NULL); | |
447 | magic = readl(priv->base + AVS_MBOX_MAGIC); | |
448 | ||
22a26cc6 FF |
449 | return (magic == AVS_FIRMWARE_MAGIC) && ((rc != -ENOTSUPP) || |
450 | (rc != -EINVAL)); | |
de322e08 MM |
451 | } |
452 | ||
453 | static unsigned int brcm_avs_cpufreq_get(unsigned int cpu) | |
454 | { | |
455 | struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); | |
456 | struct private_data *priv = policy->driver_data; | |
457 | ||
458 | return brcm_avs_get_frequency(priv->base); | |
459 | } | |
460 | ||
461 | static int brcm_avs_target_index(struct cpufreq_policy *policy, | |
462 | unsigned int index) | |
463 | { | |
464 | return brcm_avs_set_pstate(policy->driver_data, | |
465 | policy->freq_table[index].driver_data); | |
466 | } | |
467 | ||
468 | static int brcm_avs_suspend(struct cpufreq_policy *policy) | |
469 | { | |
470 | struct private_data *priv = policy->driver_data; | |
3c223c19 MM |
471 | int ret; |
472 | ||
473 | ret = brcm_avs_get_pmap(priv, &priv->pmap); | |
474 | if (ret) | |
475 | return ret; | |
de322e08 | 476 | |
3c223c19 MM |
477 | /* |
478 | * We can't use the P-state returned by brcm_avs_get_pmap(), since | |
479 | * that's the initial P-state from when the P-map was downloaded to the | |
480 | * AVS co-processor, not necessarily the P-state we are running at now. | |
481 | * So, we get the current P-state explicitly. | |
482 | */ | |
483 | return brcm_avs_get_pstate(priv, &priv->pmap.state); | |
de322e08 MM |
484 | } |
485 | ||
486 | static int brcm_avs_resume(struct cpufreq_policy *policy) | |
487 | { | |
488 | struct private_data *priv = policy->driver_data; | |
489 | int ret; | |
490 | ||
491 | ret = brcm_avs_set_pmap(priv, &priv->pmap); | |
492 | if (ret == -EEXIST) { | |
493 | struct platform_device *pdev = cpufreq_get_driver_data(); | |
494 | struct device *dev = &pdev->dev; | |
495 | ||
496 | dev_warn(dev, "PMAP was already set\n"); | |
497 | ret = 0; | |
498 | } | |
499 | ||
500 | return ret; | |
501 | } | |
502 | ||
503 | /* | |
504 | * All initialization code that we only want to execute once goes here. Setup | |
505 | * code that can be re-tried on every core (if it failed before) can go into | |
506 | * brcm_avs_cpufreq_init(). | |
507 | */ | |
508 | static int brcm_avs_prepare_init(struct platform_device *pdev) | |
509 | { | |
510 | struct private_data *priv; | |
511 | struct device *dev; | |
512 | int host_irq, ret; | |
513 | ||
514 | dev = &pdev->dev; | |
515 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
516 | if (!priv) | |
517 | return -ENOMEM; | |
518 | ||
519 | priv->dev = dev; | |
520 | sema_init(&priv->sem, 1); | |
521 | init_completion(&priv->done); | |
522 | platform_set_drvdata(pdev, priv); | |
523 | ||
524 | priv->base = __map_region(BRCM_AVS_CPU_DATA); | |
525 | if (!priv->base) { | |
526 | dev_err(dev, "Couldn't find property %s in device tree.\n", | |
527 | BRCM_AVS_CPU_DATA); | |
528 | return -ENOENT; | |
529 | } | |
530 | ||
531 | priv->avs_intr_base = __map_region(BRCM_AVS_CPU_INTR); | |
532 | if (!priv->avs_intr_base) { | |
533 | dev_err(dev, "Couldn't find property %s in device tree.\n", | |
534 | BRCM_AVS_CPU_INTR); | |
535 | ret = -ENOENT; | |
536 | goto unmap_base; | |
537 | } | |
538 | ||
539 | host_irq = platform_get_irq_byname(pdev, BRCM_AVS_HOST_INTR); | |
540 | if (host_irq < 0) { | |
541 | dev_err(dev, "Couldn't find interrupt %s -- %d\n", | |
542 | BRCM_AVS_HOST_INTR, host_irq); | |
543 | ret = host_irq; | |
544 | goto unmap_intr_base; | |
545 | } | |
546 | ||
547 | ret = devm_request_irq(dev, host_irq, irq_handler, IRQF_TRIGGER_RISING, | |
548 | BRCM_AVS_HOST_INTR, priv); | |
549 | if (ret) { | |
550 | dev_err(dev, "IRQ request failed: %s (%d) -- %d\n", | |
551 | BRCM_AVS_HOST_INTR, host_irq, ret); | |
552 | goto unmap_intr_base; | |
553 | } | |
554 | ||
555 | if (brcm_avs_is_firmware_loaded(priv)) | |
556 | return 0; | |
557 | ||
558 | dev_err(dev, "AVS firmware is not loaded or doesn't support DVFS\n"); | |
559 | ret = -ENODEV; | |
560 | ||
561 | unmap_intr_base: | |
562 | iounmap(priv->avs_intr_base); | |
563 | unmap_base: | |
564 | iounmap(priv->base); | |
de322e08 MM |
565 | |
566 | return ret; | |
567 | } | |
568 | ||
569 | static int brcm_avs_cpufreq_init(struct cpufreq_policy *policy) | |
570 | { | |
571 | struct cpufreq_frequency_table *freq_table; | |
572 | struct platform_device *pdev; | |
573 | struct private_data *priv; | |
574 | struct device *dev; | |
575 | int ret; | |
576 | ||
577 | pdev = cpufreq_get_driver_data(); | |
578 | priv = platform_get_drvdata(pdev); | |
579 | policy->driver_data = priv; | |
580 | dev = &pdev->dev; | |
581 | ||
582 | freq_table = brcm_avs_get_freq_table(dev, priv); | |
583 | if (IS_ERR(freq_table)) { | |
584 | ret = PTR_ERR(freq_table); | |
585 | dev_err(dev, "Couldn't determine frequency table (%d).\n", ret); | |
586 | return ret; | |
587 | } | |
588 | ||
5d8d4f92 | 589 | policy->freq_table = freq_table; |
de322e08 MM |
590 | |
591 | /* All cores share the same clock and thus the same policy. */ | |
592 | cpumask_setall(policy->cpus); | |
593 | ||
594 | ret = __issue_avs_command(priv, AVS_CMD_ENABLE, false, NULL); | |
595 | if (!ret) { | |
596 | unsigned int pstate; | |
597 | ||
598 | ret = brcm_avs_get_pstate(priv, &pstate); | |
599 | if (!ret) { | |
600 | policy->cur = freq_table[pstate].frequency; | |
601 | dev_info(dev, "registered\n"); | |
602 | return 0; | |
603 | } | |
604 | } | |
605 | ||
606 | dev_err(dev, "couldn't initialize driver (%d)\n", ret); | |
607 | ||
608 | return ret; | |
609 | } | |
610 | ||
611 | static ssize_t show_brcm_avs_pstate(struct cpufreq_policy *policy, char *buf) | |
612 | { | |
613 | struct private_data *priv = policy->driver_data; | |
614 | unsigned int pstate; | |
615 | ||
616 | if (brcm_avs_get_pstate(priv, &pstate)) | |
617 | return sprintf(buf, "<unknown>\n"); | |
618 | ||
619 | return sprintf(buf, "%u\n", pstate); | |
620 | } | |
621 | ||
622 | static ssize_t show_brcm_avs_mode(struct cpufreq_policy *policy, char *buf) | |
623 | { | |
624 | struct private_data *priv = policy->driver_data; | |
625 | struct pmap pmap; | |
626 | ||
627 | if (brcm_avs_get_pmap(priv, &pmap)) | |
628 | return sprintf(buf, "<unknown>\n"); | |
629 | ||
630 | return sprintf(buf, "%s %u\n", brcm_avs_mode_to_string(pmap.mode), | |
631 | pmap.mode); | |
632 | } | |
633 | ||
634 | static ssize_t show_brcm_avs_pmap(struct cpufreq_policy *policy, char *buf) | |
635 | { | |
636 | unsigned int mdiv_p0, mdiv_p1, mdiv_p2, mdiv_p3, mdiv_p4; | |
637 | struct private_data *priv = policy->driver_data; | |
638 | unsigned int ndiv, pdiv; | |
639 | struct pmap pmap; | |
640 | ||
641 | if (brcm_avs_get_pmap(priv, &pmap)) | |
642 | return sprintf(buf, "<unknown>\n"); | |
643 | ||
644 | brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); | |
645 | brcm_avs_parse_p2(pmap.p2, &mdiv_p1, &mdiv_p2, &mdiv_p3, &mdiv_p4); | |
646 | ||
9b02c54b | 647 | return sprintf(buf, "0x%08x 0x%08x %u %u %u %u %u %u %u %u %u\n", |
de322e08 | 648 | pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, |
9b02c54b | 649 | mdiv_p3, mdiv_p4, pmap.mode, pmap.state); |
de322e08 MM |
650 | } |
651 | ||
652 | static ssize_t show_brcm_avs_voltage(struct cpufreq_policy *policy, char *buf) | |
653 | { | |
654 | struct private_data *priv = policy->driver_data; | |
655 | ||
4c5681fc | 656 | return sprintf(buf, "0x%08x\n", brcm_avs_get_voltage(priv->base)); |
de322e08 MM |
657 | } |
658 | ||
659 | static ssize_t show_brcm_avs_frequency(struct cpufreq_policy *policy, char *buf) | |
660 | { | |
661 | struct private_data *priv = policy->driver_data; | |
662 | ||
4c5681fc | 663 | return sprintf(buf, "0x%08x\n", brcm_avs_get_frequency(priv->base)); |
de322e08 MM |
664 | } |
665 | ||
666 | cpufreq_freq_attr_ro(brcm_avs_pstate); | |
667 | cpufreq_freq_attr_ro(brcm_avs_mode); | |
668 | cpufreq_freq_attr_ro(brcm_avs_pmap); | |
669 | cpufreq_freq_attr_ro(brcm_avs_voltage); | |
670 | cpufreq_freq_attr_ro(brcm_avs_frequency); | |
671 | ||
e7d040b8 | 672 | static struct freq_attr *brcm_avs_cpufreq_attr[] = { |
de322e08 MM |
673 | &cpufreq_freq_attr_scaling_available_freqs, |
674 | &brcm_avs_pstate, | |
675 | &brcm_avs_mode, | |
676 | &brcm_avs_pmap, | |
677 | &brcm_avs_voltage, | |
678 | &brcm_avs_frequency, | |
679 | NULL | |
680 | }; | |
681 | ||
682 | static struct cpufreq_driver brcm_avs_driver = { | |
683 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, | |
684 | .verify = cpufreq_generic_frequency_table_verify, | |
685 | .target_index = brcm_avs_target_index, | |
686 | .get = brcm_avs_cpufreq_get, | |
687 | .suspend = brcm_avs_suspend, | |
688 | .resume = brcm_avs_resume, | |
689 | .init = brcm_avs_cpufreq_init, | |
690 | .attr = brcm_avs_cpufreq_attr, | |
691 | .name = BRCM_AVS_CPUFREQ_PREFIX, | |
692 | }; | |
693 | ||
694 | static int brcm_avs_cpufreq_probe(struct platform_device *pdev) | |
695 | { | |
696 | int ret; | |
697 | ||
698 | ret = brcm_avs_prepare_init(pdev); | |
699 | if (ret) | |
700 | return ret; | |
701 | ||
702 | brcm_avs_driver.driver_data = pdev; | |
703 | ||
ee53a65d | 704 | return cpufreq_register_driver(&brcm_avs_driver); |
de322e08 MM |
705 | } |
706 | ||
707 | static int brcm_avs_cpufreq_remove(struct platform_device *pdev) | |
708 | { | |
709 | struct private_data *priv; | |
710 | int ret; | |
711 | ||
712 | ret = cpufreq_unregister_driver(&brcm_avs_driver); | |
713 | if (ret) | |
714 | return ret; | |
715 | ||
716 | priv = platform_get_drvdata(pdev); | |
717 | iounmap(priv->base); | |
718 | iounmap(priv->avs_intr_base); | |
de322e08 MM |
719 | |
720 | return 0; | |
721 | } | |
722 | ||
723 | static const struct of_device_id brcm_avs_cpufreq_match[] = { | |
724 | { .compatible = BRCM_AVS_CPU_DATA }, | |
725 | { } | |
726 | }; | |
727 | MODULE_DEVICE_TABLE(of, brcm_avs_cpufreq_match); | |
728 | ||
729 | static struct platform_driver brcm_avs_cpufreq_platdrv = { | |
730 | .driver = { | |
731 | .name = BRCM_AVS_CPUFREQ_NAME, | |
732 | .of_match_table = brcm_avs_cpufreq_match, | |
733 | }, | |
734 | .probe = brcm_avs_cpufreq_probe, | |
735 | .remove = brcm_avs_cpufreq_remove, | |
736 | }; | |
737 | module_platform_driver(brcm_avs_cpufreq_platdrv); | |
738 | ||
739 | MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>"); | |
740 | MODULE_DESCRIPTION("CPUfreq driver for Broadcom STB AVS"); | |
741 | MODULE_LICENSE("GPL"); |