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ec437d71 HR |
1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* | |
3 | * amd-pstate.c - AMD Processor P-state Frequency Driver | |
4 | * | |
5 | * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. | |
6 | * | |
7 | * Author: Huang Rui <ray.huang@amd.com> | |
8 | * | |
9 | * AMD P-State introduces a new CPU performance scaling design for AMD | |
10 | * processors using the ACPI Collaborative Performance and Power Control (CPPC) | |
11 | * feature which works with the AMD SMU firmware providing a finer grained | |
12 | * frequency control range. It is to replace the legacy ACPI P-States control, | |
13 | * allows a flexible, low-latency interface for the Linux kernel to directly | |
14 | * communicate the performance hints to hardware. | |
15 | * | |
16 | * AMD P-State is supported on recent AMD Zen base CPU series include some of | |
17 | * Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD | |
18 | * P-State supported system. And there are two types of hardware implementations | |
19 | * for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution. | |
20 | * X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types. | |
21 | */ | |
22 | ||
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/smp.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/cpufreq.h> | |
31 | #include <linux/compiler.h> | |
32 | #include <linux/dmi.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/acpi.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/uaccess.h> | |
38 | #include <linux/static_call.h> | |
39 | ||
40 | #include <acpi/processor.h> | |
41 | #include <acpi/cppc_acpi.h> | |
42 | ||
43 | #include <asm/msr.h> | |
44 | #include <asm/processor.h> | |
45 | #include <asm/cpufeature.h> | |
46 | #include <asm/cpu_device_id.h> | |
60e10f89 | 47 | #include "amd-pstate-trace.h" |
ec437d71 HR |
48 | |
49 | #define AMD_PSTATE_TRANSITION_LATENCY 0x20000 | |
50 | #define AMD_PSTATE_TRANSITION_DELAY 500 | |
51 | ||
e059c184 HR |
52 | /* |
53 | * TODO: We need more time to fine tune processors with shared memory solution | |
54 | * with community together. | |
55 | * | |
56 | * There are some performance drops on the CPU benchmarks which reports from | |
57 | * Suse. We are co-working with them to fine tune the shared memory solution. So | |
58 | * we disable it by default to go acpi-cpufreq on these processors and add a | |
59 | * module parameter to be able to enable it manually for debugging. | |
60 | */ | |
61 | static bool shared_mem = false; | |
62 | module_param(shared_mem, bool, 0444); | |
63 | MODULE_PARM_DESC(shared_mem, | |
64 | "enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)"); | |
65 | ||
ec437d71 HR |
66 | static struct cpufreq_driver amd_pstate_driver; |
67 | ||
68 | /** | |
69 | * struct amd_cpudata - private CPU data for AMD P-State | |
70 | * @cpu: CPU number | |
71 | * @cppc_req_cached: cached performance request hints | |
72 | * @highest_perf: the maximum performance an individual processor may reach, | |
73 | * assuming ideal conditions | |
74 | * @nominal_perf: the maximum sustained performance level of the processor, | |
75 | * assuming ideal operating conditions | |
76 | * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power | |
77 | * savings are achieved | |
78 | * @lowest_perf: the absolute lowest performance level of the processor | |
79 | * @max_freq: the frequency that mapped to highest_perf | |
80 | * @min_freq: the frequency that mapped to lowest_perf | |
81 | * @nominal_freq: the frequency that mapped to nominal_perf | |
82 | * @lowest_nonlinear_freq: the frequency that mapped to lowest_nonlinear_perf | |
83 | * | |
84 | * The amd_cpudata is key private data for each CPU thread in AMD P-State, and | |
85 | * represents all the attributes and goals that AMD P-State requests at runtime. | |
86 | */ | |
87 | struct amd_cpudata { | |
88 | int cpu; | |
89 | ||
41271016 | 90 | struct freq_qos_request req[2]; |
ec437d71 HR |
91 | u64 cppc_req_cached; |
92 | ||
93 | u32 highest_perf; | |
94 | u32 nominal_perf; | |
95 | u32 lowest_nonlinear_perf; | |
96 | u32 lowest_perf; | |
97 | ||
98 | u32 max_freq; | |
99 | u32 min_freq; | |
100 | u32 nominal_freq; | |
101 | u32 lowest_nonlinear_freq; | |
41271016 HR |
102 | |
103 | bool boost_supported; | |
ec437d71 HR |
104 | }; |
105 | ||
e059c184 | 106 | static inline int pstate_enable(bool enable) |
ec437d71 HR |
107 | { |
108 | return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); | |
109 | } | |
110 | ||
e059c184 HR |
111 | static int cppc_enable(bool enable) |
112 | { | |
113 | int cpu, ret = 0; | |
114 | ||
115 | for_each_present_cpu(cpu) { | |
116 | ret = cppc_set_enable(cpu, enable); | |
117 | if (ret) | |
118 | return ret; | |
119 | } | |
120 | ||
121 | return ret; | |
122 | } | |
123 | ||
124 | DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); | |
125 | ||
126 | static inline int amd_pstate_enable(bool enable) | |
127 | { | |
128 | return static_call(amd_pstate_enable)(enable); | |
129 | } | |
130 | ||
131 | static int pstate_init_perf(struct amd_cpudata *cpudata) | |
ec437d71 HR |
132 | { |
133 | u64 cap1; | |
134 | ||
135 | int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, | |
136 | &cap1); | |
137 | if (ret) | |
138 | return ret; | |
139 | ||
140 | /* | |
141 | * TODO: Introduce AMD specific power feature. | |
142 | * | |
143 | * CPPC entry doesn't indicate the highest performance in some ASICs. | |
144 | */ | |
145 | WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); | |
146 | ||
147 | WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); | |
148 | WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); | |
149 | WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
e059c184 HR |
154 | static int cppc_init_perf(struct amd_cpudata *cpudata) |
155 | { | |
156 | struct cppc_perf_caps cppc_perf; | |
157 | ||
158 | int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); | |
159 | if (ret) | |
160 | return ret; | |
161 | ||
162 | WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf()); | |
163 | ||
164 | WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); | |
165 | WRITE_ONCE(cpudata->lowest_nonlinear_perf, | |
166 | cppc_perf.lowest_nonlinear_perf); | |
167 | WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf); | |
173 | ||
174 | static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) | |
175 | { | |
176 | return static_call(amd_pstate_init_perf)(cpudata); | |
177 | } | |
178 | ||
179 | static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, | |
180 | u32 des_perf, u32 max_perf, bool fast_switch) | |
ec437d71 HR |
181 | { |
182 | if (fast_switch) | |
183 | wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); | |
184 | else | |
185 | wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, | |
186 | READ_ONCE(cpudata->cppc_req_cached)); | |
187 | } | |
188 | ||
e059c184 HR |
189 | static void cppc_update_perf(struct amd_cpudata *cpudata, |
190 | u32 min_perf, u32 des_perf, | |
191 | u32 max_perf, bool fast_switch) | |
192 | { | |
193 | struct cppc_perf_ctrls perf_ctrls; | |
194 | ||
195 | perf_ctrls.max_perf = max_perf; | |
196 | perf_ctrls.min_perf = min_perf; | |
197 | perf_ctrls.desired_perf = des_perf; | |
198 | ||
199 | cppc_set_perf(cpudata->cpu, &perf_ctrls); | |
200 | } | |
201 | ||
202 | DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); | |
203 | ||
204 | static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, | |
205 | u32 min_perf, u32 des_perf, | |
206 | u32 max_perf, bool fast_switch) | |
207 | { | |
208 | static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, | |
209 | max_perf, fast_switch); | |
210 | } | |
211 | ||
ec437d71 HR |
212 | static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, |
213 | u32 des_perf, u32 max_perf, bool fast_switch) | |
214 | { | |
215 | u64 prev = READ_ONCE(cpudata->cppc_req_cached); | |
216 | u64 value = prev; | |
217 | ||
218 | value &= ~AMD_CPPC_MIN_PERF(~0L); | |
219 | value |= AMD_CPPC_MIN_PERF(min_perf); | |
220 | ||
221 | value &= ~AMD_CPPC_DES_PERF(~0L); | |
222 | value |= AMD_CPPC_DES_PERF(des_perf); | |
223 | ||
224 | value &= ~AMD_CPPC_MAX_PERF(~0L); | |
225 | value |= AMD_CPPC_MAX_PERF(max_perf); | |
226 | ||
60e10f89 HR |
227 | trace_amd_pstate_perf(min_perf, des_perf, max_perf, |
228 | cpudata->cpu, (value != prev), fast_switch); | |
229 | ||
ec437d71 HR |
230 | if (value == prev) |
231 | return; | |
232 | ||
233 | WRITE_ONCE(cpudata->cppc_req_cached, value); | |
234 | ||
235 | amd_pstate_update_perf(cpudata, min_perf, des_perf, | |
236 | max_perf, fast_switch); | |
237 | } | |
238 | ||
239 | static int amd_pstate_verify(struct cpufreq_policy_data *policy) | |
240 | { | |
241 | cpufreq_verify_within_cpu_limits(policy); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static int amd_pstate_target(struct cpufreq_policy *policy, | |
247 | unsigned int target_freq, | |
248 | unsigned int relation) | |
249 | { | |
250 | struct cpufreq_freqs freqs; | |
251 | struct amd_cpudata *cpudata = policy->driver_data; | |
252 | unsigned long max_perf, min_perf, des_perf, cap_perf; | |
253 | ||
254 | if (!cpudata->max_freq) | |
255 | return -ENODEV; | |
256 | ||
257 | cap_perf = READ_ONCE(cpudata->highest_perf); | |
258 | min_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); | |
259 | max_perf = cap_perf; | |
260 | ||
261 | freqs.old = policy->cur; | |
262 | freqs.new = target_freq; | |
263 | ||
264 | des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf, | |
265 | cpudata->max_freq); | |
266 | ||
267 | cpufreq_freq_transition_begin(policy, &freqs); | |
268 | amd_pstate_update(cpudata, min_perf, des_perf, | |
269 | max_perf, false); | |
270 | cpufreq_freq_transition_end(policy, &freqs, false); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
1d215f03 HR |
275 | static void amd_pstate_adjust_perf(unsigned int cpu, |
276 | unsigned long _min_perf, | |
277 | unsigned long target_perf, | |
278 | unsigned long capacity) | |
279 | { | |
280 | unsigned long max_perf, min_perf, des_perf, | |
281 | cap_perf, lowest_nonlinear_perf; | |
282 | struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); | |
283 | struct amd_cpudata *cpudata = policy->driver_data; | |
284 | ||
285 | cap_perf = READ_ONCE(cpudata->highest_perf); | |
286 | lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); | |
287 | ||
288 | des_perf = cap_perf; | |
289 | if (target_perf < capacity) | |
290 | des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); | |
291 | ||
292 | min_perf = READ_ONCE(cpudata->highest_perf); | |
293 | if (_min_perf < capacity) | |
294 | min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); | |
295 | ||
296 | if (min_perf < lowest_nonlinear_perf) | |
297 | min_perf = lowest_nonlinear_perf; | |
298 | ||
299 | max_perf = cap_perf; | |
300 | if (max_perf < min_perf) | |
301 | max_perf = min_perf; | |
302 | ||
303 | des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); | |
304 | ||
305 | amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); | |
306 | } | |
307 | ||
ec437d71 HR |
308 | static int amd_get_min_freq(struct amd_cpudata *cpudata) |
309 | { | |
310 | struct cppc_perf_caps cppc_perf; | |
311 | ||
312 | int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); | |
313 | if (ret) | |
314 | return ret; | |
315 | ||
316 | /* Switch to khz */ | |
317 | return cppc_perf.lowest_freq * 1000; | |
318 | } | |
319 | ||
320 | static int amd_get_max_freq(struct amd_cpudata *cpudata) | |
321 | { | |
322 | struct cppc_perf_caps cppc_perf; | |
323 | u32 max_perf, max_freq, nominal_freq, nominal_perf; | |
324 | u64 boost_ratio; | |
325 | ||
326 | int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); | |
327 | if (ret) | |
328 | return ret; | |
329 | ||
330 | nominal_freq = cppc_perf.nominal_freq; | |
331 | nominal_perf = READ_ONCE(cpudata->nominal_perf); | |
332 | max_perf = READ_ONCE(cpudata->highest_perf); | |
333 | ||
334 | boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, | |
335 | nominal_perf); | |
336 | ||
337 | max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT; | |
338 | ||
339 | /* Switch to khz */ | |
340 | return max_freq * 1000; | |
341 | } | |
342 | ||
343 | static int amd_get_nominal_freq(struct amd_cpudata *cpudata) | |
344 | { | |
345 | struct cppc_perf_caps cppc_perf; | |
346 | ||
347 | int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | /* Switch to khz */ | |
352 | return cppc_perf.nominal_freq * 1000; | |
353 | } | |
354 | ||
355 | static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) | |
356 | { | |
357 | struct cppc_perf_caps cppc_perf; | |
358 | u32 lowest_nonlinear_freq, lowest_nonlinear_perf, | |
359 | nominal_freq, nominal_perf; | |
360 | u64 lowest_nonlinear_ratio; | |
361 | ||
362 | int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); | |
363 | if (ret) | |
364 | return ret; | |
365 | ||
366 | nominal_freq = cppc_perf.nominal_freq; | |
367 | nominal_perf = READ_ONCE(cpudata->nominal_perf); | |
368 | ||
369 | lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; | |
370 | ||
371 | lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT, | |
372 | nominal_perf); | |
373 | ||
374 | lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT; | |
375 | ||
376 | /* Switch to khz */ | |
377 | return lowest_nonlinear_freq * 1000; | |
378 | } | |
379 | ||
41271016 HR |
380 | static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) |
381 | { | |
382 | struct amd_cpudata *cpudata = policy->driver_data; | |
383 | int ret; | |
384 | ||
385 | if (!cpudata->boost_supported) { | |
386 | pr_err("Boost mode is not supported by this processor or SBIOS\n"); | |
387 | return -EINVAL; | |
388 | } | |
389 | ||
390 | if (state) | |
391 | policy->cpuinfo.max_freq = cpudata->max_freq; | |
392 | else | |
393 | policy->cpuinfo.max_freq = cpudata->nominal_freq; | |
394 | ||
395 | policy->max = policy->cpuinfo.max_freq; | |
396 | ||
397 | ret = freq_qos_update_request(&cpudata->req[1], | |
398 | policy->cpuinfo.max_freq); | |
399 | if (ret < 0) | |
400 | return ret; | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | static void amd_pstate_boost_init(struct amd_cpudata *cpudata) | |
406 | { | |
407 | u32 highest_perf, nominal_perf; | |
408 | ||
409 | highest_perf = READ_ONCE(cpudata->highest_perf); | |
410 | nominal_perf = READ_ONCE(cpudata->nominal_perf); | |
411 | ||
412 | if (highest_perf <= nominal_perf) | |
413 | return; | |
414 | ||
415 | cpudata->boost_supported = true; | |
416 | amd_pstate_driver.boost_enabled = true; | |
417 | } | |
418 | ||
ec437d71 HR |
419 | static int amd_pstate_cpu_init(struct cpufreq_policy *policy) |
420 | { | |
421 | int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; | |
422 | struct device *dev; | |
423 | struct amd_cpudata *cpudata; | |
424 | ||
425 | dev = get_cpu_device(policy->cpu); | |
426 | if (!dev) | |
427 | return -ENODEV; | |
428 | ||
429 | cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); | |
430 | if (!cpudata) | |
431 | return -ENOMEM; | |
432 | ||
433 | cpudata->cpu = policy->cpu; | |
434 | ||
435 | ret = amd_pstate_init_perf(cpudata); | |
436 | if (ret) | |
41271016 | 437 | goto free_cpudata1; |
ec437d71 HR |
438 | |
439 | min_freq = amd_get_min_freq(cpudata); | |
440 | max_freq = amd_get_max_freq(cpudata); | |
441 | nominal_freq = amd_get_nominal_freq(cpudata); | |
442 | lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); | |
443 | ||
444 | if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { | |
445 | dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", | |
446 | min_freq, max_freq); | |
447 | ret = -EINVAL; | |
41271016 | 448 | goto free_cpudata1; |
ec437d71 HR |
449 | } |
450 | ||
451 | policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; | |
452 | policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; | |
453 | ||
454 | policy->min = min_freq; | |
455 | policy->max = max_freq; | |
456 | ||
457 | policy->cpuinfo.min_freq = min_freq; | |
458 | policy->cpuinfo.max_freq = max_freq; | |
459 | ||
460 | /* It will be updated by governor */ | |
461 | policy->cur = policy->cpuinfo.min_freq; | |
462 | ||
e059c184 HR |
463 | if (boot_cpu_has(X86_FEATURE_CPPC)) |
464 | policy->fast_switch_possible = true; | |
1d215f03 | 465 | |
41271016 HR |
466 | ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], |
467 | FREQ_QOS_MIN, policy->cpuinfo.min_freq); | |
468 | if (ret < 0) { | |
469 | dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); | |
470 | goto free_cpudata1; | |
471 | } | |
472 | ||
473 | ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1], | |
474 | FREQ_QOS_MAX, policy->cpuinfo.max_freq); | |
475 | if (ret < 0) { | |
476 | dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); | |
477 | goto free_cpudata2; | |
478 | } | |
479 | ||
ec437d71 HR |
480 | /* Initial processor data capability frequencies */ |
481 | cpudata->max_freq = max_freq; | |
482 | cpudata->min_freq = min_freq; | |
483 | cpudata->nominal_freq = nominal_freq; | |
484 | cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; | |
485 | ||
486 | policy->driver_data = cpudata; | |
487 | ||
41271016 HR |
488 | amd_pstate_boost_init(cpudata); |
489 | ||
ec437d71 HR |
490 | return 0; |
491 | ||
41271016 HR |
492 | free_cpudata2: |
493 | freq_qos_remove_request(&cpudata->req[0]); | |
494 | free_cpudata1: | |
ec437d71 HR |
495 | kfree(cpudata); |
496 | return ret; | |
497 | } | |
498 | ||
499 | static int amd_pstate_cpu_exit(struct cpufreq_policy *policy) | |
500 | { | |
501 | struct amd_cpudata *cpudata; | |
502 | ||
503 | cpudata = policy->driver_data; | |
504 | ||
41271016 HR |
505 | freq_qos_remove_request(&cpudata->req[1]); |
506 | freq_qos_remove_request(&cpudata->req[0]); | |
ec437d71 HR |
507 | kfree(cpudata); |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
ec4e3326 HR |
512 | /* Sysfs attributes */ |
513 | ||
514 | /* | |
515 | * This frequency is to indicate the maximum hardware frequency. | |
516 | * If boost is not active but supported, the frequency will be larger than the | |
517 | * one in cpuinfo. | |
518 | */ | |
519 | static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, | |
520 | char *buf) | |
521 | { | |
522 | int max_freq; | |
523 | struct amd_cpudata *cpudata; | |
524 | ||
525 | cpudata = policy->driver_data; | |
526 | ||
527 | max_freq = amd_get_max_freq(cpudata); | |
528 | if (max_freq < 0) | |
529 | return max_freq; | |
530 | ||
531 | return sprintf(&buf[0], "%u\n", max_freq); | |
532 | } | |
533 | ||
534 | static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, | |
535 | char *buf) | |
536 | { | |
537 | int freq; | |
538 | struct amd_cpudata *cpudata; | |
539 | ||
540 | cpudata = policy->driver_data; | |
541 | ||
542 | freq = amd_get_lowest_nonlinear_freq(cpudata); | |
543 | if (freq < 0) | |
544 | return freq; | |
545 | ||
546 | return sprintf(&buf[0], "%u\n", freq); | |
547 | } | |
548 | ||
3ad7fde1 HR |
549 | /* |
550 | * In some of ASICs, the highest_perf is not the one in the _CPC table, so we | |
551 | * need to expose it to sysfs. | |
552 | */ | |
553 | static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, | |
554 | char *buf) | |
555 | { | |
556 | u32 perf; | |
557 | struct amd_cpudata *cpudata = policy->driver_data; | |
558 | ||
559 | perf = READ_ONCE(cpudata->highest_perf); | |
560 | ||
561 | return sprintf(&buf[0], "%u\n", perf); | |
562 | } | |
563 | ||
ec4e3326 HR |
564 | cpufreq_freq_attr_ro(amd_pstate_max_freq); |
565 | cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); | |
566 | ||
3ad7fde1 HR |
567 | cpufreq_freq_attr_ro(amd_pstate_highest_perf); |
568 | ||
ec4e3326 HR |
569 | static struct freq_attr *amd_pstate_attr[] = { |
570 | &amd_pstate_max_freq, | |
571 | &amd_pstate_lowest_nonlinear_freq, | |
3ad7fde1 | 572 | &amd_pstate_highest_perf, |
ec4e3326 HR |
573 | NULL, |
574 | }; | |
575 | ||
ec437d71 HR |
576 | static struct cpufreq_driver amd_pstate_driver = { |
577 | .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, | |
578 | .verify = amd_pstate_verify, | |
579 | .target = amd_pstate_target, | |
580 | .init = amd_pstate_cpu_init, | |
581 | .exit = amd_pstate_cpu_exit, | |
41271016 | 582 | .set_boost = amd_pstate_set_boost, |
ec437d71 | 583 | .name = "amd-pstate", |
ec4e3326 | 584 | .attr = amd_pstate_attr, |
ec437d71 HR |
585 | }; |
586 | ||
587 | static int __init amd_pstate_init(void) | |
588 | { | |
589 | int ret; | |
590 | ||
591 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
592 | return -ENODEV; | |
593 | ||
594 | if (!acpi_cpc_valid()) { | |
595 | pr_debug("the _CPC object is not present in SBIOS\n"); | |
596 | return -ENODEV; | |
597 | } | |
598 | ||
599 | /* don't keep reloading if cpufreq_driver exists */ | |
600 | if (cpufreq_get_current_driver()) | |
601 | return -EEXIST; | |
602 | ||
603 | /* capability check */ | |
e059c184 HR |
604 | if (boot_cpu_has(X86_FEATURE_CPPC)) { |
605 | pr_debug("AMD CPPC MSR based functionality is supported\n"); | |
606 | amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; | |
607 | } else if (shared_mem) { | |
608 | static_call_update(amd_pstate_enable, cppc_enable); | |
609 | static_call_update(amd_pstate_init_perf, cppc_init_perf); | |
610 | static_call_update(amd_pstate_update_perf, cppc_update_perf); | |
611 | } else { | |
612 | pr_info("This processor supports shared memory solution, you can enable it with amd_pstate.shared_mem=1\n"); | |
ec437d71 HR |
613 | return -ENODEV; |
614 | } | |
615 | ||
616 | /* enable amd pstate feature */ | |
617 | ret = amd_pstate_enable(true); | |
618 | if (ret) { | |
619 | pr_err("failed to enable amd-pstate with return %d\n", ret); | |
620 | return ret; | |
621 | } | |
622 | ||
623 | ret = cpufreq_register_driver(&amd_pstate_driver); | |
624 | if (ret) | |
625 | pr_err("failed to register amd_pstate_driver with return %d\n", | |
626 | ret); | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
631 | static void __exit amd_pstate_exit(void) | |
632 | { | |
633 | cpufreq_unregister_driver(&amd_pstate_driver); | |
634 | ||
635 | amd_pstate_enable(false); | |
636 | } | |
637 | ||
638 | module_init(amd_pstate_init); | |
639 | module_exit(amd_pstate_exit); | |
640 | ||
641 | MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); | |
642 | MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); | |
643 | MODULE_LICENSE("GPL"); |