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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
3a58df35 | 3 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
6 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
7 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 8 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
9 | */ |
10 | ||
1c5864e2 JP |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
1da177e4 LT |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
fe27cb35 VP |
16 | #include <linux/smp.h> |
17 | #include <linux/sched.h> | |
1da177e4 | 18 | #include <linux/cpufreq.h> |
d395bf12 | 19 | #include <linux/compiler.h> |
8adcc0c6 | 20 | #include <linux/dmi.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include <linux/acpi.h> | |
3a58df35 DJ |
24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/uaccess.h> | |
27 | ||
1da177e4 LT |
28 | #include <acpi/processor.h> |
29 | ||
dde9f7ba | 30 | #include <asm/msr.h> |
fe27cb35 VP |
31 | #include <asm/processor.h> |
32 | #include <asm/cpufeature.h> | |
ba5bade4 | 33 | #include <asm/cpu_device_id.h> |
fe27cb35 | 34 | |
1da177e4 LT |
35 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
36 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
37 | MODULE_LICENSE("GPL"); | |
38 | ||
dde9f7ba VP |
39 | enum { |
40 | UNDEFINED_CAPABLE = 0, | |
41 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 42 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
43 | SYSTEM_IO_CAPABLE, |
44 | }; | |
45 | ||
46 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 47 | #define AMD_MSR_RANGE (0x7) |
cc9690cf | 48 | #define HYGON_MSR_RANGE (0x7) |
dde9f7ba | 49 | |
615b7300 AP |
50 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
51 | ||
fe27cb35 | 52 | struct acpi_cpufreq_data { |
64be7eed VP |
53 | unsigned int resume; |
54 | unsigned int cpu_feature; | |
8cfcfd39 | 55 | unsigned int acpi_perf_cpu; |
f4fd3797 | 56 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
57 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
58 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
59 | }; |
60 | ||
50109292 | 61 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 62 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 63 | |
3427616b RW |
64 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
65 | { | |
66 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
67 | } | |
68 | ||
1da177e4 LT |
69 | static struct cpufreq_driver acpi_cpufreq_driver; |
70 | ||
d395bf12 | 71 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
72 | |
73 | static bool boost_state(unsigned int cpu) | |
74 | { | |
75 | u32 lo, hi; | |
76 | u64 msr; | |
77 | ||
78 | switch (boot_cpu_data.x86_vendor) { | |
79 | case X86_VENDOR_INTEL: | |
80 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
81 | msr = lo | ((u64)hi << 32); | |
82 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
cc9690cf | 83 | case X86_VENDOR_HYGON: |
615b7300 AP |
84 | case X86_VENDOR_AMD: |
85 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
86 | msr = lo | ((u64)hi << 32); | |
87 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
88 | } | |
89 | return false; | |
90 | } | |
91 | ||
a3605c46 | 92 | static int boost_set_msr(bool enable) |
615b7300 | 93 | { |
615b7300 | 94 | u32 msr_addr; |
a3605c46 | 95 | u64 msr_mask, val; |
615b7300 AP |
96 | |
97 | switch (boot_cpu_data.x86_vendor) { | |
98 | case X86_VENDOR_INTEL: | |
99 | msr_addr = MSR_IA32_MISC_ENABLE; | |
100 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
101 | break; | |
cc9690cf | 102 | case X86_VENDOR_HYGON: |
615b7300 AP |
103 | case X86_VENDOR_AMD: |
104 | msr_addr = MSR_K7_HWCR; | |
105 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
106 | break; | |
107 | default: | |
a3605c46 | 108 | return -EINVAL; |
615b7300 AP |
109 | } |
110 | ||
a3605c46 | 111 | rdmsrl(msr_addr, val); |
615b7300 | 112 | |
a3605c46 SAS |
113 | if (enable) |
114 | val &= ~msr_mask; | |
115 | else | |
116 | val |= msr_mask; | |
615b7300 | 117 | |
a3605c46 SAS |
118 | wrmsrl(msr_addr, val); |
119 | return 0; | |
120 | } | |
121 | ||
122 | static void boost_set_msr_each(void *p_en) | |
123 | { | |
124 | bool enable = (bool) p_en; | |
125 | ||
126 | boost_set_msr(enable); | |
615b7300 AP |
127 | } |
128 | ||
cf6fada7 | 129 | static int set_boost(struct cpufreq_policy *policy, int val) |
615b7300 | 130 | { |
cf6fada7 XW |
131 | on_each_cpu_mask(policy->cpus, boost_set_msr_each, |
132 | (void *)(long)val, 1); | |
133 | pr_debug("CPU %*pbl: Core Boosting %sabled.\n", | |
134 | cpumask_pr_args(policy->cpus), val ? "en" : "dis"); | |
615b7300 | 135 | |
cfc9c8ed | 136 | return 0; |
615b7300 AP |
137 | } |
138 | ||
f4fd3797 LT |
139 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
140 | { | |
eb0b3e78 | 141 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 142 | |
e2530367 SP |
143 | if (unlikely(!data)) |
144 | return -ENODEV; | |
145 | ||
f4fd3797 LT |
146 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
147 | } | |
148 | ||
149 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
150 | ||
11269ff5 | 151 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
152 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
153 | size_t count) | |
cfc9c8ed LM |
154 | { |
155 | int ret; | |
17135782 | 156 | unsigned int val = 0; |
cfc9c8ed | 157 | |
7a6c79f2 | 158 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
159 | return -EINVAL; |
160 | ||
17135782 RW |
161 | ret = kstrtouint(buf, 10, &val); |
162 | if (ret || val > 1) | |
cfc9c8ed LM |
163 | return -EINVAL; |
164 | ||
cf6fada7 XW |
165 | get_online_cpus(); |
166 | set_boost(policy, val); | |
167 | put_online_cpus(); | |
cfc9c8ed LM |
168 | |
169 | return count; | |
170 | } | |
171 | ||
11269ff5 AP |
172 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
173 | { | |
cfc9c8ed | 174 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
175 | } |
176 | ||
59027d35 | 177 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
178 | #endif |
179 | ||
dde9f7ba VP |
180 | static int check_est_cpu(unsigned int cpuid) |
181 | { | |
92cb7612 | 182 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 183 | |
0de51088 | 184 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
185 | } |
186 | ||
3dc9a633 MG |
187 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
188 | { | |
189 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
190 | ||
191 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
192 | } | |
193 | ||
8cee1eed | 194 | static unsigned extract_io(struct cpufreq_policy *policy, u32 value) |
fe27cb35 | 195 | { |
8cee1eed | 196 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
197 | struct acpi_processor_performance *perf; |
198 | int i; | |
fe27cb35 | 199 | |
3427616b | 200 | perf = to_perf_data(data); |
fe27cb35 | 201 | |
3a58df35 | 202 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 | 203 | if (value == perf->states[i].status) |
8cee1eed | 204 | return policy->freq_table[i].frequency; |
fe27cb35 VP |
205 | } |
206 | return 0; | |
207 | } | |
208 | ||
8cee1eed | 209 | static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr) |
dde9f7ba | 210 | { |
8cee1eed | 211 | struct acpi_cpufreq_data *data = policy->driver_data; |
041526f9 | 212 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 213 | struct acpi_processor_performance *perf; |
dde9f7ba | 214 | |
3dc9a633 MG |
215 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
216 | msr &= AMD_MSR_RANGE; | |
cc9690cf PW |
217 | else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) |
218 | msr &= HYGON_MSR_RANGE; | |
3dc9a633 MG |
219 | else |
220 | msr &= INTEL_MSR_RANGE; | |
221 | ||
3427616b | 222 | perf = to_perf_data(data); |
a6f6e6e6 | 223 | |
8cee1eed | 224 | cpufreq_for_each_entry(pos, policy->freq_table) |
041526f9 SK |
225 | if (msr == perf->states[pos->driver_data].status) |
226 | return pos->frequency; | |
8cee1eed | 227 | return policy->freq_table[0].frequency; |
dde9f7ba VP |
228 | } |
229 | ||
8cee1eed | 230 | static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) |
dde9f7ba | 231 | { |
8cee1eed VK |
232 | struct acpi_cpufreq_data *data = policy->driver_data; |
233 | ||
dde9f7ba | 234 | switch (data->cpu_feature) { |
64be7eed | 235 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 236 | case SYSTEM_AMD_MSR_CAPABLE: |
8cee1eed | 237 | return extract_msr(policy, val); |
64be7eed | 238 | case SYSTEM_IO_CAPABLE: |
8cee1eed | 239 | return extract_io(policy, val); |
64be7eed | 240 | default: |
dde9f7ba VP |
241 | return 0; |
242 | } | |
243 | } | |
244 | ||
ac13b996 | 245 | static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
ed757a2c RW |
246 | { |
247 | u32 val, dummy; | |
dde9f7ba | 248 | |
ed757a2c RW |
249 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
250 | return val; | |
251 | } | |
252 | ||
ac13b996 | 253 | static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
254 | { |
255 | u32 lo, hi; | |
256 | ||
257 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
258 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
259 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
260 | } | |
261 | ||
ac13b996 | 262 | static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) |
ed757a2c RW |
263 | { |
264 | u32 val, dummy; | |
265 | ||
266 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
267 | return val; | |
268 | } | |
269 | ||
ac13b996 | 270 | static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
271 | { |
272 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
273 | } | |
274 | ||
ac13b996 | 275 | static u32 cpu_freq_read_io(struct acpi_pct_register *reg) |
ed757a2c RW |
276 | { |
277 | u32 val; | |
278 | ||
279 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
280 | return val; | |
281 | } | |
282 | ||
ac13b996 | 283 | static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) |
ed757a2c RW |
284 | { |
285 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
286 | } | |
fe27cb35 VP |
287 | |
288 | struct drv_cmd { | |
ed757a2c | 289 | struct acpi_pct_register *reg; |
fe27cb35 | 290 | u32 val; |
ed757a2c RW |
291 | union { |
292 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
293 | u32 (*read)(struct acpi_pct_register *reg); | |
294 | } func; | |
fe27cb35 VP |
295 | }; |
296 | ||
01599fca AM |
297 | /* Called via smp_call_function_single(), on the target CPU */ |
298 | static void do_drv_read(void *_cmd) | |
1da177e4 | 299 | { |
72859081 | 300 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 301 | |
ed757a2c | 302 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 303 | } |
1da177e4 | 304 | |
ed757a2c | 305 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 306 | { |
ed757a2c RW |
307 | struct acpi_processor_performance *perf = to_perf_data(data); |
308 | struct drv_cmd cmd = { | |
309 | .reg = &perf->control_register, | |
310 | .func.read = data->cpu_freq_read, | |
311 | }; | |
312 | int err; | |
dde9f7ba | 313 | |
ed757a2c RW |
314 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
315 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
316 | return cmd.val; | |
fe27cb35 | 317 | } |
1da177e4 | 318 | |
ed757a2c RW |
319 | /* Called via smp_call_function_many(), on the target CPUs */ |
320 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 321 | { |
ed757a2c | 322 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 323 | |
ed757a2c | 324 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
325 | } |
326 | ||
ed757a2c RW |
327 | static void drv_write(struct acpi_cpufreq_data *data, |
328 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 329 | { |
ed757a2c RW |
330 | struct acpi_processor_performance *perf = to_perf_data(data); |
331 | struct drv_cmd cmd = { | |
332 | .reg = &perf->control_register, | |
333 | .val = val, | |
334 | .func.write = data->cpu_freq_write, | |
335 | }; | |
ea34f43a LT |
336 | int this_cpu; |
337 | ||
338 | this_cpu = get_cpu(); | |
ed757a2c RW |
339 | if (cpumask_test_cpu(this_cpu, mask)) |
340 | do_drv_write(&cmd); | |
341 | ||
342 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 343 | put_cpu(); |
fe27cb35 | 344 | } |
1da177e4 | 345 | |
ed757a2c | 346 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 347 | { |
ed757a2c | 348 | u32 val; |
1da177e4 | 349 | |
4d8bb537 | 350 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 351 | return 0; |
1da177e4 | 352 | |
ed757a2c | 353 | val = drv_read(data, mask); |
1da177e4 | 354 | |
eae2ef0e | 355 | pr_debug("%s = %u\n", __func__, val); |
fe27cb35 | 356 | |
ed757a2c | 357 | return val; |
fe27cb35 | 358 | } |
1da177e4 | 359 | |
fe27cb35 VP |
360 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
361 | { | |
eb0b3e78 PX |
362 | struct acpi_cpufreq_data *data; |
363 | struct cpufreq_policy *policy; | |
64be7eed | 364 | unsigned int freq; |
e56a727b | 365 | unsigned int cached_freq; |
fe27cb35 | 366 | |
eae2ef0e | 367 | pr_debug("%s (%d)\n", __func__, cpu); |
fe27cb35 | 368 | |
1f0bd44e | 369 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
370 | if (unlikely(!policy)) |
371 | return 0; | |
372 | ||
373 | data = policy->driver_data; | |
8cee1eed | 374 | if (unlikely(!data || !policy->freq_table)) |
fe27cb35 | 375 | return 0; |
1da177e4 | 376 | |
8cee1eed VK |
377 | cached_freq = policy->freq_table[to_perf_data(data)->state].frequency; |
378 | freq = extract_freq(policy, get_cur_val(cpumask_of(cpu), data)); | |
e56a727b VP |
379 | if (freq != cached_freq) { |
380 | /* | |
381 | * The dreaded BIOS frequency change behind our back. | |
382 | * Force set the frequency on next target call. | |
383 | */ | |
384 | data->resume = 1; | |
385 | } | |
386 | ||
2d06d8c4 | 387 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 388 | |
fe27cb35 | 389 | return freq; |
1da177e4 LT |
390 | } |
391 | ||
8cee1eed VK |
392 | static unsigned int check_freqs(struct cpufreq_policy *policy, |
393 | const struct cpumask *mask, unsigned int freq) | |
fe27cb35 | 394 | { |
8cee1eed | 395 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
396 | unsigned int cur_freq; |
397 | unsigned int i; | |
1da177e4 | 398 | |
3a58df35 | 399 | for (i = 0; i < 100; i++) { |
8cee1eed | 400 | cur_freq = extract_freq(policy, get_cur_val(mask, data)); |
fe27cb35 VP |
401 | if (cur_freq == freq) |
402 | return 1; | |
403 | udelay(10); | |
404 | } | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 409 | unsigned int index) |
1da177e4 | 410 | { |
eb0b3e78 | 411 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 412 | struct acpi_processor_performance *perf; |
ed757a2c | 413 | const struct cpumask *mask; |
8edc59d9 | 414 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 415 | int result = 0; |
fe27cb35 | 416 | |
8cee1eed | 417 | if (unlikely(!data)) { |
fe27cb35 VP |
418 | return -ENODEV; |
419 | } | |
1da177e4 | 420 | |
3427616b | 421 | perf = to_perf_data(data); |
8cee1eed | 422 | next_perf_state = policy->freq_table[index].driver_data; |
7650b281 | 423 | if (perf->state == next_perf_state) { |
fe27cb35 | 424 | if (unlikely(data->resume)) { |
2d06d8c4 | 425 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 426 | next_perf_state); |
fe27cb35 VP |
427 | data->resume = 0; |
428 | } else { | |
2d06d8c4 | 429 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 430 | next_perf_state); |
9a909a14 | 431 | return 0; |
fe27cb35 | 432 | } |
09b4d1ee VP |
433 | } |
434 | ||
ed757a2c RW |
435 | /* |
436 | * The core won't allow CPUs to go away until the governor has been | |
437 | * stopped, so we can rely on the stability of policy->cpus. | |
438 | */ | |
439 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
440 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 441 | |
ed757a2c | 442 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 443 | |
fe27cb35 | 444 | if (acpi_pstate_strict) { |
8cee1eed VK |
445 | if (!check_freqs(policy, mask, |
446 | policy->freq_table[index].frequency)) { | |
eae2ef0e | 447 | pr_debug("%s (%d)\n", __func__, policy->cpu); |
4d8bb537 | 448 | result = -EAGAIN; |
09b4d1ee VP |
449 | } |
450 | } | |
451 | ||
e15d8309 VK |
452 | if (!result) |
453 | perf->state = next_perf_state; | |
fe27cb35 VP |
454 | |
455 | return result; | |
1da177e4 LT |
456 | } |
457 | ||
08e9cc40 CIK |
458 | static unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy, |
459 | unsigned int target_freq) | |
b7898fda RW |
460 | { |
461 | struct acpi_cpufreq_data *data = policy->driver_data; | |
462 | struct acpi_processor_performance *perf; | |
463 | struct cpufreq_frequency_table *entry; | |
82577360 | 464 | unsigned int next_perf_state, next_freq, index; |
b7898fda RW |
465 | |
466 | /* | |
467 | * Find the closest frequency above target_freq. | |
b7898fda | 468 | */ |
5b6667c7 SM |
469 | if (policy->cached_target_freq == target_freq) |
470 | index = policy->cached_resolved_idx; | |
471 | else | |
472 | index = cpufreq_table_find_index_dl(policy, target_freq); | |
82577360 VK |
473 | |
474 | entry = &policy->freq_table[index]; | |
b7898fda RW |
475 | next_freq = entry->frequency; |
476 | next_perf_state = entry->driver_data; | |
477 | ||
478 | perf = to_perf_data(data); | |
479 | if (perf->state == next_perf_state) { | |
480 | if (unlikely(data->resume)) | |
481 | data->resume = 0; | |
482 | else | |
483 | return next_freq; | |
484 | } | |
485 | ||
486 | data->cpu_freq_write(&perf->control_register, | |
487 | perf->states[next_perf_state].control); | |
488 | perf->state = next_perf_state; | |
489 | return next_freq; | |
490 | } | |
491 | ||
1da177e4 | 492 | static unsigned long |
64be7eed | 493 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 494 | { |
3427616b | 495 | struct acpi_processor_performance *perf; |
09b4d1ee | 496 | |
3427616b | 497 | perf = to_perf_data(data); |
1da177e4 LT |
498 | if (cpu_khz) { |
499 | /* search the closest match to cpu_khz */ | |
500 | unsigned int i; | |
501 | unsigned long freq; | |
09b4d1ee | 502 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 503 | |
3a58df35 | 504 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 505 | freq = freqn; |
95dd7227 | 506 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 507 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 508 | perf->state = i; |
64be7eed | 509 | return freq; |
1da177e4 LT |
510 | } |
511 | } | |
95dd7227 | 512 | perf->state = perf->state_count-1; |
64be7eed | 513 | return freqn; |
09b4d1ee | 514 | } else { |
1da177e4 | 515 | /* assume CPU is at P0... */ |
09b4d1ee VP |
516 | perf->state = 0; |
517 | return perf->states[0].core_frequency * 1000; | |
518 | } | |
1da177e4 LT |
519 | } |
520 | ||
2fdf66b4 RR |
521 | static void free_acpi_perf_data(void) |
522 | { | |
523 | unsigned int i; | |
524 | ||
525 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
526 | for_each_possible_cpu(i) | |
527 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
528 | ->shared_cpu_map); | |
529 | free_percpu(acpi_perf_data); | |
530 | } | |
531 | ||
4d66ddf2 | 532 | static int cpufreq_boost_online(unsigned int cpu) |
615b7300 | 533 | { |
615b7300 | 534 | /* |
4d66ddf2 SAS |
535 | * On the CPU_UP path we simply keep the boost-disable flag |
536 | * in sync with the current global state. | |
615b7300 | 537 | */ |
a3605c46 | 538 | return boost_set_msr(acpi_cpufreq_driver.boost_enabled); |
4d66ddf2 | 539 | } |
615b7300 | 540 | |
4d66ddf2 SAS |
541 | static int cpufreq_boost_down_prep(unsigned int cpu) |
542 | { | |
4d66ddf2 SAS |
543 | /* |
544 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
545 | * this cpu cannot block the remaining ones from boosting. | |
546 | */ | |
a3605c46 | 547 | return boost_set_msr(1); |
615b7300 AP |
548 | } |
549 | ||
09b4d1ee VP |
550 | /* |
551 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
552 | * | |
553 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
554 | * in order to determine correct frequency and voltage pairings. We can | |
555 | * do _PDC and _PSD and find out the processor dependency for the | |
556 | * actual init that will happen later... | |
557 | */ | |
50109292 | 558 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 559 | { |
2fdf66b4 | 560 | unsigned int i; |
eae2ef0e | 561 | pr_debug("%s\n", __func__); |
09b4d1ee | 562 | |
50109292 FY |
563 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
564 | if (!acpi_perf_data) { | |
2d06d8c4 | 565 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 566 | return -ENOMEM; |
09b4d1ee | 567 | } |
2fdf66b4 | 568 | for_each_possible_cpu(i) { |
eaa95840 | 569 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
570 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
571 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
572 | |
573 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
574 | free_acpi_perf_data(); | |
575 | return -ENOMEM; | |
576 | } | |
577 | } | |
09b4d1ee VP |
578 | |
579 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
580 | acpi_processor_preregister_performance(acpi_perf_data); |
581 | return 0; | |
09b4d1ee VP |
582 | } |
583 | ||
95625b8f | 584 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
585 | /* |
586 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
587 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
588 | * detected, this has a side effect of making CPU run at a different speed | |
589 | * than OS intended it to run at. Detect it and handle it cleanly. | |
590 | */ | |
591 | static int bios_with_sw_any_bug; | |
592 | ||
1855256c | 593 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
594 | { |
595 | bios_with_sw_any_bug = 1; | |
596 | return 0; | |
597 | } | |
598 | ||
1855256c | 599 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
600 | { |
601 | .callback = sw_any_bug_found, | |
602 | .ident = "Supermicro Server X6DLP", | |
603 | .matches = { | |
604 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
605 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
606 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
607 | }, | |
608 | }, | |
609 | { } | |
610 | }; | |
1a8e42fa PB |
611 | |
612 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
613 | { | |
293afe44 JV |
614 | /* Intel Xeon Processor 7100 Series Specification Update |
615 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
616 | * AL30: A Machine Check Exception (MCE) Occurring during an |
617 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 618 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
619 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
620 | if ((c->x86 == 15) && | |
621 | (c->x86_model == 6) && | |
b399151c | 622 | (c->x86_stepping == 8)) { |
1c5864e2 | 623 | pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n"); |
1a8e42fa | 624 | return -ENODEV; |
293afe44 | 625 | } |
1a8e42fa PB |
626 | } |
627 | return 0; | |
628 | } | |
95625b8f | 629 | #endif |
8adcc0c6 | 630 | |
64be7eed | 631 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 632 | { |
64be7eed VP |
633 | unsigned int i; |
634 | unsigned int valid_states = 0; | |
635 | unsigned int cpu = policy->cpu; | |
636 | struct acpi_cpufreq_data *data; | |
64be7eed | 637 | unsigned int result = 0; |
92cb7612 | 638 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 639 | struct acpi_processor_performance *perf; |
8cee1eed | 640 | struct cpufreq_frequency_table *freq_table; |
293afe44 JV |
641 | #ifdef CONFIG_SMP |
642 | static int blacklisted; | |
643 | #endif | |
1da177e4 | 644 | |
eae2ef0e | 645 | pr_debug("%s\n", __func__); |
1da177e4 | 646 | |
1a8e42fa | 647 | #ifdef CONFIG_SMP |
293afe44 JV |
648 | if (blacklisted) |
649 | return blacklisted; | |
650 | blacklisted = acpi_cpufreq_blacklist(c); | |
651 | if (blacklisted) | |
652 | return blacklisted; | |
1a8e42fa PB |
653 | #endif |
654 | ||
d5b73cd8 | 655 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 656 | if (!data) |
64be7eed | 657 | return -ENOMEM; |
1da177e4 | 658 | |
f4fd3797 LT |
659 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
660 | result = -ENOMEM; | |
661 | goto err_free; | |
662 | } | |
663 | ||
3427616b | 664 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 665 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 666 | policy->driver_data = data; |
1da177e4 | 667 | |
95dd7227 | 668 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 669 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 670 | |
3427616b | 671 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 672 | if (result) |
f4fd3797 | 673 | goto err_free_mask; |
1da177e4 | 674 | |
09b4d1ee | 675 | policy->shared_type = perf->shared_type; |
95dd7227 | 676 | |
46f18e3a | 677 | /* |
95dd7227 | 678 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
679 | * coordination is required. |
680 | */ | |
681 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 682 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 683 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 684 | } |
f4fd3797 | 685 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
686 | |
687 | #ifdef CONFIG_SMP | |
688 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 689 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 690 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 691 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 692 | } |
acd31624 AP |
693 | |
694 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
695 | cpumask_clear(policy->cpus); | |
696 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
697 | cpumask_copy(data->freqdomain_cpus, |
698 | topology_sibling_cpumask(cpu)); | |
acd31624 | 699 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
1c5864e2 | 700 | pr_info_once("overriding BIOS provided _PSD data\n"); |
acd31624 | 701 | } |
8adcc0c6 | 702 | #endif |
09b4d1ee | 703 | |
1da177e4 | 704 | /* capability check */ |
09b4d1ee | 705 | if (perf->state_count <= 1) { |
2d06d8c4 | 706 | pr_debug("No P-States\n"); |
1da177e4 LT |
707 | result = -ENODEV; |
708 | goto err_unreg; | |
709 | } | |
09b4d1ee | 710 | |
fe27cb35 VP |
711 | if (perf->control_register.space_id != perf->status_register.space_id) { |
712 | result = -ENODEV; | |
713 | goto err_unreg; | |
714 | } | |
715 | ||
716 | switch (perf->control_register.space_id) { | |
64be7eed | 717 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
718 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
719 | boot_cpu_data.x86 == 0xf) { | |
720 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
721 | result = -ENODEV; | |
722 | goto err_unreg; | |
723 | } | |
2d06d8c4 | 724 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 725 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
726 | data->cpu_freq_read = cpu_freq_read_io; |
727 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 728 | break; |
64be7eed | 729 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 730 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
731 | if (check_est_cpu(cpu)) { |
732 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
733 | data->cpu_freq_read = cpu_freq_read_intel; |
734 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 735 | break; |
dde9f7ba | 736 | } |
3dc9a633 MG |
737 | if (check_amd_hwpstate_cpu(cpu)) { |
738 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
739 | data->cpu_freq_read = cpu_freq_read_amd; |
740 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
741 | break; |
742 | } | |
743 | result = -ENODEV; | |
744 | goto err_unreg; | |
64be7eed | 745 | default: |
2d06d8c4 | 746 | pr_debug("Unknown addr space %d\n", |
64be7eed | 747 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
748 | result = -ENODEV; |
749 | goto err_unreg; | |
750 | } | |
751 | ||
6396bb22 KC |
752 | freq_table = kcalloc(perf->state_count + 1, sizeof(*freq_table), |
753 | GFP_KERNEL); | |
8cee1eed | 754 | if (!freq_table) { |
1da177e4 LT |
755 | result = -ENOMEM; |
756 | goto err_unreg; | |
757 | } | |
758 | ||
759 | /* detect transition latency */ | |
760 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 761 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
762 | if ((perf->states[i].transition_latency * 1000) > |
763 | policy->cpuinfo.transition_latency) | |
764 | policy->cpuinfo.transition_latency = | |
765 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 766 | } |
1da177e4 | 767 | |
a59d1637 PV |
768 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
769 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
770 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 771 | policy->cpuinfo.transition_latency = 20 * 1000; |
b49c22a6 | 772 | pr_info_once("P-state transition latency capped at 20 uS\n"); |
a59d1637 PV |
773 | } |
774 | ||
1da177e4 | 775 | /* table init */ |
3a58df35 DJ |
776 | for (i = 0; i < perf->state_count; i++) { |
777 | if (i > 0 && perf->states[i].core_frequency >= | |
8cee1eed | 778 | freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
779 | continue; |
780 | ||
8cee1eed VK |
781 | freq_table[valid_states].driver_data = i; |
782 | freq_table[valid_states].frequency = | |
64be7eed | 783 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 784 | valid_states++; |
1da177e4 | 785 | } |
8cee1eed | 786 | freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
1a186d9e | 787 | policy->freq_table = freq_table; |
8edc59d9 | 788 | perf->state = 0; |
1da177e4 | 789 | |
a507ac4b | 790 | switch (perf->control_register.space_id) { |
64be7eed | 791 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
792 | /* |
793 | * The core will not set policy->cur, because | |
794 | * cpufreq_driver->get is NULL, so we need to set it here. | |
795 | * However, we have to guess it, because the current speed is | |
796 | * unknown and not detectable via IO ports. | |
797 | */ | |
dde9f7ba VP |
798 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
799 | break; | |
64be7eed | 800 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 801 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 802 | break; |
64be7eed | 803 | default: |
dde9f7ba VP |
804 | break; |
805 | } | |
806 | ||
1da177e4 LT |
807 | /* notify BIOS that we exist */ |
808 | acpi_processor_notify_smm(THIS_MODULE); | |
809 | ||
2d06d8c4 | 810 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 811 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 812 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 813 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
814 | (u32) perf->states[i].core_frequency, |
815 | (u32) perf->states[i].power, | |
816 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 817 | |
4b31e774 DB |
818 | /* |
819 | * the first call to ->target() should result in us actually | |
820 | * writing something to the appropriate registers. | |
821 | */ | |
822 | data->resume = 1; | |
64be7eed | 823 | |
b7898fda RW |
824 | policy->fast_switch_possible = !acpi_pstate_strict && |
825 | !(policy_is_shared(policy) && policy->shared_type != CPUFREQ_SHARED_TYPE_ANY); | |
826 | ||
fe27cb35 | 827 | return result; |
1da177e4 | 828 | |
95dd7227 | 829 | err_unreg: |
b2f8dc4c | 830 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
831 | err_free_mask: |
832 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 833 | err_free: |
1da177e4 | 834 | kfree(data); |
eb0b3e78 | 835 | policy->driver_data = NULL; |
1da177e4 | 836 | |
64be7eed | 837 | return result; |
1da177e4 LT |
838 | } |
839 | ||
64be7eed | 840 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 841 | { |
eb0b3e78 | 842 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 843 | |
eae2ef0e | 844 | pr_debug("%s\n", __func__); |
1da177e4 | 845 | |
9b55f55a VK |
846 | policy->fast_switch_possible = false; |
847 | policy->driver_data = NULL; | |
848 | acpi_processor_unregister_performance(data->acpi_perf_cpu); | |
849 | free_cpumask_var(data->freqdomain_cpus); | |
8cee1eed | 850 | kfree(policy->freq_table); |
9b55f55a | 851 | kfree(data); |
1da177e4 | 852 | |
64be7eed | 853 | return 0; |
1da177e4 LT |
854 | } |
855 | ||
1a186d9e VK |
856 | static void acpi_cpufreq_cpu_ready(struct cpufreq_policy *policy) |
857 | { | |
858 | struct acpi_processor_performance *perf = per_cpu_ptr(acpi_perf_data, | |
859 | policy->cpu); | |
860 | ||
861 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) | |
862 | pr_warn(FW_WARN "P-state 0 is not max freq\n"); | |
863 | } | |
864 | ||
64be7eed | 865 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 866 | { |
eb0b3e78 | 867 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 868 | |
eae2ef0e | 869 | pr_debug("%s\n", __func__); |
1da177e4 LT |
870 | |
871 | data->resume = 1; | |
872 | ||
64be7eed | 873 | return 0; |
1da177e4 LT |
874 | } |
875 | ||
64be7eed | 876 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 877 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 878 | &freqdomain_cpus, |
f56c50e3 RW |
879 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
880 | &cpb, | |
881 | #endif | |
1da177e4 LT |
882 | NULL, |
883 | }; | |
884 | ||
885 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 886 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 887 | .target_index = acpi_cpufreq_target, |
b7898fda | 888 | .fast_switch = acpi_cpufreq_fast_switch, |
e2f74f35 TR |
889 | .bios_limit = acpi_processor_get_bios_limit, |
890 | .init = acpi_cpufreq_cpu_init, | |
891 | .exit = acpi_cpufreq_cpu_exit, | |
1a186d9e | 892 | .ready = acpi_cpufreq_cpu_ready, |
e2f74f35 TR |
893 | .resume = acpi_cpufreq_resume, |
894 | .name = "acpi-cpufreq", | |
e2f74f35 | 895 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
896 | }; |
897 | ||
4d66ddf2 SAS |
898 | static enum cpuhp_state acpi_cpufreq_online; |
899 | ||
615b7300 AP |
900 | static void __init acpi_cpufreq_boost_init(void) |
901 | { | |
4d66ddf2 | 902 | int ret; |
615b7300 | 903 | |
1222d527 EV |
904 | if (!(boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA))) { |
905 | pr_debug("Boost capabilities not present in the processor\n"); | |
4d66ddf2 | 906 | return; |
1222d527 | 907 | } |
0197fbd2 | 908 | |
4d66ddf2 SAS |
909 | acpi_cpufreq_driver.set_boost = set_boost; |
910 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
615b7300 | 911 | |
4d66ddf2 SAS |
912 | /* |
913 | * This calls the online callback on all online cpu and forces all | |
914 | * MSRs to the same value. | |
915 | */ | |
916 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "cpufreq/acpi:online", | |
917 | cpufreq_boost_online, cpufreq_boost_down_prep); | |
918 | if (ret < 0) { | |
919 | pr_err("acpi_cpufreq: failed to register hotplug callbacks\n"); | |
4d66ddf2 | 920 | return; |
cfc9c8ed | 921 | } |
4d66ddf2 | 922 | acpi_cpufreq_online = ret; |
615b7300 AP |
923 | } |
924 | ||
eb8c68ef | 925 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 926 | { |
2a8fa123 | 927 | if (acpi_cpufreq_online > 0) |
4d66ddf2 | 928 | cpuhp_remove_state_nocalls(acpi_cpufreq_online); |
615b7300 AP |
929 | } |
930 | ||
64be7eed | 931 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 932 | { |
50109292 FY |
933 | int ret; |
934 | ||
75c07581 RW |
935 | if (acpi_disabled) |
936 | return -ENODEV; | |
937 | ||
8a61e12e YL |
938 | /* don't keep reloading if cpufreq_driver exists */ |
939 | if (cpufreq_get_current_driver()) | |
75c07581 | 940 | return -EEXIST; |
ee297533 | 941 | |
eae2ef0e | 942 | pr_debug("%s\n", __func__); |
1da177e4 | 943 | |
50109292 FY |
944 | ret = acpi_cpufreq_early_init(); |
945 | if (ret) | |
946 | return ret; | |
09b4d1ee | 947 | |
11269ff5 AP |
948 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
949 | /* this is a sysfs file with a strange name and an even stranger | |
950 | * semantic - per CPU instantiation, but system global effect. | |
951 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
952 | * only if configured. This is considered legacy code, which | |
953 | * will probably be removed at some point in the future. | |
954 | */ | |
f56c50e3 RW |
955 | if (!check_amd_hwpstate_cpu(0)) { |
956 | struct freq_attr **attr; | |
11269ff5 | 957 | |
f56c50e3 | 958 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 959 | |
f56c50e3 RW |
960 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
961 | if (*attr == &cpb) { | |
962 | *attr = NULL; | |
963 | break; | |
964 | } | |
11269ff5 AP |
965 | } |
966 | #endif | |
cfc9c8ed | 967 | acpi_cpufreq_boost_init(); |
11269ff5 | 968 | |
847aef6f | 969 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 970 | if (ret) { |
2fdf66b4 | 971 | free_acpi_perf_data(); |
eb8c68ef KRW |
972 | acpi_cpufreq_boost_exit(); |
973 | } | |
847aef6f | 974 | return ret; |
1da177e4 LT |
975 | } |
976 | ||
64be7eed | 977 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 978 | { |
eae2ef0e | 979 | pr_debug("%s\n", __func__); |
1da177e4 | 980 | |
615b7300 AP |
981 | acpi_cpufreq_boost_exit(); |
982 | ||
1da177e4 LT |
983 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
984 | ||
50f4ddd4 | 985 | free_acpi_perf_data(); |
1da177e4 LT |
986 | } |
987 | ||
d395bf12 | 988 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 989 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
990 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
991 | "performed during frequency changes."); | |
1da177e4 LT |
992 | |
993 | late_initcall(acpi_cpufreq_init); | |
994 | module_exit(acpi_cpufreq_exit); | |
995 | ||
efa17194 | 996 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
b11d77fa TG |
997 | X86_MATCH_FEATURE(X86_FEATURE_ACPI, NULL), |
998 | X86_MATCH_FEATURE(X86_FEATURE_HW_PSTATE, NULL), | |
efa17194 MG |
999 | {} |
1000 | }; | |
1001 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1002 | ||
c655affb RW |
1003 | static const struct acpi_device_id processor_device_ids[] = { |
1004 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1005 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1006 | {}, | |
1007 | }; | |
1008 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1009 | ||
1da177e4 | 1010 | MODULE_ALIAS("acpi"); |